7453645f2a
All devices: - add support for rate adaptation via ieee80211_amrr(9); - use short preamble for transmitted frames when needed; - multi-bss support: * for RTL8821AU: 2 VAPs at the same time; * other: 1 any VAP + 1 sta VAP. RTL8188CE: - fix IQ calibration bug (reason of significant speed degradation); - add h/w crypto acceleration support. USB: - A-MPDU Tx support; - short GI support; Other: - add support for RTL8812AU / RTL8821AU chipsets (a/b/g/n only; no ac yet); - split merged code into subparts: * bus glue (usb/*, pci/*, rtl*/usb/*, rtl*/pci/*) * common (if_rtwn*) * chip-specific (rtl*/*) - various other bugfixes. Due to code reorganization, module names / requirements were changed too: urtwn urtwnfw -> rtwn rtwn_usb rtwnfw rtwn rtwnfw -> rtwn rtwn_pci rtwnfw Tested with RTL8188CE, RTL8188CUS, RTL8188EU and RTL8821AU. Tested by: kevlo, garga, Peter Garshtja <peter.garshtja@ambient-md.com>, Kevin McAleavey <kevin.mcaleavey@knosproject.com>, Ilias-Dimitrios Vrachnis <id@vrachnis.com>, <otacilio.neto@bsd.com.br> Relnotes: yes
123 lines
3.8 KiB
C
123 lines
3.8 KiB
C
/*-
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* Copyright (c) 2010 Damien Bergamini <damien.bergamini@free.fr>
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* Copyright (c) 2016 Andriy Voskoboinyk <avos@FreeBSD.org>
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*
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* Permission to use, copy, modify, and distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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* $OpenBSD: if_urtwnreg.h,v 1.3 2010/11/16 18:02:59 damien Exp $
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* $FreeBSD$
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*/
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#ifndef R92C_TX_DESC_H
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#define R92C_TX_DESC_H
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/* Tx MAC descriptor (common part). */
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struct r92c_tx_desc {
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uint16_t pktlen;
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uint8_t offset;
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uint8_t flags0;
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#define R92C_FLAGS0_BMCAST 0x01
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#define R92C_FLAGS0_LSG 0x04
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#define R92C_FLAGS0_FSG 0x08
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#define R92C_FLAGS0_OWN 0x80
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uint32_t txdw1;
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#define R92C_TXDW1_MACID_M 0x0000001f
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#define R92C_TXDW1_MACID_S 0
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#define R92C_TXDW1_AGGEN 0x00000020
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#define R92C_TXDW1_AGGBK 0x00000040
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#define R92C_TXDW1_QSEL_M 0x00001f00
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#define R92C_TXDW1_QSEL_S 8
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#define R92C_TXDW1_QSEL_BE 0x00 /* or 0x03 */
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#define R92C_TXDW1_QSEL_BK 0x01 /* or 0x02 */
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#define R92C_TXDW1_QSEL_VI 0x04 /* or 0x05 */
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#define R92C_TXDW1_QSEL_VO 0x06 /* or 0x07 */
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#define RTWN_MAX_TID 8
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#define R92C_TXDW1_QSEL_BEACON 0x10
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#define R92C_TXDW1_QSEL_MGNT 0x12
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#define R92C_TXDW1_RAID_M 0x000f0000
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#define R92C_TXDW1_RAID_S 16
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#define R92C_TXDW1_CIPHER_M 0x00c00000
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#define R92C_TXDW1_CIPHER_S 22
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#define R92C_TXDW1_CIPHER_NONE 0
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#define R92C_TXDW1_CIPHER_RC4 1
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#define R92C_TXDW1_CIPHER_AES 3
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#define R92C_TXDW1_PKTOFF_M 0x7c000000
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#define R92C_TXDW1_PKTOFF_S 26
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uint32_t txdw2;
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#define R92C_TXDW2_CCX_RPT 0x00080000
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#define R92C_TXDW2_AMPDU_DEN_M 0x00700000
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#define R92C_TXDW2_AMPDU_DEN_S 20
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uint16_t txdw3;
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uint16_t txdseq;
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uint32_t txdw4;
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#define R92C_TXDW4_RTSRATE_M 0x0000003f
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#define R92C_TXDW4_RTSRATE_S 0
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#define R92C_TXDW4_SEQ_SEL_M 0x00000040
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#define R92C_TXDW4_SEQ_SEL_S 6
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#define R92C_TXDW4_HWSEQ_EN 0x00000080
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#define R92C_TXDW4_DRVRATE 0x00000100
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#define R92C_TXDW4_CTS2SELF 0x00000800
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#define R92C_TXDW4_RTSEN 0x00001000
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#define R92C_TXDW4_HWRTSEN 0x00002000
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#define R92C_TXDW4_PORT_ID_M 0x00004000
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#define R92C_TXDW4_PORT_ID_S 14
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#define R92C_TXDW4_DATA_SCO_M 0x00300000
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#define R92C_TXDW4_DATA_SCO_S 20
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#define R92C_TXDW4_SCO_SCA 1
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#define R92C_TXDW4_SCO_SCB 2
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#define R92C_TXDW4_DATA_SHPRE 0x01000000
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#define R92C_TXDW4_DATA_BW40 0x02000000
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#define R92C_TXDW4_RTS_SHORT 0x04000000
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#define R92C_TXDW4_RTS_BW40 0x08000000
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#define R92C_TXDW4_RTS_SCO_M 0x30000000
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#define R92C_TXDW4_RTS_SCO_S 28
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uint32_t txdw5;
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#define R92C_TXDW5_DATARATE_M 0x0000003f
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#define R92C_TXDW5_DATARATE_S 0
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#define R92C_TXDW5_SGI 0x00000040
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#define R92C_TXDW5_DATARATE_FB_LMT_M 0x00001f00
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#define R92C_TXDW5_DATARATE_FB_LMT_S 8
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#define R92C_TXDW5_RTSRATE_FB_LMT_M 0x0001e000
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#define R92C_TXDW5_RTSRATE_FB_LMT_S 13
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#define R92C_TXDW5_RTY_LMT_ENA 0x00020000
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#define R92C_TXDW5_RTY_LMT_M 0x00fc0000
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#define R92C_TXDW5_RTY_LMT_S 18
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#define R92C_TXDW5_AGGNUM_M 0xff000000
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#define R92C_TXDW5_AGGNUM_S 24
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uint32_t txdw6;
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#define R92C_TXDW6_MAX_AGG_M 0x0000f800
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#define R92C_TXDW6_MAX_AGG_S 11
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} __packed __attribute__((aligned(4)));
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/* Rate adaptation modes. */
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#define R92C_RAID_11BGN 0
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#define R92C_RAID_11GN 1
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#define R92C_RAID_11BN 2
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#define R92C_RAID_11N 3
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#define R92C_RAID_11BG 4
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#define R92C_RAID_11G 5 /* "pure" 11g */
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#define R92C_RAID_11B 6
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#endif /* R92C_TX_DESC_H */
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