267 lines
6.8 KiB
C
267 lines
6.8 KiB
C
/*-
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* Copyright (c) 2018-2020 Ruslan Bukin <br@bsdpad.com>
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* All rights reserved.
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*
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* This software was developed by BAE Systems, the University of Cambridge
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* Computer Laboratory, and Memorial University under DARPA/AFRL contract
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* FA8650-15-C-7558 ("CADETS"), as part of the DARPA Transparent Computing
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* (TC) research program.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/rman.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <machine/bus.h>
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#include <arm64/coresight/coresight.h>
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#include <arm64/coresight/coresight_etm4x.h>
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#include "coresight_if.h"
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#define ETM_DEBUG
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#undef ETM_DEBUG
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#ifdef ETM_DEBUG
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#define dprintf(fmt, ...) printf(fmt, ##__VA_ARGS__)
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#else
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#define dprintf(fmt, ...)
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#endif
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/*
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* Typical trace flow:
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*
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* CPU0 -> ETM0 -> funnel1 -> funnel0 -> ETF -> replicator -> ETR -> DRAM
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* CPU1 -> ETM1 -> funnel1 -^
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* CPU2 -> ETM2 -> funnel1 -^
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* CPU3 -> ETM3 -> funnel1 -^
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*/
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static struct resource_spec etm_spec[] = {
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{ SYS_RES_MEMORY, 0, RF_ACTIVE },
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{ -1, 0 }
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};
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static int
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etm_prepare(device_t dev, struct coresight_event *event)
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{
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struct etm_softc *sc;
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uint32_t reg;
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int i;
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sc = device_get_softc(dev);
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/* Configure ETM */
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/*
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* Enable the return stack, global timestamping,
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* Context ID, and Virtual context identifier tracing.
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*/
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reg = TRCCONFIGR_RS | TRCCONFIGR_TS;
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reg |= TRCCONFIGR_CID | TRCCONFIGR_VMID;
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reg |= TRCCONFIGR_INSTP0_LDRSTR;
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reg |= TRCCONFIGR_COND_ALL;
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bus_write_4(sc->res, TRCCONFIGR, reg);
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/* Disable all event tracing. */
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bus_write_4(sc->res, TRCEVENTCTL0R, 0);
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bus_write_4(sc->res, TRCEVENTCTL1R, 0);
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/* Disable stalling, if implemented. */
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bus_write_4(sc->res, TRCSTALLCTLR, 0);
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/* Enable trace synchronization every 4096 bytes of trace. */
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bus_write_4(sc->res, TRCSYNCPR, TRCSYNCPR_4K);
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/* Set a value for the trace ID */
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bus_write_4(sc->res, TRCTRACEIDR, event->etm.trace_id);
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/*
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* Disable the timestamp event. The trace unit still generates
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* timestamps due to other reasons such as trace synchronization.
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*/
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bus_write_4(sc->res, TRCTSCTLR, 0);
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/*
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* Enable ViewInst to trace everything, with the start/stop
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* logic started.
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*/
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reg = TRCVICTLR_SSSTATUS;
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/* The number of the single resource used to activate the event. */
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reg |= (1 << EVENT_SEL_S);
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if (event->excp_level > 2)
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return (-1);
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reg |= TRCVICTLR_EXLEVEL_NS_M;
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reg &= ~TRCVICTLR_EXLEVEL_NS(event->excp_level);
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reg |= TRCVICTLR_EXLEVEL_S_M;
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reg &= ~TRCVICTLR_EXLEVEL_S(event->excp_level);
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bus_write_4(sc->res, TRCVICTLR, reg);
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for (i = 0; i < event->naddr * 2; i++) {
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dprintf("configure range %d, address %lx\n",
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i, event->addr[i]);
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bus_write_8(sc->res, TRCACVR(i), event->addr[i]);
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reg = 0;
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/* Secure state */
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reg |= TRCACATR_EXLEVEL_S_M;
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reg &= ~TRCACATR_EXLEVEL_S(event->excp_level);
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/* Non-secure state */
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reg |= TRCACATR_EXLEVEL_NS_M;
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reg &= ~TRCACATR_EXLEVEL_NS(event->excp_level);
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bus_write_4(sc->res, TRCACATR(i), reg);
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/* Address range is included */
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reg = bus_read_4(sc->res, TRCVIIECTLR);
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reg |= (1 << (TRCVIIECTLR_INCLUDE_S + i / 2));
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bus_write_4(sc->res, TRCVIIECTLR, reg);
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}
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/* No address filtering for ViewData. */
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bus_write_4(sc->res, TRCVDARCCTLR, 0);
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/* Clear the STATUS bit to zero */
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bus_write_4(sc->res, TRCSSCSR(0), 0);
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if (event->naddr == 0) {
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/* No address range filtering for ViewInst. */
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bus_write_4(sc->res, TRCVIIECTLR, 0);
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}
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/* No start or stop points for ViewInst. */
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bus_write_4(sc->res, TRCVISSCTLR, 0);
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/* Disable ViewData */
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bus_write_4(sc->res, TRCVDCTLR, 0);
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/* No address filtering for ViewData. */
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bus_write_4(sc->res, TRCVDSACCTLR, 0);
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return (0);
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}
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static int
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etm_init(device_t dev)
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{
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struct etm_softc *sc;
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uint32_t reg __unused;
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sc = device_get_softc(dev);
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/* Unlocking Coresight */
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bus_write_4(sc->res, CORESIGHT_LAR, CORESIGHT_UNLOCK);
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/* Unlocking ETM */
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bus_write_4(sc->res, TRCOSLAR, 0);
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reg = bus_read_4(sc->res, TRCIDR(1));
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dprintf("ETM Version: %d.%d\n",
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(reg & TRCIDR1_TRCARCHMAJ_M) >> TRCIDR1_TRCARCHMAJ_S,
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(reg & TRCIDR1_TRCARCHMIN_M) >> TRCIDR1_TRCARCHMIN_S);
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return (0);
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}
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static int
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etm_enable(device_t dev, struct endpoint *endp,
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struct coresight_event *event)
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{
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struct etm_softc *sc;
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uint32_t reg;
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sc = device_get_softc(dev);
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etm_prepare(dev, event);
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/* Enable the trace unit */
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bus_write_4(sc->res, TRCPRGCTLR, TRCPRGCTLR_EN);
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/* Wait for an IDLE bit to be LOW */
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do {
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reg = bus_read_4(sc->res, TRCSTATR);
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} while ((reg & TRCSTATR_IDLE) == 1);
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if ((bus_read_4(sc->res, TRCPRGCTLR) & TRCPRGCTLR_EN) == 0)
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panic("etm is not enabled\n");
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return (0);
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}
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static void
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etm_disable(device_t dev, struct endpoint *endp,
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struct coresight_event *event)
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{
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struct etm_softc *sc;
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uint32_t reg;
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sc = device_get_softc(dev);
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/* Disable the trace unit */
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bus_write_4(sc->res, TRCPRGCTLR, 0);
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/* Wait for an IDLE bit */
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do {
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reg = bus_read_4(sc->res, TRCSTATR);
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} while ((reg & TRCSTATR_IDLE) == 0);
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}
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int
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etm_attach(device_t dev)
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{
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struct coresight_desc desc;
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struct etm_softc *sc;
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sc = device_get_softc(dev);
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if (bus_alloc_resources(dev, etm_spec, &sc->res) != 0) {
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device_printf(dev, "cannot allocate resources for device\n");
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return (ENXIO);
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}
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desc.pdata = sc->pdata;
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desc.dev = dev;
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desc.dev_type = CORESIGHT_ETMV4;
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coresight_register(&desc);
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return (0);
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}
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static device_method_t etm_methods[] = {
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/* Coresight interface */
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DEVMETHOD(coresight_init, etm_init),
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DEVMETHOD(coresight_enable, etm_enable),
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DEVMETHOD(coresight_disable, etm_disable),
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DEVMETHOD_END
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};
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DEFINE_CLASS_0(etm, etm_driver, etm_methods, sizeof(struct etm_softc));
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