422 lines
16 KiB
C
422 lines
16 KiB
C
/*-
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* Copyright (c) 1999 Doug Rabson
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* Copyright (c) 1997 Luigi Rizzo
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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/*
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* This file contains information and macro definitions for
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* AD1848-compatible devices, used in the MSS/WSS compatible boards.
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*/
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/*
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*
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The codec part of the board is seen as a set of 4 registers mapped
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at the base address for the board (default 0x534). Note that some
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(early) boards implemented 4 additional registers 4 location before
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(usually 0x530) to store configuration information. This is a source
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of confusion in that one never knows what address to specify. The
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(current) convention is to use the old address (0x530) in the kernel
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configuration file and consider MSS registers start four location
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ahead.
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*
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*/
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struct mixer_def {
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u_int regno:7;
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u_int polarity:1; /* 1 means reversed */
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u_int bitoffs:4;
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u_int nbits:4;
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};
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typedef struct mixer_def mixer_ent;
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typedef struct mixer_def mixer_tab[32][2];
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#define MIX_ENT(name, reg_l, pol_l, pos_l, len_l, reg_r, pol_r, pos_r, len_r) \
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{{reg_l, pol_l, pos_l, len_l}, {reg_r, pol_r, pos_r, len_r}}
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#define PMIX_ENT(name, reg_l, pos_l, len_l, reg_r, pos_r, len_r) \
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{{reg_l, 0, pos_l, len_l}, {reg_r, 0, pos_r, len_r}}
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#define MIX_NONE(name) MIX_ENT(name, 0,0,0,0, 0,0,0,0)
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/*
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* The four visible registers of the MSS :
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*
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*/
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#define MSS_INDEX (0 + 4)
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#define MSS_IDXBUSY 0x80 /* readonly, set when busy */
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#define MSS_MCE 0x40 /* the MCE bit. */
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/*
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* the MCE bit must be set whenever the current mode of the
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* codec is changed; this in particular is true for the
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* Data Format (I8, I28) and Interface Config(I9) registers.
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* Only exception are CEN and PEN which can be changed on the fly.
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* The DAC output is muted when MCE is set.
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*/
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#define MSS_TRD 0x20 /* Transfer request disable */
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/*
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* When TRD is set, DMA transfers cease when the INT bit in
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* the MSS status reg is set. Must be cleared for automode
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* DMA, set otherwise.
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*/
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#define MSS_IDXMASK 0x1f /* mask for indirect address */
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#define MSS_IDATA (1 + 4)
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/*
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* data to be transferred to the indirect register addressed
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* by index addr. During init and sw. powerdown, cannot be
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* written to, and is always read as 0x80 (consistent with the
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* busy flag).
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*/
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#define MSS_STATUS (2 + 4)
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#define IS_CUL 0x80 /* capture upper/lower */
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#define IS_CLR 0x40 /* capture left/right */
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#define IS_CRDY 0x20 /* capture ready for programmed i/o */
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#define IS_SER 0x10 /* sample error (overrun/underrun) */
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#define IS_PUL 0x08 /* playback upper/lower */
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#define IS_PLR 0x04 /* playback left/right */
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#define IS_PRDY 0x02 /* playback ready for programmed i/o */
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#define IS_INT 0x01 /* int status (1 = active) */
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/*
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* IS_INT is clreared by any write to the status register.
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*/
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#if 0
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#define io_Polled_IO(d) ((d)->io_base+3+4)
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/*
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* this register is used in case of polled i/o
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*/
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#endif
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/*
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* The MSS has a set of 16 (or 32 depending on the model) indirect
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* registers accessible through the data port by specifying the
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* appropriate address in the address register.
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*
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* The 16 low registers are uniformly handled in AD1848/CS4248 compatible
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* mode (often called MODE1). For the upper 16 registers there are
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* some differences among different products, mainly Crystal uses them
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* differently from OPTi.
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*
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*/
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/*
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* volume registers
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*/
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#define I6_MUTE 0x80
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/*
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* register I9 -- interface configuration.
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*/
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#define I9_PEN 0x01 /* playback enable */
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#define I9_CEN 0x02 /* capture enable */
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/*
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* values used in bd_flags
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*/
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#define BD_F_MCE_BIT 0x0001
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#define BD_F_IRQ_OK 0x0002
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#define BD_F_TMR_RUN 0x0004
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#define BD_F_MSS_OFFSET 0x0008 /* offset mss writes by -4 */
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#define BD_F_DUPLEX 0x0010
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#define BD_F_924PNP 0x0020 /* OPTi924 is in PNP mode */
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/*
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* sound/ad1848_mixer.h
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*
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* Definitions for the mixer of AD1848 and compatible codecs.
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*
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* Copyright by Hannu Savolainen 1994
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer. 2.
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY
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* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/*
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* The AD1848 codec has generic input lines called Line, Aux1 and Aux2.
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* Soundcard manufacturers have connected actual inputs (CD, synth, line,
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* etc) to these inputs in different order. Therefore it's difficult
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* to assign mixer channels to to these inputs correctly. The following
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* contains two alternative mappings. The first one is for GUS MAX and
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* the second is just a generic one (line1, line2 and line3).
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* (Actually this is not a mapping but rather some kind of interleaving
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* solution).
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*/
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#define MSS_REC_DEVICES \
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(SOUND_MASK_LINE | SOUND_MASK_MIC | SOUND_MASK_CD|SOUND_MASK_IMIX)
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/*
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* Table of mixer registers. There is a default table for the
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* AD1848/CS423x clones, one for the OPTI931 and one for the
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* OPTi930. As more MSS clones come out, there ought to be
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* more tables.
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*
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* Fields in the table are : polarity, register, offset, bits
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*
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* The channel numbering used by individual soundcards is not fixed.
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* Some cards have assigned different meanings for the AUX1, AUX2
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* and LINE inputs. Some have different features...
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*
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* Following there is a macro ...MIXER_DEVICES which is a bitmap
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* of all non-zero fields in the table.
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* MODE1_MIXER_DEVICES is the basic mixer of the 1848 in mode 1
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* registers I0..I15)
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*
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*/
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mixer_ent mix_devices[32][2] = {
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MIX_NONE(SOUND_MIXER_VOLUME),
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MIX_NONE(SOUND_MIXER_BASS),
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MIX_NONE(SOUND_MIXER_TREBLE),
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#ifdef PC98 /* PC98's synth is assigned to AUX#2 */
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MIX_ENT(SOUND_MIXER_SYNTH, 4, 1, 0, 5, 5, 1, 0, 5),
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#else /* AT386's synth is assigned to AUX#1 */
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MIX_ENT(SOUND_MIXER_SYNTH, 2, 1, 0, 5, 3, 1, 0, 5),
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#endif
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MIX_ENT(SOUND_MIXER_PCM, 6, 1, 0, 6, 7, 1, 0, 6),
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MIX_ENT(SOUND_MIXER_SPEAKER, 26, 1, 0, 4, 0, 0, 0, 0),
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MIX_ENT(SOUND_MIXER_LINE, 18, 1, 0, 5, 19, 1, 0, 5),
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MIX_ENT(SOUND_MIXER_MIC, 0, 0, 5, 1, 1, 0, 5, 1),
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#ifdef PC98 /* PC98's cd-audio is assigned to AUX#1 */
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MIX_ENT(SOUND_MIXER_CD, 2, 1, 0, 5, 3, 1, 0, 5),
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#else /* AT386's cd-audio is assigned to AUX#2 */
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MIX_ENT(SOUND_MIXER_CD, 4, 1, 0, 5, 5, 1, 0, 5),
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#endif
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MIX_ENT(SOUND_MIXER_IMIX, 13, 1, 2, 6, 0, 0, 0, 0),
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MIX_NONE(SOUND_MIXER_ALTPCM),
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MIX_NONE(SOUND_MIXER_RECLEV),
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MIX_ENT(SOUND_MIXER_IGAIN, 0, 0, 0, 4, 1, 0, 0, 4),
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MIX_NONE(SOUND_MIXER_OGAIN),
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MIX_NONE(SOUND_MIXER_LINE1),
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MIX_NONE(SOUND_MIXER_LINE2),
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MIX_NONE(SOUND_MIXER_LINE3),
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};
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#define MODE2_MIXER_DEVICES \
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(SOUND_MASK_SYNTH | SOUND_MASK_PCM | SOUND_MASK_SPEAKER | \
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SOUND_MASK_LINE | SOUND_MASK_MIC | SOUND_MASK_CD | \
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SOUND_MASK_IMIX | SOUND_MASK_IGAIN )
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#define MODE1_MIXER_DEVICES \
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(SOUND_MASK_SYNTH | SOUND_MASK_PCM | SOUND_MASK_MIC | \
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SOUND_MASK_CD | SOUND_MASK_IMIX | SOUND_MASK_IGAIN )
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mixer_ent opti930_devices[32][2] = {
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MIX_ENT(SOUND_MIXER_VOLUME, 22, 1, 0, 4, 23, 1, 0, 4),
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MIX_NONE(SOUND_MIXER_BASS),
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MIX_NONE(SOUND_MIXER_TREBLE),
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MIX_ENT(SOUND_MIXER_SYNTH, 4, 1, 0, 4, 5, 1, 0, 4),
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MIX_ENT(SOUND_MIXER_PCM, 6, 1, 1, 5, 7, 1, 1, 5),
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MIX_ENT(SOUND_MIXER_LINE, 18, 1, 1, 4, 19, 1, 1, 4),
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MIX_NONE(SOUND_MIXER_SPEAKER),
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MIX_ENT(SOUND_MIXER_MIC, 21, 1, 0, 4, 22, 1, 0, 4),
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MIX_ENT(SOUND_MIXER_CD, 2, 1, 1, 4, 3, 1, 1, 4),
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MIX_NONE(SOUND_MIXER_IMIX),
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MIX_NONE(SOUND_MIXER_ALTPCM),
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MIX_NONE(SOUND_MIXER_RECLEV),
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MIX_NONE(SOUND_MIXER_IGAIN),
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MIX_NONE(SOUND_MIXER_OGAIN),
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MIX_NONE(SOUND_MIXER_LINE1),
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MIX_NONE(SOUND_MIXER_LINE2),
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MIX_NONE(SOUND_MIXER_LINE3),
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};
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#define OPTI930_MIXER_DEVICES \
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(SOUND_MASK_VOLUME | SOUND_MASK_SYNTH | SOUND_MASK_PCM | \
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SOUND_MASK_LINE | SOUND_MASK_MIC | SOUND_MASK_CD )
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/*
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* entries for the opti931...
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*/
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mixer_ent opti931_devices[32][2] = { /* for the opti931 */
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MIX_ENT(SOUND_MIXER_VOLUME, 22, 1, 1, 5, 23, 1, 1, 5),
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MIX_NONE(SOUND_MIXER_BASS),
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MIX_NONE(SOUND_MIXER_TREBLE),
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MIX_ENT(SOUND_MIXER_SYNTH, 4, 1, 1, 4, 5, 1, 1, 4),
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MIX_ENT(SOUND_MIXER_PCM, 6, 1, 0, 5, 7, 1, 0, 5),
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MIX_NONE(SOUND_MIXER_SPEAKER),
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MIX_ENT(SOUND_MIXER_LINE, 18, 1, 1, 4, 19, 1, 1, 4),
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MIX_ENT(SOUND_MIXER_MIC, 0, 0, 5, 1, 1, 0, 5, 1),
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MIX_ENT(SOUND_MIXER_CD, 2, 1, 1, 4, 3, 1, 1, 4),
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MIX_NONE(SOUND_MIXER_IMIX),
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MIX_NONE(SOUND_MIXER_ALTPCM),
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MIX_NONE(SOUND_MIXER_RECLEV),
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MIX_ENT(SOUND_MIXER_IGAIN, 0, 0, 0, 4, 1, 0, 0, 4),
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MIX_NONE(SOUND_MIXER_OGAIN),
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MIX_ENT(SOUND_MIXER_LINE1, 16, 1, 1, 4, 17, 1, 1, 4),
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MIX_NONE(SOUND_MIXER_LINE2),
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MIX_NONE(SOUND_MIXER_LINE3),
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};
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#define OPTI931_MIXER_DEVICES \
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(SOUND_MASK_VOLUME | SOUND_MASK_SYNTH | SOUND_MASK_PCM | \
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SOUND_MASK_LINE | SOUND_MASK_MIC | SOUND_MASK_CD | \
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SOUND_MASK_IGAIN | SOUND_MASK_LINE1 )
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/*
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* Register definitions for the Yamaha OPL3-SA[23x].
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*/
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#define OPL3SAx_POWER 0x01 /* Power Management (R/W) */
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#define OPL3SAx_POWER_PDX 0x01 /* Set to 1 to halt oscillator */
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#define OPL3SAx_POWER_PDN 0x02 /* Set to 1 to power down */
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#define OPL3SAx_POWER_PSV 0x04 /* Set to 1 to power save */
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#define OPL3SAx_POWER_ADOWN 0x20 /* Analog power (?) */
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#define OPL3SAx_SYSTEM 0x02 /* System control (R/W) */
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#define OPL3SAx_SYSTEM_VZE 0x01 /* I2S audio routing */
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#define OPL3SAx_SYSTEM_IDSEL 0x03 /* SB compat version select */
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#define OPL3SAx_SYSTEM_SBHE 0x80 /* 0 for AT bus, 1 for XT bus */
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#define OPL3SAx_IRQCONF 0x03 /* Interrupt configuration (R/W */
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#define OPL3SAx_IRQCONF_WSSA 0x01 /* WSS interrupts through IRQA */
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#define OPL3SAx_IRQCONF_SBA 0x02 /* WSS interrupts through IRQA */
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#define OPL3SAx_IRQCONF_MPUA 0x04 /* WSS interrupts through IRQA */
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#define OPL3SAx_IRQCONF_OPL3A 0x08 /* WSS interrupts through IRQA */
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#define OPL3SAx_IRQCONF_WSSB 0x10 /* WSS interrupts through IRQB */
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#define OPL3SAx_IRQCONF_SBB 0x20 /* WSS interrupts through IRQB */
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#define OPL3SAx_IRQCONF_MPUB 0x40 /* WSS interrupts through IRQB */
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#define OPL3SAx_IRQCONF_OPL3B 0x80 /* WSS interrupts through IRQB */
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#define OPL3SAx_IRQSTATUSA 0x04 /* Interrupt (IRQ-A) Status (RO) */
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#define OPL3SAx_IRQSTATUSB 0x05 /* Interrupt (IRQ-B) Status (RO) */
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#define OPL3SAx_IRQSTATUS_PI 0x01 /* Playback Flag of CODEC */
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#define OPL3SAx_IRQSTATUS_CI 0x02 /* Recording Flag of CODEC */
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#define OPL3SAx_IRQSTATUS_TI 0x04 /* Timer Flag of CODEC */
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#define OPL3SAx_IRQSTATUS_SB 0x08 /* SB compat Playback Interrupt Flag */
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#define OPL3SAx_IRQSTATUS_MPU 0x10 /* MPU401 Interrupt Flag */
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#define OPL3SAx_IRQSTATUS_OPL3 0x20 /* Internal FM Timer Flag */
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#define OPL3SAx_IRQSTATUS_MV 0x40 /* HW Volume Interrupt Flag */
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#define OPL3SAx_IRQSTATUS_PI 0x01 /* Playback Flag of CODEC */
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#define OPL3SAx_IRQSTATUS_CI 0x02 /* Recording Flag of CODEC */
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#define OPL3SAx_IRQSTATUS_TI 0x04 /* Timer Flag of CODEC */
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#define OPL3SAx_IRQSTATUS_SB 0x08 /* SB compat Playback Interrupt Flag */
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#define OPL3SAx_IRQSTATUS_MPU 0x10 /* MPU401 Interrupt Flag */
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#define OPL3SAx_IRQSTATUS_OPL3 0x20 /* Internal FM Timer Flag */
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#define OPL3SAx_IRQSTATUS_MV 0x40 /* HW Volume Interrupt Flag */
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#define OPL3SAx_DMACONF 0x06 /* DMA configuration (R/W) */
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#define OPL3SAx_DMACONF_WSSPA 0x01 /* WSS Playback on DMA-A */
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#define OPL3SAx_DMACONF_WSSRA 0x02 /* WSS Recording on DMA-A */
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#define OPL3SAx_DMACONF_SBA 0x02 /* SB Playback on DMA-A */
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#define OPL3SAx_DMACONF_WSSPB 0x10 /* WSS Playback on DMA-A */
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#define OPL3SAx_DMACONF_WSSRB 0x20 /* WSS Recording on DMA-A */
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#define OPL3SAx_DMACONF_SBB 0x20 /* SB Playback on DMA-A */
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#define OPL3SAx_VOLUMEL 0x07 /* Master Volume Left (R/W) */
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#define OPL3SAx_VOLUMEL_MVL 0x0f /* Attenuation level */
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#define OPL3SAx_VOLUMEL_MVLM 0x80 /* Mute */
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#define OPL3SAx_VOLUMER 0x08 /* Master Volume Right (R/W) */
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#define OPL3SAx_VOLUMER_MVR 0x0f /* Attenuation level */
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#define OPL3SAx_VOLUMER_MVRM 0x80 /* Mute */
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#define OPL3SAx_MIC 0x09 /* MIC Volume (R/W) */
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#define OPL3SAx_VOLUMER_MCV 0x1f /* Attenuation level */
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#define OPL3SAx_VOLUMER_MICM 0x80 /* Mute */
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#define OPL3SAx_MISC 0x0a /* Miscellaneous */
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#define OPL3SAx_MISC_VER 0x07 /* Version */
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#define OPL3SAx_MISC_MODE 0x08 /* SB or WSS mode */
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#define OPL3SAx_MISC_MCSW 0x10 /* */
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#define OPL3SAx_MISC_VEN 0x80 /* Enable hardware volume control */
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#define OPL3SAx_WSSDMA 0x0b /* WSS DMA Counter (RW) (4 regs) */
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#define OPL3SAx_WSSIRQSCAN 0x0f /* WSS Interrupt Scan out/in (R/W) */
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#define OPL3SAx_WSSIRQSCAN_SPI 0x01
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#define OPL3SAx_WSSIRQSCAN_SCI 0x02
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#define OPL3SAx_WSSIRQSCAN_STI 0x04
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#define OPL3SAx_SBSTATE 0x10 /* SB compat Internal State (R/W) */
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#define OPL3SAx_SBSTATE_SBPDR 0x01 /* SB Power Down Request */
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#define OPL3SAx_SBSTATE_SE 0x02 /* Scan Enable */
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#define OPL3SAx_SBSTATE_SM 0x04 /* Scan Mode */
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#define OPL3SAx_SBSTATE_SS 0x08 /* Scan Select */
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#define OPL3SAx_SBSTATE_SBPDA 0x80 /* SB Power Down Acknowledge */
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#define OPL3SAx_SBDATA 0x11 /* SB compat State Scan Data (R/W) */
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#define OPL3SAx_DIGITALPOWER 0x12 /* Digital Partial Power Down (R/W) */
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#define OPL3SAx_DIGITALPOWER_PnP 0x01
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#define OPL3SAx_DIGITALPOWER_SB 0x02
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#define OPL3SAx_DIGITALPOWER_WSSP 0x04
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#define OPL3SAx_DIGITALPOWER_WSSR 0x08
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#define OPL3SAx_DIGITALPOWER_FM 0x10
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#define OPL3SAx_DIGITALPOWER_MCLK0 0x20
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#define OPL3SAx_DIGITALPOWER_MPU 0x40
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#define OPL3SAx_DIGITALPOWER_JOY 0x80
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#define OPL3SAx_ANALOGPOWER 0x13 /* Analog Partial Power Down (R/W) */
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#define OPL3SAx_ANALOGPOWER_WIDE 0x01
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#define OPL3SAx_ANALOGPOWER_SBDAC 0x02
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#define OPL3SAx_ANALOGPOWER_DA 0x04
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#define OPL3SAx_ANALOGPOWER_AD 0x08
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#define OPL3SAx_ANALOGPOWER_FMDAC 0x10
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#define OPL3SAx_WIDE 0x14 /* Enhanced control(WIDE) (R/W) */
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#define OPL3SAx_WIDE_WIDEL 0x07 /* Wide level on Left Channel */
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#define OPL3SAx_WIDE_WIDER 0x70 /* Wide level on Right Channel */
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#define OPL3SAx_BASS 0x15 /* Enhanced control(BASS) (R/W) */
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#define OPL3SAx_BASS_BASSL 0x07 /* Bass level on Left Channel */
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#define OPL3SAx_BASS_BASSR 0x70 /* Bass level on Right Channel */
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#define OPL3SAx_TREBLE 0x16 /* Enhanced control(TREBLE) (R/W) */
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#define OPL3SAx_TREBLE_TREBLEL 0x07 /* Treble level on Left Channel */
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#define OPL3SAx_TREBLE_TREBLER 0x70 /* Treble level on Right Channel */
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#define OPL3SAx_HWVOL 0x17 /* HW Volume IRQ Configuration (R/W) */
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#define OPL3SAx_HWVOL_IRQA 0x10 /* HW Volume IRQ on IRQ-A */
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#define OPL3SAx_HWVOL_IRQB 0x20 /* HW Volume IRQ on IRQ-B */
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