2be05b70c9
Previously these were libc functions but were requested to be made into system calls for atomicity and to coalesce what might be two entrances into the kernel (signal mask setting and floating point trap) into one. A few style nits and comments from bde are also included. Tested on alpha by: gallatin
123 lines
4.6 KiB
C
123 lines
4.6 KiB
C
/*-
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* Copyright (c) 1998 Doug Rabson
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _MACHINE_FPU_H_
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#define _MACHINE_FPU_H_
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/*
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* Floating point control register bits.
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*
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* From Alpha AXP Architecture Reference Manual, Instruction
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* Descriptions (I) PP 4-69.
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*/
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#define FPCR_INVD (1LL << 49) /* Invalid Operation DIsable */
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#define FPCR_DZED (1LL << 50) /* Division by Zero Disable */
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#define FPCR_OVFD (1LL << 51) /* Overflow Disable */
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#define FPCR_INV (1LL << 52) /* Invalid Operation */
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#define FPCR_DZE (1LL << 53) /* Division by Zero */
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#define FPCR_OVF (1LL << 54) /* Overflow */
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#define FPCR_UNF (1LL << 55) /* Underflow */
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#define FPCR_INE (1LL << 56) /* Inexact Result */
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#define FPCR_IOV (1LL << 57) /* Integer Overflow */
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#define FPCR_DYN_CHOPPED (0LL << 58) /* Chopped rounding mode */
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#define FPCR_DYN_MINUS (1LL << 58) /* Minus infinity */
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#define FPCR_DYN_NORMAL (2LL << 58) /* Normal rounding */
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#define FPCR_DYN_PLUS (3LL << 58) /* Plus infinity */
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#define FPCR_DYN_MASK (3LL << 58) /* Rounding mode mask */
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#define FPCR_DYN_SHIFT 58
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#define FPCR_UNDZ (1LL << 60) /* Underflow to Zero */
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#define FPCR_UNFD (1LL << 61) /* Underflow Disable */
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#define FPCR_INED (1LL << 62) /* Inexact Disable */
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#define FPCR_SUM (1LL << 63) /* Summary Bit */
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#define FPCR_MASK (~0LL << 49)
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/*
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* Exception summary bits.
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*
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* From Alpha AXP Architecture Reference Manual, DEC OSF/1 Exceptions
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* and Interrupts (II-B) PP 5-5.
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*/
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#define EXCSUM_SWC (1LL << 0) /* Software completion */
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#define EXCSUM_INV (1LL << 1) /* Invalid operation */
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#define EXCSUM_DZE (1LL << 2) /* Division by zero */
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#define EXCSUM_OVF (1LL << 3) /* Overflow */
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#define EXCSUM_UNF (1LL << 4) /* Underflow */
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#define EXCSUM_INE (1LL << 5) /* Inexact result */
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#define EXCSUM_IOV (1LL << 6) /* Integer overflow */
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/*
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* Definitions for IEEE trap enables. These are implemented in
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* software and should be compatible with OSF/1 and Linux.
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*/
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/* read/write flags */
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#define IEEE_TRAP_ENABLE_INV (1LL << 1) /* Invalid operation */
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#define IEEE_TRAP_ENABLE_DZE (1LL << 2) /* Division by zero */
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#define IEEE_TRAP_ENABLE_OVF (1LL << 3) /* Overflow */
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#define IEEE_TRAP_ENABLE_UNF (1LL << 4) /* Underflow */
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#define IEEE_TRAP_ENABLE_INE (1LL << 5) /* Inexact result */
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#define IEEE_TRAP_ENABLE_MASK (IEEE_TRAP_ENABLE_INV \
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| IEEE_TRAP_ENABLE_DZE \
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| IEEE_TRAP_ENABLE_OVF \
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| IEEE_TRAP_ENABLE_UNF \
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| IEEE_TRAP_ENABLE_INE)
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/* read only flags */
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#define IEEE_STATUS_INV (1LL << 17) /* Invalid operation */
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#define IEEE_STATUS_DZE (1LL << 18) /* Division by zero */
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#define IEEE_STATUS_OVF (1LL << 19) /* Overflow */
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#define IEEE_STATUS_UNF (1LL << 20) /* Underflow */
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#define IEEE_STATUS_INE (1LL << 21) /* Inexact result */
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#define IEEE_STATUS_MASK (IEEE_STATUS_INV \
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| IEEE_STATUS_DZE \
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| IEEE_STATUS_OVF \
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| IEEE_STATUS_UNF \
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| IEEE_STATUS_INE)
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#define IEEE_STATUS_TO_EXCSUM_SHIFT 16 /* convert to excsum */
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#define IEEE_STATUS_TO_FPCR_SHIFT 35 /* convert to fpcr */
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#define IEEE_INHERIT (1LL << 63) /* inherit on fork */
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/* read and write floating point control register */
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#define GET_FPCR(x) \
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__asm__("trapb"); \
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__asm__("mf_fpcr %0" : "=f" (x)); \
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__asm__("trapb")
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#define SET_FPCR(x) \
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__asm__("trapb"); \
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__asm__("mt_fpcr %0" : : "f" (x)); \
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__asm__("trapb")
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#ifdef _KERNEL
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extern int fp_software_completion(u_int64_t regmask, struct thread *td);
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#endif
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#endif /* ! _MACHINE_FPU_H_ */
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