653 lines
21 KiB
C
653 lines
21 KiB
C
/*
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* Copyright (c) 2013 Qualcomm Atheros, Inc.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH
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* REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
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* AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT,
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* INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM
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* LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR
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* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
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* PERFORMANCE OF THIS SOFTWARE.
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*/
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#include "opt_ah.h"
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#ifdef AH_SUPPORT_AR9300
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#include "ah.h"
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#include "ah_internal.h"
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#include "ah_devid.h"
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#ifdef AH_DEBUG
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#include "ah_desc.h" /* NB: for HAL_PHYERR* */
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#endif
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#include "ar9300/ar9300.h"
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#include "ar9300/ar9300reg.h"
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#include "ar9300/ar9300phy.h"
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#define AR_GPIO_BIT(_gpio) (1 << (_gpio))
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/*
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* Configure GPIO Output Mux control
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*/
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#ifdef UMAC_SUPPORT_SMARTANTENNA
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static void ar9340_soc_gpio_cfg_output_mux(
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struct ath_hal *ah,
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u_int32_t gpio,
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u_int32_t ah_signal_type)
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{
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#define ADDR_READ(addr) (*((volatile u_int32_t *)(addr)))
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#define ADDR_WRITE(addr, b) (void)((*(volatile u_int32_t *) (addr)) = (b))
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#define AR9340_SOC_GPIO_FUN0 0xB804002c
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#define AR9340_SOC_GPIO_OE 0xB8040000
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#if ATH_SMARTANTENNA_DISABLE_JTAG
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#define AR9340_SOC_GPIO_FUNCTION (volatile u_int32_t*) 0xB804006c
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#define WASP_DISABLE_JTAG 0x2
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#define MAX_JTAG_GPIO_PIN 1
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#endif
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u_int8_t out_func, shift;
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u_int32_t flags;
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volatile u_int32_t* address;
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if (!ah_signal_type){
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return;
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}
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#if ATH_SMARTANTENNA_DISABLE_JTAG
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/*
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* To use GPIO pins 0 and 1 for controling antennas, JTAG needs to disabled.
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*/
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if (gpio <= MAX_JTAG_GPIO_PIN) {
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flags = ADDR_READ(AR9340_SOC_GPIO_FUNCTION);
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flags |= WASP_DISABLE_JTAG;
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ADDR_WRITE(AR9340_SOC_GPIO_FUNCTION, flags);
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}
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#endif
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out_func = gpio / 4;
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shift = (gpio % 4);
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address = (volatile u_int32_t *)(AR9340_SOC_GPIO_FUN0 + (out_func*4));
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flags = ADDR_READ(address);
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flags |= ah_signal_type << (8*shift);
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ADDR_WRITE(address, flags);
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flags = ADDR_READ(AR9340_SOC_GPIO_OE);
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flags &= ~(1 << gpio);
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ADDR_WRITE(AR9340_SOC_GPIO_OE, flags);
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}
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#endif
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static void
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ar9300_gpio_cfg_output_mux(struct ath_hal *ah, u_int32_t gpio, u_int32_t type)
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{
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int addr;
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u_int32_t gpio_shift;
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/* each MUX controls 6 GPIO pins */
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if (gpio > 11) {
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addr = AR_HOSTIF_REG(ah, AR_GPIO_OUTPUT_MUX3);
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} else if (gpio > 5) {
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addr = AR_HOSTIF_REG(ah, AR_GPIO_OUTPUT_MUX2);
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} else {
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addr = AR_HOSTIF_REG(ah, AR_GPIO_OUTPUT_MUX1);
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}
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/*
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* 5 bits per GPIO pin.
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* Bits 0..4 for 1st pin in that mux,
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* bits 5..9 for 2nd pin, etc.
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*/
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gpio_shift = (gpio % 6) * 5;
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OS_REG_RMW(ah, addr, (type << gpio_shift), (0x1f << gpio_shift));
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}
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/*
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* Configure GPIO Output lines
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*/
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HAL_BOOL
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ar9300_gpio_cfg_output(
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struct ath_hal *ah,
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u_int32_t gpio,
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HAL_GPIO_OUTPUT_MUX_TYPE hal_signal_type)
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{
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u_int32_t ah_signal_type;
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u_int32_t gpio_shift;
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u_int8_t smart_ant = 0;
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static const u_int32_t mux_signal_conversion_table[] = {
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/* HAL_GPIO_OUTPUT_MUX_AS_OUTPUT */
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AR_GPIO_OUTPUT_MUX_AS_OUTPUT,
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/* HAL_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED */
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AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED,
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/* HAL_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED */
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AR_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED,
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/* HAL_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED */
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AR_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED,
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/* HAL_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED */
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AR_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED,
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/* HAL_GPIO_OUTPUT_MUX_AS_WLAN_ACTIVE */
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AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL,
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/* HAL_GPIO_OUTPUT_MUX_AS_TX_FRAME */
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AR_GPIO_OUTPUT_MUX_AS_TX_FRAME,
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/* HAL_GPIO_OUTPUT_MUX_AS_MCI_WLAN_DATA */
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AR_GPIO_OUTPUT_MUX_AS_MCI_WLAN_DATA,
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/* HAL_GPIO_OUTPUT_MUX_AS_MCI_WLAN_CLK */
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AR_GPIO_OUTPUT_MUX_AS_MCI_WLAN_CLK,
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/* HAL_GPIO_OUTPUT_MUX_AS_MCI_BT_DATA */
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AR_GPIO_OUTPUT_MUX_AS_MCI_BT_DATA,
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/* HAL_GPIO_OUTPUT_MUX_AS_MCI_BT_CLK */
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AR_GPIO_OUTPUT_MUX_AS_MCI_BT_CLK,
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/* HAL_GPIO_OUTPUT_MUX_AS_WL_IN_TX */
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AR_GPIO_OUTPUT_MUX_AS_WL_IN_TX,
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/* HAL_GPIO_OUTPUT_MUX_AS_WL_IN_RX */
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AR_GPIO_OUTPUT_MUX_AS_WL_IN_RX,
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/* HAL_GPIO_OUTPUT_MUX_AS_BT_IN_TX */
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AR_GPIO_OUTPUT_MUX_AS_BT_IN_TX,
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/* HAL_GPIO_OUTPUT_MUX_AS_BT_IN_RX */
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AR_GPIO_OUTPUT_MUX_AS_BT_IN_RX,
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/* HAL_GPIO_OUTPUT_MUX_AS_RUCKUS_STROBE */
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AR_GPIO_OUTPUT_MUX_AS_RUCKUS_STROBE,
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/* HAL_GPIO_OUTPUT_MUX_AS_RUCKUS_DATA */
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AR_GPIO_OUTPUT_MUX_AS_RUCKUS_DATA,
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/* HAL_GPIO_OUTPUT_MUX_AS_SMARTANT_CTRL0 */
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AR_GPIO_OUTPUT_MUX_AS_SMARTANT_CTRL0,
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/* HAL_GPIO_OUTPUT_MUX_AS_SMARTANT_CTRL1 */
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AR_GPIO_OUTPUT_MUX_AS_SMARTANT_CTRL1,
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/* HAL_GPIO_OUTPUT_MUX_AS_SMARTANT_CTRL2 */
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AR_GPIO_OUTPUT_MUX_AS_SMARTANT_CTRL2,
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/* HAL_GPIO_OUTPUT_MUX_AS_SMARTANT_SWCOM3 */
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AR_GPIO_OUTPUT_MUX_AS_SWCOM3,
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};
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HALASSERT(gpio < AH_PRIVATE(ah)->ah_caps.hal_num_gpio_pins);
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if ((gpio == AR9382_GPIO_PIN_8_RESERVED) ||
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(gpio == AR9382_GPIO_PIN_11_RESERVED) ||
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(gpio == AR9382_GPIO_9_INPUT_ONLY))
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{
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return AH_FALSE;
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}
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/* Convert HAL signal type definitions to hardware-specific values. */
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if (hal_signal_type < ARRAY_LENGTH(mux_signal_conversion_table))
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{
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ah_signal_type = mux_signal_conversion_table[hal_signal_type];
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} else {
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return AH_FALSE;
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}
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if (gpio <= AR9382_MAX_JTAG_GPIO_PIN_NUM) {
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OS_REG_SET_BIT(ah,
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AR_HOSTIF_REG(ah, AR_GPIO_INPUT_EN_VAL), AR_GPIO_JTAG_DISABLE);
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}
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#if UMAC_SUPPORT_SMARTANTENNA
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/* Get the pin and func values for smart antenna */
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switch (ah_signal_type)
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{
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case AR_GPIO_OUTPUT_MUX_AS_SMARTANT_CTRL0:
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gpio = ATH_GPIOPIN_ANTCHAIN0;
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ah_signal_type = ATH_GPIOFUNC_ANTCHAIN0;
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smart_ant = 1;
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break;
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case AR_GPIO_OUTPUT_MUX_AS_SMARTANT_CTRL1:
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gpio = ATH_GPIOPIN_ANTCHAIN1;
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ah_signal_type = ATH_GPIOFUNC_ANTCHAIN1;
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smart_ant = 1;
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break;
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case AR_GPIO_OUTPUT_MUX_AS_SMARTANT_CTRL2:
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gpio = ATH_GPIOPIN_ANTCHAIN2;
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ah_signal_type = ATH_GPIOFUNC_ANTCHAIN2;
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smart_ant = 1;
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break;
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#if ATH_SMARTANTENNA_ROUTE_SWCOM_TO_GPIO
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case AR_GPIO_OUTPUT_MUX_AS_SWCOM3:
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gpio = ATH_GPIOPIN_ROUTE_SWCOM3;
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ah_signal_type = ATH_GPIOFUNC_ROUTE_SWCOM3;
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smart_ant = 1;
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break;
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#endif
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default:
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break;
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}
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#endif
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if (smart_ant && (AR_SREV_WASP(ah) || AR_SREV_SCORPION(ah)))
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{
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#ifdef UMAC_SUPPORT_SMARTANTENNA
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ar9340_soc_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
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#endif
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return AH_TRUE;
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} else
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{
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/* Configure the MUX */
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ar9300_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
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}
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/* 2 bits per output mode */
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gpio_shift = 2 * gpio;
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OS_REG_RMW(ah,
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AR_HOSTIF_REG(ah, AR_GPIO_OE_OUT),
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(AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
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(AR_GPIO_OE_OUT_DRV << gpio_shift));
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return AH_TRUE;
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}
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/*
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* Configure GPIO Output lines -LED off
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*/
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HAL_BOOL
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ar9300_gpio_cfg_output_led_off(
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struct ath_hal *ah,
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u_int32_t gpio,
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HAL_GPIO_OUTPUT_MUX_TYPE halSignalType)
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{
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#define N(a) (sizeof(a) / sizeof(a[0]))
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u_int32_t ah_signal_type;
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u_int32_t gpio_shift;
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u_int8_t smart_ant = 0;
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static const u_int32_t mux_signal_conversion_table[] = {
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/* HAL_GPIO_OUTPUT_MUX_AS_OUTPUT */
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AR_GPIO_OUTPUT_MUX_AS_OUTPUT,
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/* HAL_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED */
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AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED,
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/* HAL_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED */
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AR_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED,
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/* HAL_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED */
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AR_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED,
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/* HAL_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED */
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AR_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED,
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/* HAL_GPIO_OUTPUT_MUX_AS_WLAN_ACTIVE */
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AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL,
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/* HAL_GPIO_OUTPUT_MUX_AS_TX_FRAME */
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AR_GPIO_OUTPUT_MUX_AS_TX_FRAME,
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/* HAL_GPIO_OUTPUT_MUX_AS_MCI_WLAN_DATA */
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AR_GPIO_OUTPUT_MUX_AS_MCI_WLAN_DATA,
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/* HAL_GPIO_OUTPUT_MUX_AS_MCI_WLAN_CLK */
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AR_GPIO_OUTPUT_MUX_AS_MCI_WLAN_CLK,
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/* HAL_GPIO_OUTPUT_MUX_AS_MCI_BT_DATA */
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AR_GPIO_OUTPUT_MUX_AS_MCI_BT_DATA,
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/* HAL_GPIO_OUTPUT_MUX_AS_MCI_BT_CLK */
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AR_GPIO_OUTPUT_MUX_AS_MCI_BT_CLK,
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/* HAL_GPIO_OUTPUT_MUX_AS_WL_IN_TX */
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AR_GPIO_OUTPUT_MUX_AS_WL_IN_TX,
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/* HAL_GPIO_OUTPUT_MUX_AS_WL_IN_RX */
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AR_GPIO_OUTPUT_MUX_AS_WL_IN_RX,
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/* HAL_GPIO_OUTPUT_MUX_AS_BT_IN_TX */
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AR_GPIO_OUTPUT_MUX_AS_BT_IN_TX,
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/* HAL_GPIO_OUTPUT_MUX_AS_BT_IN_RX */
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AR_GPIO_OUTPUT_MUX_AS_BT_IN_RX,
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AR_GPIO_OUTPUT_MUX_AS_RUCKUS_STROBE,
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AR_GPIO_OUTPUT_MUX_AS_RUCKUS_DATA,
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AR_GPIO_OUTPUT_MUX_AS_SMARTANT_CTRL0,
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AR_GPIO_OUTPUT_MUX_AS_SMARTANT_CTRL1,
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AR_GPIO_OUTPUT_MUX_AS_SMARTANT_CTRL2
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};
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HALASSERT(gpio < AH_PRIVATE(ah)->ah_caps.hal_num_gpio_pins);
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/* Convert HAL signal type definitions to hardware-specific values. */
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if (halSignalType < ARRAY_LENGTH(mux_signal_conversion_table))
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{
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ah_signal_type = mux_signal_conversion_table[halSignalType];
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} else {
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return AH_FALSE;
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}
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#if UMAC_SUPPORT_SMARTANTENNA
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/* Get the pin and func values for smart antenna */
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switch (halSignalType)
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{
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case AR_GPIO_OUTPUT_MUX_AS_SMARTANT_CTRL0:
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gpio = ATH_GPIOPIN_ANTCHAIN0;
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ah_signal_type = ATH_GPIOFUNC_ANTCHAIN0;
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smart_ant = 1;
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break;
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case AR_GPIO_OUTPUT_MUX_AS_SMARTANT_CTRL1:
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gpio = ATH_GPIOPIN_ANTCHAIN1;
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ah_signal_type = ATH_GPIOFUNC_ANTCHAIN1;
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smart_ant = 1;
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break;
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case AR_GPIO_OUTPUT_MUX_AS_SMARTANT_CTRL2:
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gpio = ATH_GPIOPIN_ANTCHAIN2;
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ah_signal_type = ATH_GPIOFUNC_ANTCHAIN2;
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smart_ant = 1;
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break;
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default:
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break;
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}
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#endif
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if (smart_ant && AR_SREV_WASP(ah))
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{
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return AH_FALSE;
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}
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// Configure the MUX
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ar9300_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
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// 2 bits per output mode
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gpio_shift = 2*gpio;
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OS_REG_RMW(ah,
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AR_HOSTIF_REG(ah, AR_GPIO_OE_OUT),
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(AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
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(AR_GPIO_OE_OUT_DRV << gpio_shift));
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return AH_TRUE;
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#undef N
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}
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/*
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* Configure GPIO Input lines
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*/
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HAL_BOOL
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ar9300_gpio_cfg_input(struct ath_hal *ah, u_int32_t gpio)
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{
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u_int32_t gpio_shift;
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HALASSERT(gpio < AH_PRIVATE(ah)->ah_caps.hal_num_gpio_pins);
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if ((gpio == AR9382_GPIO_PIN_8_RESERVED) ||
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(gpio == AR9382_GPIO_PIN_11_RESERVED) ||
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(gpio > AR9382_MAX_GPIO_INPUT_PIN_NUM))
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{
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return AH_FALSE;
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}
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if (gpio <= AR9382_MAX_JTAG_GPIO_PIN_NUM) {
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OS_REG_SET_BIT(ah,
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AR_HOSTIF_REG(ah, AR_GPIO_INPUT_EN_VAL), AR_GPIO_JTAG_DISABLE);
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}
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/* TODO: configure input mux for AR9300 */
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/* If configured as input, set output to tristate */
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gpio_shift = 2 * gpio;
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OS_REG_RMW(ah,
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AR_HOSTIF_REG(ah, AR_GPIO_OE_OUT),
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(AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
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(AR_GPIO_OE_OUT_DRV << gpio_shift));
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return AH_TRUE;
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}
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/*
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* Once configured for I/O - set output lines
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* output the level of GPio PIN without care work mode
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*/
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HAL_BOOL
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ar9300_gpio_set(struct ath_hal *ah, u_int32_t gpio, u_int32_t val)
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{
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HALASSERT(gpio < AH_PRIVATE(ah)->ah_caps.hal_num_gpio_pins);
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if ((gpio == AR9382_GPIO_PIN_8_RESERVED) ||
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(gpio == AR9382_GPIO_PIN_11_RESERVED) ||
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(gpio == AR9382_GPIO_9_INPUT_ONLY))
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{
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return AH_FALSE;
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}
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OS_REG_RMW(ah, AR_HOSTIF_REG(ah, AR_GPIO_OUT),
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((val & 1) << gpio), AR_GPIO_BIT(gpio));
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return AH_TRUE;
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}
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/*
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* Once configured for I/O - get input lines
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*/
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u_int32_t
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ar9300_gpio_get(struct ath_hal *ah, u_int32_t gpio)
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{
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u_int32_t gpio_in;
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HALASSERT(gpio < AH_PRIVATE(ah)->ah_caps.hal_num_gpio_pins);
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if ((gpio == AR9382_GPIO_PIN_8_RESERVED) ||
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(gpio == AR9382_GPIO_PIN_11_RESERVED))
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{
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return 0xffffffff;
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}
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gpio_in = OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_GPIO_IN));
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OS_REG_RMW(ah, AR_HOSTIF_REG(ah, AR_GPIO_IN),
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(1 << gpio), AR_GPIO_BIT(gpio));
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return (MS(gpio_in, AR_GPIO_IN_VAL) & AR_GPIO_BIT(gpio)) != 0;
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}
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u_int32_t
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ar9300_gpio_get_intr(struct ath_hal *ah)
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{
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unsigned int mask = 0;
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struct ath_hal_9300 *ahp = AH9300(ah);
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mask = ahp->ah_gpio_cause;
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return mask;
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}
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/*
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* Set the GPIO Interrupt
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* Sync and Async interrupts are both set/cleared.
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* Async GPIO interrupts may not be raised when the chip is put to sleep.
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*/
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void
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ar9300_gpio_set_intr(struct ath_hal *ah, u_int gpio, u_int32_t ilevel)
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{
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int i, reg_bit;
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u_int32_t reg_val;
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u_int32_t regs[2], shifts[2];
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#ifdef AH_ASSERT
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u_int32_t gpio_mask;
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u_int32_t old_field_val = 0, field_val = 0;
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#endif
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#ifdef ATH_GPIO_USE_ASYNC_CAUSE
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regs[0] = AR_HOSTIF_REG(ah, AR_INTR_ASYNC_ENABLE);
|
|
regs[1] = AR_HOSTIF_REG(ah, AR_INTR_ASYNC_MASK);
|
|
shifts[0] = AR_INTR_ASYNC_ENABLE_GPIO_S;
|
|
shifts[1] = AR_INTR_ASYNC_MASK_GPIO_S;
|
|
#else
|
|
regs[0] = AR_HOSTIF_REG(ah, AR_INTR_SYNC_ENABLE);
|
|
regs[1] = AR_HOSTIF_REG(ah, AR_INTR_SYNC_MASK);
|
|
shifts[0] = AR_INTR_SYNC_ENABLE_GPIO_S;
|
|
shifts[1] = AR_INTR_SYNC_MASK_GPIO_S;
|
|
#endif
|
|
|
|
HALASSERT(gpio < AH_PRIVATE(ah)->ah_caps.hal_num_gpio_pins);
|
|
|
|
if ((gpio == AR9382_GPIO_PIN_8_RESERVED) ||
|
|
(gpio == AR9382_GPIO_PIN_11_RESERVED) ||
|
|
(gpio > AR9382_MAX_GPIO_INPUT_PIN_NUM))
|
|
{
|
|
return;
|
|
}
|
|
|
|
#ifdef AH_ASSERT
|
|
gpio_mask = (1 << AH_PRIVATE(ah)->ah_caps.hal_num_gpio_pins) - 1;
|
|
#endif
|
|
|
|
if (ilevel == HAL_GPIO_INTR_DISABLE) {
|
|
/* clear this GPIO's bit in the interrupt registers */
|
|
for (i = 0; i < ARRAY_LENGTH(regs); i++) {
|
|
reg_val = OS_REG_READ(ah, regs[i]);
|
|
reg_bit = shifts[i] + gpio;
|
|
reg_val &= ~(1 << reg_bit);
|
|
OS_REG_WRITE(ah, regs[i], reg_val);
|
|
|
|
/* check that each register has same GPIOs enabled */
|
|
#ifdef AH_ASSERT
|
|
field_val = (reg_val >> shifts[i]) & gpio_mask;
|
|
HALASSERT(i == 0 || old_field_val == field_val);
|
|
old_field_val = field_val;
|
|
#endif
|
|
}
|
|
|
|
} else {
|
|
reg_val = OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_GPIO_INTR_POL));
|
|
reg_bit = gpio;
|
|
if (ilevel == HAL_GPIO_INTR_HIGH) {
|
|
/* 0 == interrupt on pin high */
|
|
reg_val &= ~(1 << reg_bit);
|
|
} else if (ilevel == HAL_GPIO_INTR_LOW) {
|
|
/* 1 == interrupt on pin low */
|
|
reg_val |= (1 << reg_bit);
|
|
}
|
|
OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_GPIO_INTR_POL), reg_val);
|
|
|
|
/* set this GPIO's bit in the interrupt registers */
|
|
for (i = 0; i < ARRAY_LENGTH(regs); i++) {
|
|
reg_val = OS_REG_READ(ah, regs[i]);
|
|
reg_bit = shifts[i] + gpio;
|
|
reg_val |= (1 << reg_bit);
|
|
OS_REG_WRITE(ah, regs[i], reg_val);
|
|
|
|
/* check that each register has same GPIOs enabled */
|
|
#ifdef AH_ASSERT
|
|
field_val = (reg_val >> shifts[i]) & gpio_mask;
|
|
HALASSERT(i == 0 || old_field_val == field_val);
|
|
old_field_val = field_val;
|
|
#endif
|
|
}
|
|
}
|
|
}
|
|
|
|
u_int32_t
|
|
ar9300_gpio_get_polarity(struct ath_hal *ah)
|
|
{
|
|
return OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_GPIO_INTR_POL));
|
|
|
|
}
|
|
|
|
void
|
|
ar9300_gpio_set_polarity(struct ath_hal *ah, u_int32_t pol_map,
|
|
u_int32_t changed_mask)
|
|
{
|
|
u_int32_t gpio_mask;
|
|
|
|
gpio_mask = (1 << AH_PRIVATE(ah)->ah_caps.hal_num_gpio_pins) - 1;
|
|
OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_GPIO_INTR_POL), gpio_mask & pol_map);
|
|
|
|
#ifndef ATH_GPIO_USE_ASYNC_CAUSE
|
|
/*
|
|
* For SYNC_CAUSE type interrupts, we need to clear the cause register
|
|
* explicitly. Otherwise an interrupt with the original polarity setting
|
|
* will come up immediately (if there is already an interrupt source),
|
|
* which is not what we want usually.
|
|
*/
|
|
OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_INTR_SYNC_CAUSE_CLR),
|
|
changed_mask << AR_INTR_SYNC_ENABLE_GPIO_S);
|
|
OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_INTR_SYNC_CAUSE_CLR));
|
|
#endif
|
|
}
|
|
|
|
/*
|
|
* get the GPIO input pin mask
|
|
* gpio0 - gpio13
|
|
* gpio8, gpio11, regard as reserved by the chip ar9382
|
|
*/
|
|
|
|
u_int32_t
|
|
ar9300_gpio_get_mask(struct ath_hal *ah)
|
|
{
|
|
u_int32_t mask = (1 << (AR9382_MAX_GPIO_INPUT_PIN_NUM + 1) ) - 1;
|
|
|
|
if (AH_PRIVATE(ah)->ah_devid == AR9300_DEVID_AR9380_PCIE) {
|
|
mask = (1 << AR9382_MAX_GPIO_PIN_NUM) - 1;
|
|
mask &= ~(1 << AR9382_GPIO_PIN_8_RESERVED |
|
|
1 << AR9382_GPIO_PIN_11_RESERVED);
|
|
}
|
|
return mask;
|
|
}
|
|
|
|
int
|
|
ar9300_gpio_set_mask(struct ath_hal *ah, u_int32_t mask, u_int32_t pol_map)
|
|
{
|
|
u_int32_t invalid = ~((1 << (AR9382_MAX_GPIO_INPUT_PIN_NUM + 1)) - 1);
|
|
|
|
if (AH_PRIVATE(ah)->ah_devid == AR9300_DEVID_AR9380_PCIE) {
|
|
invalid = ~((1 << AR9382_MAX_GPIO_PIN_NUM) - 1);
|
|
invalid |= 1 << AR9382_GPIO_PIN_8_RESERVED |
|
|
1 << AR9382_GPIO_PIN_11_RESERVED;
|
|
}
|
|
if (mask & invalid) {
|
|
ath_hal_printf(ah, "%s: invalid GPIO mask 0x%x\n", __func__, mask);
|
|
return -1;
|
|
}
|
|
AH9300(ah)->ah_gpio_mask = mask;
|
|
OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_GPIO_INTR_POL), mask & pol_map);
|
|
|
|
return 0;
|
|
}
|
|
|
|
#ifdef AH_DEBUG
|
|
void ar9300_gpio_show(struct ath_hal *ah);
|
|
void ar9300_gpio_show(struct ath_hal *ah)
|
|
{
|
|
ath_hal_printf(ah, "--- 9382 GPIOs ---(ah=%p)\n", ah );
|
|
ath_hal_printf(ah,
|
|
"AH9300(_ah)->ah_hostifregs:%p\r\n", &(AH9300(ah)->ah_hostifregs));
|
|
ath_hal_printf(ah,
|
|
"GPIO_OUT: 0x%08X\n",
|
|
OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_GPIO_OUT)));
|
|
ath_hal_printf(ah,
|
|
"GPIO_IN: 0x%08X\n",
|
|
OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_GPIO_IN)));
|
|
ath_hal_printf(ah,
|
|
"GPIO_OE: 0x%08X\n",
|
|
OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_GPIO_OE_OUT)));
|
|
ath_hal_printf(ah,
|
|
"GPIO_OE1_OUT: 0x%08X\n",
|
|
OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_GPIO_OE1_OUT)));
|
|
ath_hal_printf(ah,
|
|
"GPIO_INTR_POLAR: 0x%08X\n",
|
|
OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_GPIO_INTR_POL)));
|
|
ath_hal_printf(ah,
|
|
"GPIO_INPUT_VALUE: 0x%08X\n",
|
|
OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_GPIO_INPUT_EN_VAL)));
|
|
ath_hal_printf(ah,
|
|
"GPIO_INPUT_MUX1: 0x%08X\n",
|
|
OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_GPIO_INPUT_MUX1)));
|
|
ath_hal_printf(ah,
|
|
"GPIO_INPUT_MUX2: 0x%08X\n",
|
|
OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_GPIO_INPUT_MUX2)));
|
|
ath_hal_printf(ah,
|
|
"GPIO_OUTPUT_MUX1: 0x%08X\n",
|
|
OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_GPIO_OUTPUT_MUX1)));
|
|
ath_hal_printf(ah,
|
|
"GPIO_OUTPUT_MUX2: 0x%08X\n",
|
|
OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_GPIO_OUTPUT_MUX2)));
|
|
ath_hal_printf(ah,
|
|
"GPIO_OUTPUT_MUX3: 0x%08X\n",
|
|
OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_GPIO_OUTPUT_MUX3)));
|
|
ath_hal_printf(ah,
|
|
"GPIO_INPUT_STATE: 0x%08X\n",
|
|
OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_INPUT_STATE)));
|
|
ath_hal_printf(ah,
|
|
"GPIO_PDPU: 0x%08X\n",
|
|
OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_GPIO_PDPU)));
|
|
ath_hal_printf(ah,
|
|
"GPIO_DS: 0x%08X\n",
|
|
OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_GPIO_DS)));
|
|
ath_hal_printf(ah,
|
|
"AR_INTR_ASYNC_ENABLE: 0x%08X\n",
|
|
OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_INTR_ASYNC_ENABLE)));
|
|
ath_hal_printf(ah,
|
|
"AR_INTR_ASYNC_MASK: 0x%08X\n",
|
|
OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_INTR_ASYNC_MASK)));
|
|
ath_hal_printf(ah,
|
|
"AR_INTR_SYNC_ENABLE: 0x%08X\n",
|
|
OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_INTR_SYNC_ENABLE)));
|
|
ath_hal_printf(ah,
|
|
"AR_INTR_SYNC_MASK: 0x%08X\n",
|
|
OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_INTR_SYNC_MASK)));
|
|
ath_hal_printf(ah,
|
|
"AR_INTR_ASYNC_CAUSE: 0x%08X\n",
|
|
OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_INTR_ASYNC_CAUSE)));
|
|
ath_hal_printf(ah,
|
|
"AR_INTR_SYNC_CAUSE: 0x%08X\n",
|
|
OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_INTR_SYNC_CAUSE)));
|
|
|
|
}
|
|
#endif /*AH_DEBUG*/
|
|
|
|
#endif /* AH_SUPPORT_AR9300 */
|