e92d228bbb
PowerISA 2.07 and PowerISA 3.0 both specify special NOPs for priority adjustments, with "medium" priority being normal. We had been setting medium-low as our normal priority. Rather than guess each time as to what we want and the right NOP, wrap them in inline functions, and replace the occurrances of the NOPs with the functions. Also, make DELAY() drop to very low priority while waiting, so we don't burn CPU. Coupled with r346143, this shaves off a modest 5-8% on buildworld times with -j72. There may be more room for improvement with judicious use of these NOPs. MFC after: 2 weeks
255 lines
4.4 KiB
C
255 lines
4.4 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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* Copyright (c) 1998 Doug Rabson
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _MACHINE_CPUFUNC_H_
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#define _MACHINE_CPUFUNC_H_
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#ifdef _KERNEL
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#include <sys/types.h>
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#include <machine/psl.h>
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#include <machine/spr.h>
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struct thread;
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#ifdef KDB
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void breakpoint(void);
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#else
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static __inline void
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breakpoint(void)
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{
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return;
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}
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#endif
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/* CPU register mangling inlines */
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static __inline void
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mtmsr(register_t value)
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{
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__asm __volatile ("mtmsr %0; isync" :: "r"(value));
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}
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#ifdef __powerpc64__
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static __inline void
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mtmsrd(register_t value)
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{
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__asm __volatile ("mtmsrd %0; isync" :: "r"(value));
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}
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#endif
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static __inline register_t
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mfmsr(void)
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{
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register_t value;
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__asm __volatile ("mfmsr %0" : "=r"(value));
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return (value);
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}
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#ifndef __powerpc64__
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static __inline void
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mtsrin(vm_offset_t va, register_t value)
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{
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__asm __volatile ("mtsrin %0,%1; isync" :: "r"(value), "r"(va));
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}
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static __inline register_t
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mfsrin(vm_offset_t va)
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{
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register_t value;
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__asm __volatile ("mfsrin %0,%1" : "=r"(value) : "r"(va));
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return (value);
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}
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#endif
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static __inline register_t
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mfctrl(void)
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{
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register_t value;
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__asm __volatile ("mfspr %0,136" : "=r"(value));
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return (value);
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}
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static __inline void
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mtdec(register_t value)
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{
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__asm __volatile ("mtdec %0" :: "r"(value));
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}
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static __inline register_t
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mfdec(void)
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{
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register_t value;
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__asm __volatile ("mfdec %0" : "=r"(value));
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return (value);
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}
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static __inline register_t
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mfpvr(void)
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{
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register_t value;
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__asm __volatile ("mfpvr %0" : "=r"(value));
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return (value);
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}
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static __inline u_quad_t
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mftb(void)
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{
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u_quad_t tb;
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#ifdef __powerpc64__
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__asm __volatile ("mftb %0" : "=r"(tb));
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#else
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uint32_t *tbup = (uint32_t *)&tb;
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uint32_t *tblp = tbup + 1;
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do {
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*tbup = mfspr(TBR_TBU);
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*tblp = mfspr(TBR_TBL);
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} while (*tbup != mfspr(TBR_TBU));
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#endif
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return (tb);
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}
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static __inline void
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mttb(u_quad_t time)
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{
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mtspr(TBR_TBWL, 0);
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mtspr(TBR_TBWU, (uint32_t)(time >> 32));
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mtspr(TBR_TBWL, (uint32_t)(time & 0xffffffff));
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}
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static __inline void
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eieio(void)
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{
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__asm __volatile ("eieio" : : : "memory");
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}
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static __inline void
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isync(void)
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{
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__asm __volatile ("isync" : : : "memory");
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}
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static __inline void
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powerpc_sync(void)
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{
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__asm __volatile ("sync" : : : "memory");
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}
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static __inline register_t
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intr_disable(void)
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{
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register_t msr;
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msr = mfmsr();
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mtmsr(msr & ~PSL_EE);
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return (msr);
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}
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static __inline void
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intr_restore(register_t msr)
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{
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mtmsr(msr);
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}
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static __inline struct pcpu *
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get_pcpu(void)
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{
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struct pcpu *ret;
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__asm __volatile("mfsprg %0, 0" : "=r"(ret));
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return (ret);
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}
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/* "NOP" operations to signify priorities to the kernel. */
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static __inline void
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nop_prio_vlow(void)
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{
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__asm __volatile("or 31,31,31");
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}
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static __inline void
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nop_prio_low(void)
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{
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__asm __volatile("or 1,1,1");
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}
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static __inline void
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nop_prio_mlow(void)
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{
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__asm __volatile("or 6,6,6");
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}
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static __inline void
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nop_prio_medium(void)
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{
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__asm __volatile("or 2,2,2");
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}
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static __inline void
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nop_prio_mhigh(void)
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{
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__asm __volatile("or 5,5,5");
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}
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static __inline void
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nop_prio_high(void)
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{
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__asm __volatile("or 3,3,3");
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}
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#endif /* _KERNEL */
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#endif /* !_MACHINE_CPUFUNC_H_ */
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