5ed9deef6b
This is a verbatim copy of the public headers from Xen 4.14.1. No functional change intended. Sponsored by: Citrix Systems R&D
296 lines
16 KiB
C
296 lines
16 KiB
C
/*
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* arch-x86/cpufeatureset.h
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*
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* CPU featureset definitions
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to
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* deal in the Software without restriction, including without limitation the
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* rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*
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* Copyright (c) 2015, 2016 Citrix Systems, Inc.
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*/
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/*
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* There are two expected ways of including this header.
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*
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* 1) The "default" case (expected from tools etc).
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*
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* Simply #include <public/arch-x86/cpufeatureset.h>
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*
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* In this circumstance, normal header guards apply and the includer shall get
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* an enumeration in the XEN_X86_FEATURE_xxx namespace.
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*
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* 2) The special case where the includer provides XEN_CPUFEATURE() in scope.
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*
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* In this case, no inclusion guards apply and the caller is responsible for
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* their XEN_CPUFEATURE() being appropriate in the included context.
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*/
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#ifndef XEN_CPUFEATURE
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/*
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* Includer has not provided a custom XEN_CPUFEATURE(). Arrange for normal
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* header guards, an enum and constants in the XEN_X86_FEATURE_xxx namespace.
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*/
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#ifndef __XEN_PUBLIC_ARCH_X86_CPUFEATURESET_H__
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#define __XEN_PUBLIC_ARCH_X86_CPUFEATURESET_H__
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#define XEN_CPUFEATURESET_DEFAULT_INCLUDE
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#define XEN_CPUFEATURE(name, value) XEN_X86_FEATURE_##name = value,
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enum {
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#endif /* __XEN_PUBLIC_ARCH_X86_CPUFEATURESET_H__ */
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#endif /* !XEN_CPUFEATURE */
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#ifdef XEN_CPUFEATURE
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/*
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* A featureset is a bitmap of x86 features, represented as a collection of
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* 32bit words.
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*
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* Words are as specified in vendors programming manuals, and shall not
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* contain any synthesied values. New words may be added to the end of
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* featureset.
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*
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* All featureset words currently originate from leaves specified for the
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* CPUID instruction, but this is not preclude other sources of information.
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*/
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/*
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* Attribute syntax:
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*
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* Attributes for a particular feature are provided as characters before the
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* first space in the comment immediately following the feature value. Note -
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* none of these attributes form part of the Xen public ABI.
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*
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* Special: '!'
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* This bit has special properties and is not a straight indication of a
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* piece of new functionality. Xen will handle these differently,
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* and may override toolstack settings completely.
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*
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* Applicability to guests: 'A', 'S' or 'H'
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* 'A' = All guests.
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* 'S' = All HVM guests (not PV guests).
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* 'H' = HVM HAP guests (not PV or HVM Shadow guests).
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* Upper case => Available by default
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* Lower case => Can be opted-in to, but not available by default.
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*/
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/* Intel-defined CPU features, CPUID level 0x00000001.edx, word 0 */
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XEN_CPUFEATURE(FPU, 0*32+ 0) /*A Onboard FPU */
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XEN_CPUFEATURE(VME, 0*32+ 1) /*S Virtual Mode Extensions */
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XEN_CPUFEATURE(DE, 0*32+ 2) /*A Debugging Extensions */
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XEN_CPUFEATURE(PSE, 0*32+ 3) /*S Page Size Extensions */
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XEN_CPUFEATURE(TSC, 0*32+ 4) /*A Time Stamp Counter */
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XEN_CPUFEATURE(MSR, 0*32+ 5) /*A Model-Specific Registers, RDMSR, WRMSR */
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XEN_CPUFEATURE(PAE, 0*32+ 6) /*A Physical Address Extensions */
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XEN_CPUFEATURE(MCE, 0*32+ 7) /*A Machine Check Architecture */
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XEN_CPUFEATURE(CX8, 0*32+ 8) /*A CMPXCHG8 instruction */
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XEN_CPUFEATURE(APIC, 0*32+ 9) /*!A Onboard APIC */
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XEN_CPUFEATURE(SEP, 0*32+11) /*A SYSENTER/SYSEXIT */
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XEN_CPUFEATURE(MTRR, 0*32+12) /*S Memory Type Range Registers */
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XEN_CPUFEATURE(PGE, 0*32+13) /*S Page Global Enable */
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XEN_CPUFEATURE(MCA, 0*32+14) /*A Machine Check Architecture */
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XEN_CPUFEATURE(CMOV, 0*32+15) /*A CMOV instruction (FCMOVCC and FCOMI too if FPU present) */
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XEN_CPUFEATURE(PAT, 0*32+16) /*A Page Attribute Table */
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XEN_CPUFEATURE(PSE36, 0*32+17) /*S 36-bit PSEs */
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XEN_CPUFEATURE(CLFLUSH, 0*32+19) /*A CLFLUSH instruction */
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XEN_CPUFEATURE(DS, 0*32+21) /* Debug Store */
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XEN_CPUFEATURE(ACPI, 0*32+22) /*A ACPI via MSR */
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XEN_CPUFEATURE(MMX, 0*32+23) /*A Multimedia Extensions */
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XEN_CPUFEATURE(FXSR, 0*32+24) /*A FXSAVE and FXRSTOR instructions */
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XEN_CPUFEATURE(SSE, 0*32+25) /*A Streaming SIMD Extensions */
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XEN_CPUFEATURE(SSE2, 0*32+26) /*A Streaming SIMD Extensions-2 */
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XEN_CPUFEATURE(SS, 0*32+27) /*A CPU self snoop */
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XEN_CPUFEATURE(HTT, 0*32+28) /*!A Hyper-Threading Technology */
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XEN_CPUFEATURE(TM1, 0*32+29) /* Thermal Monitor 1 */
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XEN_CPUFEATURE(PBE, 0*32+31) /* Pending Break Enable */
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/* Intel-defined CPU features, CPUID level 0x00000001.ecx, word 1 */
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XEN_CPUFEATURE(SSE3, 1*32+ 0) /*A Streaming SIMD Extensions-3 */
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XEN_CPUFEATURE(PCLMULQDQ, 1*32+ 1) /*A Carry-less multiplication */
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XEN_CPUFEATURE(DTES64, 1*32+ 2) /* 64-bit Debug Store */
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XEN_CPUFEATURE(MONITOR, 1*32+ 3) /* Monitor/Mwait support */
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XEN_CPUFEATURE(DSCPL, 1*32+ 4) /* CPL Qualified Debug Store */
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XEN_CPUFEATURE(VMX, 1*32+ 5) /*S Virtual Machine Extensions */
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XEN_CPUFEATURE(SMX, 1*32+ 6) /* Safer Mode Extensions */
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XEN_CPUFEATURE(EIST, 1*32+ 7) /* Enhanced SpeedStep */
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XEN_CPUFEATURE(TM2, 1*32+ 8) /* Thermal Monitor 2 */
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XEN_CPUFEATURE(SSSE3, 1*32+ 9) /*A Supplemental Streaming SIMD Extensions-3 */
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XEN_CPUFEATURE(FMA, 1*32+12) /*A Fused Multiply Add */
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XEN_CPUFEATURE(CX16, 1*32+13) /*A CMPXCHG16B */
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XEN_CPUFEATURE(XTPR, 1*32+14) /* Send Task Priority Messages */
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XEN_CPUFEATURE(PDCM, 1*32+15) /* Perf/Debug Capability MSR */
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XEN_CPUFEATURE(PCID, 1*32+17) /*H Process Context ID */
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XEN_CPUFEATURE(DCA, 1*32+18) /* Direct Cache Access */
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XEN_CPUFEATURE(SSE4_1, 1*32+19) /*A Streaming SIMD Extensions 4.1 */
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XEN_CPUFEATURE(SSE4_2, 1*32+20) /*A Streaming SIMD Extensions 4.2 */
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XEN_CPUFEATURE(X2APIC, 1*32+21) /*!A Extended xAPIC */
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XEN_CPUFEATURE(MOVBE, 1*32+22) /*A movbe instruction */
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XEN_CPUFEATURE(POPCNT, 1*32+23) /*A POPCNT instruction */
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XEN_CPUFEATURE(TSC_DEADLINE, 1*32+24) /*S TSC Deadline Timer */
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XEN_CPUFEATURE(AESNI, 1*32+25) /*A AES instructions */
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XEN_CPUFEATURE(XSAVE, 1*32+26) /*A XSAVE/XRSTOR/XSETBV/XGETBV */
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XEN_CPUFEATURE(OSXSAVE, 1*32+27) /*! OSXSAVE */
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XEN_CPUFEATURE(AVX, 1*32+28) /*A Advanced Vector Extensions */
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XEN_CPUFEATURE(F16C, 1*32+29) /*A Half-precision convert instruction */
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XEN_CPUFEATURE(RDRAND, 1*32+30) /*!A Digital Random Number Generator */
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XEN_CPUFEATURE(HYPERVISOR, 1*32+31) /*!A Running under some hypervisor */
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/* AMD-defined CPU features, CPUID level 0x80000001.edx, word 2 */
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XEN_CPUFEATURE(SYSCALL, 2*32+11) /*A SYSCALL/SYSRET */
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XEN_CPUFEATURE(NX, 2*32+20) /*A Execute Disable */
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XEN_CPUFEATURE(MMXEXT, 2*32+22) /*A AMD MMX extensions */
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XEN_CPUFEATURE(FFXSR, 2*32+25) /*A FFXSR instruction optimizations */
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XEN_CPUFEATURE(PAGE1GB, 2*32+26) /*H 1Gb large page support */
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XEN_CPUFEATURE(RDTSCP, 2*32+27) /*A RDTSCP */
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XEN_CPUFEATURE(LM, 2*32+29) /*A Long Mode (x86-64) */
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XEN_CPUFEATURE(3DNOWEXT, 2*32+30) /*A AMD 3DNow! extensions */
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XEN_CPUFEATURE(3DNOW, 2*32+31) /*A 3DNow! */
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/* AMD-defined CPU features, CPUID level 0x80000001.ecx, word 3 */
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XEN_CPUFEATURE(LAHF_LM, 3*32+ 0) /*A LAHF/SAHF in long mode */
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XEN_CPUFEATURE(CMP_LEGACY, 3*32+ 1) /*!A If yes HyperThreading not valid */
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XEN_CPUFEATURE(SVM, 3*32+ 2) /*S Secure virtual machine */
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XEN_CPUFEATURE(EXTAPIC, 3*32+ 3) /* Extended APIC space */
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XEN_CPUFEATURE(CR8_LEGACY, 3*32+ 4) /*S CR8 in 32-bit mode */
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XEN_CPUFEATURE(ABM, 3*32+ 5) /*A Advanced bit manipulation */
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XEN_CPUFEATURE(SSE4A, 3*32+ 6) /*A SSE-4A */
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XEN_CPUFEATURE(MISALIGNSSE, 3*32+ 7) /*A Misaligned SSE mode */
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XEN_CPUFEATURE(3DNOWPREFETCH, 3*32+ 8) /*A 3DNow prefetch instructions */
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XEN_CPUFEATURE(OSVW, 3*32+ 9) /* OS Visible Workaround */
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XEN_CPUFEATURE(IBS, 3*32+10) /* Instruction Based Sampling */
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XEN_CPUFEATURE(XOP, 3*32+11) /*A extended AVX instructions */
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XEN_CPUFEATURE(SKINIT, 3*32+12) /* SKINIT/STGI instructions */
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XEN_CPUFEATURE(WDT, 3*32+13) /* Watchdog timer */
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XEN_CPUFEATURE(LWP, 3*32+15) /* Light Weight Profiling */
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XEN_CPUFEATURE(FMA4, 3*32+16) /*A 4 operands MAC instructions */
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XEN_CPUFEATURE(NODEID_MSR, 3*32+19) /* NodeId MSR */
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XEN_CPUFEATURE(TBM, 3*32+21) /*A trailing bit manipulations */
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XEN_CPUFEATURE(TOPOEXT, 3*32+22) /* topology extensions CPUID leafs */
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XEN_CPUFEATURE(DBEXT, 3*32+26) /*A data breakpoint extension */
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XEN_CPUFEATURE(MONITORX, 3*32+29) /* MONITOR extension (MONITORX/MWAITX) */
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/* Intel-defined CPU features, CPUID level 0x0000000D:1.eax, word 4 */
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XEN_CPUFEATURE(XSAVEOPT, 4*32+ 0) /*A XSAVEOPT instruction */
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XEN_CPUFEATURE(XSAVEC, 4*32+ 1) /*A XSAVEC/XRSTORC instructions */
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XEN_CPUFEATURE(XGETBV1, 4*32+ 2) /*A XGETBV with %ecx=1 */
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XEN_CPUFEATURE(XSAVES, 4*32+ 3) /*S XSAVES/XRSTORS instructions */
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/* Intel-defined CPU features, CPUID level 0x00000007:0.ebx, word 5 */
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XEN_CPUFEATURE(FSGSBASE, 5*32+ 0) /*A {RD,WR}{FS,GS}BASE instructions */
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XEN_CPUFEATURE(TSC_ADJUST, 5*32+ 1) /*S TSC_ADJUST MSR available */
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XEN_CPUFEATURE(SGX, 5*32+ 2) /* Software Guard extensions */
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XEN_CPUFEATURE(BMI1, 5*32+ 3) /*A 1st bit manipulation extensions */
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XEN_CPUFEATURE(HLE, 5*32+ 4) /*A Hardware Lock Elision */
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XEN_CPUFEATURE(AVX2, 5*32+ 5) /*A AVX2 instructions */
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XEN_CPUFEATURE(FDP_EXCP_ONLY, 5*32+ 6) /*! x87 FDP only updated on exception. */
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XEN_CPUFEATURE(SMEP, 5*32+ 7) /*S Supervisor Mode Execution Protection */
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XEN_CPUFEATURE(BMI2, 5*32+ 8) /*A 2nd bit manipulation extensions */
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XEN_CPUFEATURE(ERMS, 5*32+ 9) /*A Enhanced REP MOVSB/STOSB */
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XEN_CPUFEATURE(INVPCID, 5*32+10) /*H Invalidate Process Context ID */
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XEN_CPUFEATURE(RTM, 5*32+11) /*A Restricted Transactional Memory */
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XEN_CPUFEATURE(PQM, 5*32+12) /* Platform QoS Monitoring */
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XEN_CPUFEATURE(NO_FPU_SEL, 5*32+13) /*! FPU CS/DS stored as zero */
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XEN_CPUFEATURE(MPX, 5*32+14) /*s Memory Protection Extensions */
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XEN_CPUFEATURE(PQE, 5*32+15) /* Platform QoS Enforcement */
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XEN_CPUFEATURE(AVX512F, 5*32+16) /*A AVX-512 Foundation Instructions */
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XEN_CPUFEATURE(AVX512DQ, 5*32+17) /*A AVX-512 Doubleword & Quadword Instrs */
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XEN_CPUFEATURE(RDSEED, 5*32+18) /*A RDSEED instruction */
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XEN_CPUFEATURE(ADX, 5*32+19) /*A ADCX, ADOX instructions */
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XEN_CPUFEATURE(SMAP, 5*32+20) /*S Supervisor Mode Access Prevention */
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XEN_CPUFEATURE(AVX512_IFMA, 5*32+21) /*A AVX-512 Integer Fused Multiply Add */
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XEN_CPUFEATURE(CLFLUSHOPT, 5*32+23) /*A CLFLUSHOPT instruction */
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XEN_CPUFEATURE(CLWB, 5*32+24) /*A CLWB instruction */
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XEN_CPUFEATURE(AVX512PF, 5*32+26) /*A AVX-512 Prefetch Instructions */
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XEN_CPUFEATURE(AVX512ER, 5*32+27) /*A AVX-512 Exponent & Reciprocal Instrs */
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XEN_CPUFEATURE(AVX512CD, 5*32+28) /*A AVX-512 Conflict Detection Instrs */
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XEN_CPUFEATURE(SHA, 5*32+29) /*A SHA1 & SHA256 instructions */
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XEN_CPUFEATURE(AVX512BW, 5*32+30) /*A AVX-512 Byte and Word Instructions */
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XEN_CPUFEATURE(AVX512VL, 5*32+31) /*A AVX-512 Vector Length Extensions */
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/* Intel-defined CPU features, CPUID level 0x00000007:0.ecx, word 6 */
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XEN_CPUFEATURE(PREFETCHWT1, 6*32+ 0) /*A PREFETCHWT1 instruction */
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XEN_CPUFEATURE(AVX512_VBMI, 6*32+ 1) /*A AVX-512 Vector Byte Manipulation Instrs */
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XEN_CPUFEATURE(UMIP, 6*32+ 2) /*S User Mode Instruction Prevention */
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XEN_CPUFEATURE(PKU, 6*32+ 3) /*H Protection Keys for Userspace */
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XEN_CPUFEATURE(OSPKE, 6*32+ 4) /*! OS Protection Keys Enable */
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XEN_CPUFEATURE(AVX512_VBMI2, 6*32+ 6) /*A Additional AVX-512 Vector Byte Manipulation Instrs */
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XEN_CPUFEATURE(CET_SS, 6*32+ 7) /* CET - Shadow Stacks */
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XEN_CPUFEATURE(GFNI, 6*32+ 8) /*A Galois Field Instrs */
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XEN_CPUFEATURE(VAES, 6*32+ 9) /*A Vector AES Instrs */
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XEN_CPUFEATURE(VPCLMULQDQ, 6*32+10) /*A Vector Carry-less Multiplication Instrs */
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XEN_CPUFEATURE(AVX512_VNNI, 6*32+11) /*A Vector Neural Network Instrs */
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XEN_CPUFEATURE(AVX512_BITALG, 6*32+12) /*A Support for VPOPCNT[B,W] and VPSHUFBITQMB */
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XEN_CPUFEATURE(AVX512_VPOPCNTDQ, 6*32+14) /*A POPCNT for vectors of DW/QW */
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XEN_CPUFEATURE(TSXLDTRK, 6*32+16) /*a TSX load tracking suspend/resume insns */
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XEN_CPUFEATURE(RDPID, 6*32+22) /*A RDPID instruction */
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XEN_CPUFEATURE(CLDEMOTE, 6*32+25) /*A CLDEMOTE instruction */
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XEN_CPUFEATURE(MOVDIRI, 6*32+27) /*a MOVDIRI instruction */
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XEN_CPUFEATURE(MOVDIR64B, 6*32+28) /*a MOVDIR64B instruction */
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XEN_CPUFEATURE(ENQCMD, 6*32+29) /* ENQCMD{,S} instructions */
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/* AMD-defined CPU features, CPUID level 0x80000007.edx, word 7 */
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XEN_CPUFEATURE(ITSC, 7*32+ 8) /* Invariant TSC */
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XEN_CPUFEATURE(EFRO, 7*32+10) /* APERF/MPERF Read Only interface */
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/* AMD-defined CPU features, CPUID level 0x80000008.ebx, word 8 */
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XEN_CPUFEATURE(CLZERO, 8*32+ 0) /*A CLZERO instruction */
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XEN_CPUFEATURE(RSTR_FP_ERR_PTRS, 8*32+ 2) /*A (F)X{SAVE,RSTOR} always saves/restores FPU Error pointers */
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XEN_CPUFEATURE(WBNOINVD, 8*32+ 9) /* WBNOINVD instruction */
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XEN_CPUFEATURE(IBPB, 8*32+12) /*A IBPB support only (no IBRS, used by AMD) */
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XEN_CPUFEATURE(AMD_PPIN, 8*32+23) /* Protected Processor Inventory Number */
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/* Intel-defined CPU features, CPUID level 0x00000007:0.edx, word 9 */
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XEN_CPUFEATURE(AVX512_4VNNIW, 9*32+ 2) /*A AVX512 Neural Network Instructions */
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XEN_CPUFEATURE(AVX512_4FMAPS, 9*32+ 3) /*A AVX512 Multiply Accumulation Single Precision */
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XEN_CPUFEATURE(SRBDS_CTRL, 9*32+ 9) /* MSR_MCU_OPT_CTRL and RNGDS_MITG_DIS. */
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XEN_CPUFEATURE(MD_CLEAR, 9*32+10) /*A VERW clears microarchitectural buffers */
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XEN_CPUFEATURE(TSX_FORCE_ABORT, 9*32+13) /* MSR_TSX_FORCE_ABORT.RTM_ABORT */
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XEN_CPUFEATURE(SERIALIZE, 9*32+14) /*a SERIALIZE insn */
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XEN_CPUFEATURE(CET_IBT, 9*32+20) /* CET - Indirect Branch Tracking */
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XEN_CPUFEATURE(IBRSB, 9*32+26) /*A IBRS and IBPB support (used by Intel) */
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XEN_CPUFEATURE(STIBP, 9*32+27) /*A STIBP */
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XEN_CPUFEATURE(L1D_FLUSH, 9*32+28) /*S MSR_FLUSH_CMD and L1D flush. */
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XEN_CPUFEATURE(ARCH_CAPS, 9*32+29) /*a IA32_ARCH_CAPABILITIES MSR */
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XEN_CPUFEATURE(CORE_CAPS, 9*32+30) /* IA32_CORE_CAPABILITIES MSR */
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XEN_CPUFEATURE(SSBD, 9*32+31) /*A MSR_SPEC_CTRL.SSBD available */
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/* Intel-defined CPU features, CPUID level 0x00000007:1.eax, word 10 */
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XEN_CPUFEATURE(AVX512_BF16, 10*32+ 5) /*A AVX512 BFloat16 Instructions */
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#endif /* XEN_CPUFEATURE */
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/* Clean up from a default include. Close the enum (for C). */
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#ifdef XEN_CPUFEATURESET_DEFAULT_INCLUDE
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#undef XEN_CPUFEATURESET_DEFAULT_INCLUDE
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#undef XEN_CPUFEATURE
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};
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#endif /* XEN_CPUFEATURESET_DEFAULT_INCLUDE */
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/*
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* Local variables:
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* mode: C
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* c-file-style: "BSD"
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* c-basic-offset: 4
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* tab-width: 4
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* indent-tabs-mode: nil
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* End:
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*/
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