af2b2a7331
o replace driver-global lock with three locks: one for the handling of mcr1 operations, one for handling of mcr2 operations, and one for the mcr1 free list o mark the interrupt handler MPSAFE o don't use locking on detach; disabling interrupts is sufficient (I think)
260 lines
8.3 KiB
C
260 lines
8.3 KiB
C
/* $FreeBSD$ */
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/* $OpenBSD: ubsecvar.h,v 1.35 2002/09/24 18:33:26 jason Exp $ */
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/*
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* Copyright (c) 2000 Theo de Raadt
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* Copyright (c) 2001 Patrik Lindergren (patrik@ipunplugged.com)
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Effort sponsored in part by the Defense Advanced Research Projects
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* Agency (DARPA) and Air Force Research Laboratory, Air Force
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* Materiel Command, USAF, under agreement number F30602-01-2-0537.
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*
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*/
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/* Maximum queue length */
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#ifndef UBS_MAX_NQUEUE
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#define UBS_MAX_NQUEUE 60
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#endif
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#define UBS_MAX_SCATTER 64 /* Maximum scatter/gather depth */
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#ifndef UBS_MAX_AGGR
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#define UBS_MAX_AGGR 5 /* Maximum aggregation count */
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#endif
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#define UBSEC_CARD(sid) (((sid) & 0xf0000000) >> 28)
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#define UBSEC_SESSION(sid) ( (sid) & 0x0fffffff)
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#define UBSEC_SID(crd, sesn) (((crd) << 28) | ((sesn) & 0x0fffffff))
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#define UBS_DEF_RTY 0xff /* PCI Retry Timeout */
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#define UBS_DEF_TOUT 0xff /* PCI TRDY Timeout */
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#define UBS_DEF_CACHELINE 0x01 /* Cache Line setting */
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#ifdef _KERNEL
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struct ubsec_dma_alloc {
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u_int32_t dma_paddr;
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caddr_t dma_vaddr;
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bus_dma_tag_t dma_tag;
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bus_dmamap_t dma_map;
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bus_dma_segment_t dma_seg;
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bus_size_t dma_size;
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int dma_nseg;
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};
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struct ubsec_q2 {
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SIMPLEQ_ENTRY(ubsec_q2) q_next;
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struct ubsec_dma_alloc q_mcr;
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struct ubsec_dma_alloc q_ctx;
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u_int q_type;
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};
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struct ubsec_q2_rng {
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struct ubsec_q2 rng_q;
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struct ubsec_dma_alloc rng_buf;
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int rng_used;
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};
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/* C = (M ^ E) mod N */
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#define UBS_MODEXP_PAR_M 0
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#define UBS_MODEXP_PAR_E 1
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#define UBS_MODEXP_PAR_N 2
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#define UBS_MODEXP_PAR_C 3
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struct ubsec_q2_modexp {
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struct ubsec_q2 me_q;
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struct cryptkop * me_krp;
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struct ubsec_dma_alloc me_M;
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struct ubsec_dma_alloc me_E;
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struct ubsec_dma_alloc me_C;
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struct ubsec_dma_alloc me_epb;
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int me_modbits;
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int me_shiftbits;
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int me_normbits;
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};
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#define UBS_RSAPRIV_PAR_P 0
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#define UBS_RSAPRIV_PAR_Q 1
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#define UBS_RSAPRIV_PAR_DP 2
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#define UBS_RSAPRIV_PAR_DQ 3
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#define UBS_RSAPRIV_PAR_PINV 4
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#define UBS_RSAPRIV_PAR_MSGIN 5
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#define UBS_RSAPRIV_PAR_MSGOUT 6
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struct ubsec_q2_rsapriv {
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struct ubsec_q2 rpr_q;
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struct cryptkop * rpr_krp;
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struct ubsec_dma_alloc rpr_msgin;
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struct ubsec_dma_alloc rpr_msgout;
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};
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#define UBSEC_RNG_BUFSIZ 16 /* measured in 32bit words */
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struct ubsec_dmachunk {
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struct ubsec_mcr d_mcr;
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struct ubsec_mcr_add d_mcradd[UBS_MAX_AGGR-1];
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struct ubsec_pktbuf d_sbuf[UBS_MAX_SCATTER-1];
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struct ubsec_pktbuf d_dbuf[UBS_MAX_SCATTER-1];
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u_int32_t d_macbuf[5];
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union {
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struct ubsec_pktctx_long ctxl;
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struct ubsec_pktctx ctx;
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} d_ctx;
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};
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struct ubsec_dma {
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SIMPLEQ_ENTRY(ubsec_dma) d_next;
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struct ubsec_dmachunk *d_dma;
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struct ubsec_dma_alloc d_alloc;
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};
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#define UBS_FLAGS_KEY 0x01 /* has key accelerator */
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#define UBS_FLAGS_LONGCTX 0x02 /* uses long ipsec ctx */
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#define UBS_FLAGS_BIGKEY 0x04 /* 2048bit keys */
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#define UBS_FLAGS_HWNORM 0x08 /* hardware normalization */
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#define UBS_FLAGS_RNG 0x10 /* hardware rng */
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struct ubsec_operand {
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union {
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struct mbuf *m;
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struct uio *io;
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} u;
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bus_dmamap_t map;
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bus_size_t mapsize;
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int nsegs;
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bus_dma_segment_t segs[UBS_MAX_SCATTER];
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};
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struct ubsec_q {
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SIMPLEQ_ENTRY(ubsec_q) q_next;
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int q_nstacked_mcrs;
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struct ubsec_q *q_stacked_mcr[UBS_MAX_AGGR-1];
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struct cryptop *q_crp;
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struct ubsec_dma *q_dma;
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struct ubsec_operand q_src;
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struct ubsec_operand q_dst;
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int q_sesn;
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int q_flags;
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};
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#define q_src_m q_src.u.m
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#define q_src_io q_src.u.io
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#define q_src_map q_src.map
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#define q_src_nsegs q_src.nsegs
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#define q_src_segs q_src.segs
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#define q_src_mapsize q_src.mapsize
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#define q_dst_m q_dst.u.m
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#define q_dst_io q_dst.u.io
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#define q_dst_map q_dst.map
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#define q_dst_nsegs q_dst.nsegs
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#define q_dst_segs q_dst.segs
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#define q_dst_mapsize q_dst.mapsize
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struct rndstate_test;
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struct ubsec_softc {
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device_t sc_dev; /* device backpointer */
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struct resource *sc_irq;
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void *sc_ih; /* interrupt handler cookie */
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bus_space_handle_t sc_sh; /* memory handle */
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bus_space_tag_t sc_st; /* memory tag */
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struct resource *sc_sr; /* memory resource */
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bus_dma_tag_t sc_dmat; /* dma tag */
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int sc_flags; /* device specific flags */
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int sc_suspended;
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int sc_needwakeup; /* notify crypto layer */
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u_int32_t sc_statmask; /* interrupt status mask */
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int32_t sc_cid; /* crypto tag */
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struct mtx sc_mcr1lock; /* mcr1 operation lock */
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SIMPLEQ_HEAD(,ubsec_q) sc_queue; /* packet queue, mcr1 */
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int sc_nqueue; /* count enqueued, mcr1 */
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SIMPLEQ_HEAD(,ubsec_q) sc_qchip; /* on chip, mcr1 */
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int sc_nqchip; /* count on chip, mcr1 */
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struct mtx sc_freeqlock; /* freequeue lock */
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SIMPLEQ_HEAD(,ubsec_q) sc_freequeue; /* list of free queue elements */
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struct mtx sc_mcr2lock; /* mcr2 operation lock */
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SIMPLEQ_HEAD(,ubsec_q2) sc_queue2; /* packet queue, mcr2 */
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int sc_nqueue2; /* count enqueued, mcr2 */
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SIMPLEQ_HEAD(,ubsec_q2) sc_qchip2; /* on chip, mcr2 */
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int sc_nsessions; /* # of sessions */
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struct ubsec_session *sc_sessions; /* sessions */
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struct callout sc_rngto; /* rng timeout */
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int sc_rnghz; /* rng poll time */
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struct ubsec_q2_rng sc_rng;
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struct rndtest_state *sc_rndtest; /* RNG test state */
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void (*sc_harvest)(struct rndtest_state *,
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void *, u_int);
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struct ubsec_dma sc_dmaa[UBS_MAX_NQUEUE];
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struct ubsec_q *sc_queuea[UBS_MAX_NQUEUE];
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SIMPLEQ_HEAD(,ubsec_q2) sc_q2free; /* free list */
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};
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#define UBSEC_QFLAGS_COPYOUTIV 0x1
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struct ubsec_session {
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u_int32_t ses_used;
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u_int32_t ses_deskey[6]; /* 3DES key */
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u_int32_t ses_hminner[5]; /* hmac inner state */
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u_int32_t ses_hmouter[5]; /* hmac outer state */
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u_int32_t ses_iv[2]; /* [3]DES iv */
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};
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#endif /* _KERNEL */
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struct ubsec_stats {
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u_int64_t hst_ibytes;
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u_int64_t hst_obytes;
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u_int32_t hst_ipackets;
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u_int32_t hst_opackets;
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u_int32_t hst_invalid; /* invalid argument */
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u_int32_t hst_badsession; /* invalid session id */
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u_int32_t hst_badflags; /* flags indicate !(mbuf | uio) */
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u_int32_t hst_nodesc; /* op submitted w/o descriptors */
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u_int32_t hst_badalg; /* unsupported algorithm */
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u_int32_t hst_nomem;
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u_int32_t hst_queuefull;
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u_int32_t hst_dmaerr;
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u_int32_t hst_mcrerr;
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u_int32_t hst_nodmafree;
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u_int32_t hst_lenmismatch; /* enc/auth lengths different */
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u_int32_t hst_skipmismatch; /* enc part begins before auth part */
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u_int32_t hst_iovmisaligned; /* iov op not aligned */
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u_int32_t hst_noirq; /* IRQ for no reason */
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u_int32_t hst_unaligned; /* unaligned src caused copy */
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u_int32_t hst_nomap; /* bus_dmamap_create failed */
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u_int32_t hst_noload; /* bus_dmamap_load_* failed */
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u_int32_t hst_nombuf; /* MGET* failed */
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u_int32_t hst_nomcl; /* MCLGET* failed */
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u_int32_t hst_totbatch; /* ops submitted w/o interrupt */
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u_int32_t hst_maxbatch; /* max ops submitted together */
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u_int32_t hst_maxqueue; /* max ops queued for submission */
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u_int32_t hst_maxqchip; /* max mcr1 ops out for processing */
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u_int32_t hst_mcr1full; /* MCR1 too busy to take ops */
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u_int32_t hst_rng; /* RNG requests */
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u_int32_t hst_modexp; /* MOD EXP requests */
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u_int32_t hst_modexpcrt; /* MOD EXP CRT requests */
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};
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