7815d3948c
from x86 to use smp_ipi_mtx spin lock not only for smp_rendezvous_cpus()
but also for the MD cache invalidation, TLB demapping and remote register
reading IPIs due to the following reasons:
- The cross-IPI SMP deadlock x86 otherwise is subject to can't happen on
sparc64. That's because on sparc64, spin locks don't disable interrupts
completely but only raise the processor interrupt level to PIL_TICK. This
means that IPIs still get delivered and direct dispatch IPIs such as the
cache invalidation etc. IPIs in question are still executed.
- In smp_rendezvous_cpus(), smp_ipi_mtx is held not only while sending an
IPI_RENDEZVOUS, but until all CPUs have processed smp_rendezvous_action().
Consequently, smp_ipi_mtx may be locked for an extended amount of time as
queued IPIs (as opposed to the direct ones) such as IPI_RENDEZVOUS are
scheduled via a soft interrupt. Moreover, given that this soft interrupt
is only delivered at PIL_RENDEZVOUS, processing of smp_rendezvous_action()
on a target may be interrupted by f. e. a tick interrupt at PIL_TICK, in
turn leading to the target in question trying to send an IPI by itself
while IPI_RENDEZVOUS isn't fully handled, yet, and, thus, resulting in a
deadlock.
o As mentioned in the commit message of r245850, on least some sun4u platforms
concurrent sending of IPIs by different CPUs is fatal. Therefore, hold the
reintroduced MD ipi_mtx also while delivering cross-traps via MI helpers,
i. e. ipi_{all_but_self,cpu,selected}().
o Akin to x86, let the last CPU to process cpu_mp_bootstrap() set smp_started
instead of the BSP in cpu_mp_unleash(). This ensures that all APs actually
are started, when smp_started is no longer 0.
o In all MD and MI IPI helpers, check for smp_started == 1 rather than for
smp_cpus > 1 or nothing at all. This avoids races during boot causing IPIs
trying to be delivered to APs that in fact aren't up and running, yet.
While at it, move setting of the cpu_ipi_{selected,single}() pointers to
the appropriate delivery functions from mp_init() to cpu_mp_start() where
it's better suited and allows to get rid of the global isjbus variable.
o Given that now concurrent IPI delivery no longer is possible, also nuke
the delays before completely disabling interrupts again in the CPU-specific
cross-trap delivery functions, previously giving other CPUs a window for
sending IPIs on their part. Actually, we now should be able to entirely get
rid of completely disabling interrupts in these functions. Such a change
needs more testing, though.
o In {s,}tick_get_timecount_mp(), make the {s,}tick variable static. While not
necessary for correctness, this avoids page faults when accessing the stack
of a foreign CPU as {s,}tick now is locked into the TLBs as part of static
kernel data. Hence, {s,}tick_get_timecount_mp() always execute as fast as
possible, avoiding jitter.
PR: 201245
MFC after: 3 days
401 lines
8.6 KiB
C
401 lines
8.6 KiB
C
/*-
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* Copyright (c) 2001 Jake Burkholder.
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* Copyright (c) 2007 - 2011 Marius Strobl <marius@FreeBSD.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _MACHINE_SMP_H_
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#define _MACHINE_SMP_H_
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#ifdef SMP
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#define CPU_TICKSYNC 1
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#define CPU_STICKSYNC 2
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#define CPU_INIT 3
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#define CPU_BOOTSTRAP 4
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#ifndef LOCORE
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#include <sys/param.h>
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#include <sys/cpuset.h>
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#include <sys/lock.h>
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#include <sys/mutex.h>
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#include <sys/proc.h>
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#include <sys/sched.h>
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#include <sys/smp.h>
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#include <machine/intr_machdep.h>
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#include <machine/tte.h>
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#define IDR_BUSY 0x0000000000000001ULL
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#define IDR_NACK 0x0000000000000002ULL
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#define IDR_CHEETAH_ALL_BUSY 0x5555555555555555ULL
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#define IDR_CHEETAH_ALL_NACK (~IDR_CHEETAH_ALL_BUSY)
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#define IDR_CHEETAH_MAX_BN_PAIRS 32
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#define IDR_JALAPENO_MAX_BN_PAIRS 4
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#define IDC_ITID_SHIFT 14
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#define IDC_BN_SHIFT 24
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#define IPI_AST PIL_AST
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#define IPI_RENDEZVOUS PIL_RENDEZVOUS
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#define IPI_PREEMPT PIL_PREEMPT
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#define IPI_HARDCLOCK PIL_HARDCLOCK
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#define IPI_STOP PIL_STOP
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#define IPI_STOP_HARD PIL_STOP
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#define IPI_RETRIES 5000
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struct cpu_start_args {
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u_int csa_count;
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u_int csa_mid;
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u_int csa_state;
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vm_offset_t csa_pcpu;
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u_long csa_tick;
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u_long csa_stick;
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u_long csa_ver;
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struct tte csa_ttes[PCPU_PAGES];
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};
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struct ipi_cache_args {
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cpuset_t ica_mask;
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vm_paddr_t ica_pa;
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};
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struct ipi_rd_args {
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cpuset_t ira_mask;
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register_t *ira_val;
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};
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struct ipi_tlb_args {
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cpuset_t ita_mask;
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struct pmap *ita_pmap;
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u_long ita_start;
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u_long ita_end;
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};
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#define ita_va ita_start
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struct pcb;
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struct pcpu;
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extern struct pcb stoppcbs[];
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void cpu_mp_bootstrap(struct pcpu *pc);
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void cpu_mp_shutdown(void);
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typedef void cpu_ipi_selected_t(cpuset_t, u_long, u_long, u_long);
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extern cpu_ipi_selected_t *cpu_ipi_selected;
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typedef void cpu_ipi_single_t(u_int, u_long, u_long, u_long);
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extern cpu_ipi_single_t *cpu_ipi_single;
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void mp_init(void);
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extern struct mtx ipi_mtx;
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extern struct ipi_cache_args ipi_cache_args;
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extern struct ipi_rd_args ipi_rd_args;
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extern struct ipi_tlb_args ipi_tlb_args;
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extern char *mp_tramp_code;
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extern u_long mp_tramp_code_len;
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extern u_long mp_tramp_tlb_slots;
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extern u_long mp_tramp_func;
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extern void mp_startup(void);
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extern char tl_ipi_cheetah_dcache_page_inval[];
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extern char tl_ipi_spitfire_dcache_page_inval[];
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extern char tl_ipi_spitfire_icache_page_inval[];
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extern char tl_ipi_level[];
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extern char tl_ipi_stick_rd[];
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extern char tl_ipi_tick_rd[];
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extern char tl_ipi_tlb_context_demap[];
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extern char tl_ipi_tlb_page_demap[];
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extern char tl_ipi_tlb_range_demap[];
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static __inline void
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ipi_all_but_self(u_int ipi)
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{
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cpuset_t cpus;
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if (__predict_false(smp_started == 0))
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return;
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cpus = all_cpus;
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sched_pin();
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CPU_CLR(PCPU_GET(cpuid), &cpus);
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mtx_lock_spin(&ipi_mtx);
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cpu_ipi_selected(cpus, 0, (u_long)tl_ipi_level, ipi);
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mtx_unlock_spin(&ipi_mtx);
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sched_unpin();
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}
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static __inline void
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ipi_selected(cpuset_t cpus, u_int ipi)
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{
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if (__predict_false(smp_started == 0 || CPU_EMPTY(&cpus)))
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return;
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mtx_lock_spin(&ipi_mtx);
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cpu_ipi_selected(cpus, 0, (u_long)tl_ipi_level, ipi);
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mtx_unlock_spin(&ipi_mtx);
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}
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static __inline void
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ipi_cpu(int cpu, u_int ipi)
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{
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if (__predict_false(smp_started == 0))
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return;
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mtx_lock_spin(&ipi_mtx);
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cpu_ipi_single(cpu, 0, (u_long)tl_ipi_level, ipi);
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mtx_unlock_spin(&ipi_mtx);
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}
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#if defined(_MACHINE_PMAP_H_) && defined(_SYS_MUTEX_H_)
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static __inline void *
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ipi_dcache_page_inval(void *func, vm_paddr_t pa)
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{
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struct ipi_cache_args *ica;
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if (__predict_false(smp_started == 0))
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return (NULL);
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sched_pin();
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ica = &ipi_cache_args;
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mtx_lock_spin(&ipi_mtx);
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ica->ica_mask = all_cpus;
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CPU_CLR(PCPU_GET(cpuid), &ica->ica_mask);
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ica->ica_pa = pa;
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cpu_ipi_selected(ica->ica_mask, 0, (u_long)func, (u_long)ica);
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return (&ica->ica_mask);
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}
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static __inline void *
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ipi_icache_page_inval(void *func, vm_paddr_t pa)
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{
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struct ipi_cache_args *ica;
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if (__predict_false(smp_started == 0))
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return (NULL);
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sched_pin();
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ica = &ipi_cache_args;
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mtx_lock_spin(&ipi_mtx);
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ica->ica_mask = all_cpus;
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CPU_CLR(PCPU_GET(cpuid), &ica->ica_mask);
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ica->ica_pa = pa;
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cpu_ipi_selected(ica->ica_mask, 0, (u_long)func, (u_long)ica);
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return (&ica->ica_mask);
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}
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static __inline void *
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ipi_rd(u_int cpu, void *func, u_long *val)
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{
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struct ipi_rd_args *ira;
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if (__predict_false(smp_started == 0))
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return (NULL);
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sched_pin();
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ira = &ipi_rd_args;
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mtx_lock_spin(&ipi_mtx);
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CPU_SETOF(cpu, &ira->ira_mask);
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ira->ira_val = val;
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cpu_ipi_single(cpu, 0, (u_long)func, (u_long)ira);
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return (&ira->ira_mask);
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}
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static __inline void *
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ipi_tlb_context_demap(struct pmap *pm)
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{
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struct ipi_tlb_args *ita;
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cpuset_t cpus;
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if (__predict_false(smp_started == 0))
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return (NULL);
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sched_pin();
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cpus = pm->pm_active;
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CPU_AND(&cpus, &all_cpus);
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CPU_CLR(PCPU_GET(cpuid), &cpus);
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if (CPU_EMPTY(&cpus)) {
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sched_unpin();
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return (NULL);
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}
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ita = &ipi_tlb_args;
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mtx_lock_spin(&ipi_mtx);
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ita->ita_mask = cpus;
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ita->ita_pmap = pm;
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cpu_ipi_selected(cpus, 0, (u_long)tl_ipi_tlb_context_demap,
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(u_long)ita);
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return (&ita->ita_mask);
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}
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static __inline void *
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ipi_tlb_page_demap(struct pmap *pm, vm_offset_t va)
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{
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struct ipi_tlb_args *ita;
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cpuset_t cpus;
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if (__predict_false(smp_started == 0))
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return (NULL);
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sched_pin();
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cpus = pm->pm_active;
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CPU_AND(&cpus, &all_cpus);
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CPU_CLR(PCPU_GET(cpuid), &cpus);
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if (CPU_EMPTY(&cpus)) {
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sched_unpin();
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return (NULL);
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}
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ita = &ipi_tlb_args;
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mtx_lock_spin(&ipi_mtx);
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ita->ita_mask = cpus;
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ita->ita_pmap = pm;
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ita->ita_va = va;
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cpu_ipi_selected(cpus, 0, (u_long)tl_ipi_tlb_page_demap, (u_long)ita);
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return (&ita->ita_mask);
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}
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static __inline void *
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ipi_tlb_range_demap(struct pmap *pm, vm_offset_t start, vm_offset_t end)
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{
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struct ipi_tlb_args *ita;
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cpuset_t cpus;
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if (__predict_false(smp_started == 0))
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return (NULL);
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sched_pin();
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cpus = pm->pm_active;
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CPU_AND(&cpus, &all_cpus);
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CPU_CLR(PCPU_GET(cpuid), &cpus);
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if (CPU_EMPTY(&cpus)) {
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sched_unpin();
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return (NULL);
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}
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ita = &ipi_tlb_args;
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mtx_lock_spin(&ipi_mtx);
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ita->ita_mask = cpus;
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ita->ita_pmap = pm;
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ita->ita_start = start;
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ita->ita_end = end;
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cpu_ipi_selected(cpus, 0, (u_long)tl_ipi_tlb_range_demap,
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(u_long)ita);
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return (&ita->ita_mask);
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}
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static __inline void
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ipi_wait(void *cookie)
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{
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volatile cpuset_t *mask;
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if (__predict_false((mask = cookie) != NULL)) {
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while (!CPU_EMPTY(mask))
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;
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mtx_unlock_spin(&ipi_mtx);
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sched_unpin();
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}
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}
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#endif /* _MACHINE_PMAP_H_ && _SYS_MUTEX_H_ */
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#endif /* !LOCORE */
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#else
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#ifndef LOCORE
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static __inline void *
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ipi_dcache_page_inval(void *func __unused, vm_paddr_t pa __unused)
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{
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return (NULL);
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}
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static __inline void *
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ipi_icache_page_inval(void *func __unused, vm_paddr_t pa __unused)
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{
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return (NULL);
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}
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static __inline void *
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ipi_rd(u_int cpu __unused, void *func __unused, u_long *val __unused)
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{
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return (NULL);
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}
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static __inline void *
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ipi_tlb_context_demap(struct pmap *pm __unused)
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{
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return (NULL);
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}
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static __inline void *
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ipi_tlb_page_demap(struct pmap *pm __unused, vm_offset_t va __unused)
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{
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return (NULL);
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}
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static __inline void *
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ipi_tlb_range_demap(struct pmap *pm __unused, vm_offset_t start __unused,
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__unused vm_offset_t end)
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{
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return (NULL);
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}
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static __inline void
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ipi_wait(void *cookie __unused)
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{
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}
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static __inline void
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tl_ipi_cheetah_dcache_page_inval(void)
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{
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}
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static __inline void
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tl_ipi_spitfire_dcache_page_inval(void)
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{
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}
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static __inline void
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tl_ipi_spitfire_icache_page_inval(void)
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{
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}
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#endif /* !LOCORE */
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#endif /* SMP */
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#endif /* !_MACHINE_SMP_H_ */
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