96c85efb4b
mp_maxid or CPU_FOREACH() as appropriate. This fixes a number of places in the kernel that assumed CPU IDs are dense in [0, mp_ncpus) and would try, for example, to run tasks on CPUs that did not exist or to allocate too few buffers on systems with sparse CPU IDs in which there are holes in the range and mp_maxid > mp_ncpus. Such circumstances generally occur on systems with SMT, but on which SMT is disabled. This patch restores system operation at least on POWER8 systems configured in this way. There are a number of other places in the kernel with potential problems in these situations, but where sparse CPU IDs are not currently known to occur, mostly in the ARM machine-dependent code. These will be fixed in a follow-up commit after the stable/11 branch. PR: kern/210106 Reviewed by: jhb Approved by: re (glebius)
179 lines
4.4 KiB
C
179 lines
4.4 KiB
C
/*-
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* Copyright (c) 2012 Konstantin Belousov <kib@FreeBSD.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef __MACHINE_COUNTER_H__
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#define __MACHINE_COUNTER_H__
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#include <sys/pcpu.h>
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#ifdef INVARIANTS
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#include <sys/proc.h>
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#endif
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#include <machine/md_var.h>
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#include <machine/specialreg.h>
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#define counter_enter() do { \
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if ((cpu_feature & CPUID_CX8) == 0) \
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critical_enter(); \
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} while (0)
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#define counter_exit() do { \
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if ((cpu_feature & CPUID_CX8) == 0) \
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critical_exit(); \
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} while (0)
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extern struct pcpu __pcpu[MAXCPU];
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static inline void
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counter_64_inc_8b(uint64_t *p, int64_t inc)
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{
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__asm __volatile(
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"movl %%fs:(%%esi),%%eax\n\t"
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"movl %%fs:4(%%esi),%%edx\n"
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"1:\n\t"
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"movl %%eax,%%ebx\n\t"
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"movl %%edx,%%ecx\n\t"
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"addl (%%edi),%%ebx\n\t"
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"adcl 4(%%edi),%%ecx\n\t"
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"cmpxchg8b %%fs:(%%esi)\n\t"
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"jnz 1b"
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:
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: "S" ((char *)p - (char *)&__pcpu[0]), "D" (&inc)
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: "memory", "cc", "eax", "edx", "ebx", "ecx");
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}
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#ifdef IN_SUBR_COUNTER_C
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static inline uint64_t
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counter_u64_read_one_8b(uint64_t *p)
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{
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uint32_t res_lo, res_high;
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__asm __volatile(
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"movl %%eax,%%ebx\n\t"
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"movl %%edx,%%ecx\n\t"
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"cmpxchg8b (%2)"
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: "=a" (res_lo), "=d"(res_high)
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: "SD" (p)
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: "cc", "ebx", "ecx");
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return (res_lo + ((uint64_t)res_high << 32));
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}
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static inline uint64_t
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counter_u64_fetch_inline(uint64_t *p)
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{
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uint64_t res;
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int i;
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res = 0;
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if ((cpu_feature & CPUID_CX8) == 0) {
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/*
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* The machines without cmpxchg8b are not SMP.
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* Disabling the preemption provides atomicity of the
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* counter reading, since update is done in the
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* critical section as well.
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*/
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critical_enter();
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CPU_FOREACH(i) {
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res += *(uint64_t *)((char *)p +
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sizeof(struct pcpu) * i);
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}
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critical_exit();
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} else {
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CPU_FOREACH(i)
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res += counter_u64_read_one_8b((uint64_t *)((char *)p +
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sizeof(struct pcpu) * i));
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}
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return (res);
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}
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static inline void
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counter_u64_zero_one_8b(uint64_t *p)
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{
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__asm __volatile(
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"movl (%0),%%eax\n\t"
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"movl 4(%0),%%edx\n"
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"xorl %%ebx,%%ebx\n\t"
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"xorl %%ecx,%%ecx\n\t"
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"1:\n\t"
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"cmpxchg8b (%0)\n\t"
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"jnz 1b"
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:
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: "SD" (p)
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: "memory", "cc", "eax", "edx", "ebx", "ecx");
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}
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static void
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counter_u64_zero_one_cpu(void *arg)
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{
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uint64_t *p;
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p = (uint64_t *)((char *)arg + sizeof(struct pcpu) * PCPU_GET(cpuid));
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counter_u64_zero_one_8b(p);
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}
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static inline void
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counter_u64_zero_inline(counter_u64_t c)
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{
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int i;
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if ((cpu_feature & CPUID_CX8) == 0) {
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critical_enter();
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CPU_FOREACH(i)
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*(uint64_t *)((char *)c + sizeof(struct pcpu) * i) = 0;
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critical_exit();
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} else {
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smp_rendezvous(smp_no_rendevous_barrier,
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counter_u64_zero_one_cpu, smp_no_rendevous_barrier, c);
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}
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}
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#endif
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#define counter_u64_add_protected(c, inc) do { \
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if ((cpu_feature & CPUID_CX8) == 0) { \
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CRITICAL_ASSERT(curthread); \
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*(uint64_t *)zpcpu_get(c) += (inc); \
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} else \
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counter_64_inc_8b((c), (inc)); \
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} while (0)
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static inline void
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counter_u64_add(counter_u64_t c, int64_t inc)
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{
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if ((cpu_feature & CPUID_CX8) == 0) {
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critical_enter();
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*(uint64_t *)zpcpu_get(c) += inc;
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critical_exit();
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} else {
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counter_64_inc_8b(c, inc);
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}
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}
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#endif /* ! __MACHINE_COUNTER_H__ */
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