287 lines
7.1 KiB
C
287 lines
7.1 KiB
C
/*-
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* Copyright (c) 2001 Cubical Solutions Ltd. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/* capi/iavc/iavc_card.c
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* The AVM ISDN controllers' card specific support routines.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/kernel.h>
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#include <sys/systm.h>
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#include <sys/mbuf.h>
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#include <sys/socket.h>
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#include <net/if.h>
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#include <machine/clock.h>
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#include <machine/bus.h>
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#include <machine/resource.h>
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#include <sys/bus.h>
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#include <sys/rman.h>
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#include <machine/i4b_debug.h>
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#include <machine/i4b_ioctl.h>
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#include <machine/i4b_trace.h>
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#include <i4b/include/i4b_global.h>
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#include <i4b/include/i4b_l3l4.h>
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#include <i4b/include/i4b_mbuf.h>
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#include <i4b/capi/capi.h>
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#include <i4b/capi/iavc/iavc.h>
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/*
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// AVM B1 (active BRI, PIO mode)
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*/
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int b1_detect(iavc_softc_t *sc)
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{
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if ((iavc_read_port(sc, B1_INSTAT) & 0xfc) ||
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(iavc_read_port(sc, B1_OUTSTAT) & 0xfc))
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return (1);
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b1io_outp(sc, B1_INSTAT, 0x02);
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b1io_outp(sc, B1_OUTSTAT, 0x02);
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if ((iavc_read_port(sc, B1_INSTAT) & 0xfe) != 2 ||
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(iavc_read_port(sc, B1_OUTSTAT) & 0xfe) != 2)
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return (2);
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b1io_outp(sc, B1_INSTAT, 0x00);
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b1io_outp(sc, B1_OUTSTAT, 0x00);
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if ((iavc_read_port(sc, B1_INSTAT) & 0xfe) ||
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(iavc_read_port(sc, B1_OUTSTAT) & 0xfe))
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return (3);
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return (0); /* found */
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}
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void b1_disable_irq(iavc_softc_t *sc)
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{
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b1io_outp(sc, B1_INSTAT, 0x00);
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}
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void b1_reset(iavc_softc_t *sc)
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{
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b1io_outp(sc, B1_RESET, 0);
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DELAY(55*2*1000);
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b1io_outp(sc, B1_RESET, 1);
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DELAY(55*2*1000);
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b1io_outp(sc, B1_RESET, 0);
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DELAY(55*2*1000);
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}
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/*
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// Newer PCI-based B1's, and T1's, supports DMA
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*/
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int b1dma_detect(iavc_softc_t *sc)
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{
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AMCC_WRITE(sc, AMCC_MCSR, 0);
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DELAY(10*1000);
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AMCC_WRITE(sc, AMCC_MCSR, 0x0f000000);
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DELAY(10*1000);
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AMCC_WRITE(sc, AMCC_MCSR, 0);
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DELAY(42*1000);
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AMCC_WRITE(sc, AMCC_RXLEN, 0);
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AMCC_WRITE(sc, AMCC_TXLEN, 0);
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sc->sc_csr = 0;
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AMCC_WRITE(sc, AMCC_INTCSR, sc->sc_csr);
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if (AMCC_READ(sc, AMCC_INTCSR) != 0)
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return 1;
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AMCC_WRITE(sc, AMCC_RXPTR, 0xffffffff);
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AMCC_WRITE(sc, AMCC_TXPTR, 0xffffffff);
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if ((AMCC_READ(sc, AMCC_RXPTR) != 0xfffffffc) ||
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(AMCC_READ(sc, AMCC_TXPTR) != 0xfffffffc))
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return 2;
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AMCC_WRITE(sc, AMCC_RXPTR, 0);
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AMCC_WRITE(sc, AMCC_TXPTR, 0);
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if ((AMCC_READ(sc, AMCC_RXPTR) != 0) ||
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(AMCC_READ(sc, AMCC_TXPTR) != 0))
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return 3;
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iavc_write_port(sc, 0x10, 0x00);
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iavc_write_port(sc, 0x07, 0x00);
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iavc_write_port(sc, 0x02, 0x02);
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iavc_write_port(sc, 0x03, 0x02);
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if (((iavc_read_port(sc, 0x02) & 0xfe) != 0x02) ||
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(iavc_read_port(sc, 0x03) != 0x03))
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return 4;
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iavc_write_port(sc, 0x02, 0x00);
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iavc_write_port(sc, 0x03, 0x00);
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if (((iavc_read_port(sc, 0x02) & 0xfe) != 0x00) ||
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(iavc_read_port(sc, 0x03) != 0x01))
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return 5;
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return (0); /* found */
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}
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void b1dma_reset(iavc_softc_t *sc)
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{
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int s = SPLI4B();
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sc->sc_csr = 0;
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AMCC_WRITE(sc, AMCC_INTCSR, sc->sc_csr);
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AMCC_WRITE(sc, AMCC_MCSR, 0);
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AMCC_WRITE(sc, AMCC_RXLEN, 0);
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AMCC_WRITE(sc, AMCC_TXLEN, 0);
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iavc_write_port(sc, 0x10, 0x00); /* XXX magic numbers from */
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iavc_write_port(sc, 0x07, 0x00); /* XXX the linux driver */
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splx(s);
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AMCC_WRITE(sc, AMCC_MCSR, 0);
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DELAY(10 * 1000);
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AMCC_WRITE(sc, AMCC_MCSR, 0x0f000000);
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DELAY(10 * 1000);
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AMCC_WRITE(sc, AMCC_MCSR, 0);
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DELAY(42 * 1000);
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}
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/*
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// AVM T1 (active PRI)
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*/
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/* XXX how do these differ from b1io_{read,write}_reg()? XXX */
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static int b1dma_tx_empty(int iobase)
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{ return inb(iobase + 3) & 1; }
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static int b1dma_rx_full(int iobase)
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{ return inb(iobase + 2) & 1; }
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static int b1dma_tolink(iavc_softc_t *sc, void *buf, int len)
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{
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volatile int spin;
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char *s = (char*) buf;
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while (len--) {
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spin = 0;
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while (!b1dma_tx_empty(sc->sc_iobase) && spin < 100000)
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spin++;
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if (!b1dma_tx_empty(sc->sc_iobase))
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return -1;
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t1io_outp(sc, 1, *s++);
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}
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return 0;
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}
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static int b1dma_fromlink(iavc_softc_t *sc, void *buf, int len)
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{
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volatile int spin;
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char *s = (char*) buf;
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while (len--) {
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spin = 0;
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while (!b1dma_rx_full(sc->sc_iobase) && spin < 100000)
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spin++;
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if (!b1dma_rx_full(sc->sc_iobase))
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return -1;
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*s++ = t1io_inp(sc, 0);
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}
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return 0;
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}
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static int WriteReg(iavc_softc_t *sc, u_int32_t reg, u_int8_t val)
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{
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u_int8_t cmd = 0;
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if (b1dma_tolink(sc, &cmd, 1) == 0 &&
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b1dma_tolink(sc, ®, 4) == 0) {
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u_int32_t tmp = val;
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return b1dma_tolink(sc, &tmp, 4);
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}
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return -1;
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}
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static u_int8_t ReadReg(iavc_softc_t *sc, u_int32_t reg)
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{
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u_int8_t cmd = 1;
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if (b1dma_tolink(sc, &cmd, 1) == 0 &&
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b1dma_tolink(sc, ®, 4) == 0) {
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u_int32_t tmp;
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if (b1dma_fromlink(sc, &tmp, 4) == 0)
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return (u_int8_t) tmp;
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}
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return 0xff;
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}
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int t1_detect(iavc_softc_t *sc)
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{
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int ret = b1dma_detect(sc);
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if (ret) return ret;
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if ((WriteReg(sc, 0x80001000, 0x11) != 0) ||
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(WriteReg(sc, 0x80101000, 0x22) != 0) ||
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(WriteReg(sc, 0x80201000, 0x33) != 0) ||
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(WriteReg(sc, 0x80301000, 0x44) != 0))
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return 6;
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if ((ReadReg(sc, 0x80001000) != 0x11) ||
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(ReadReg(sc, 0x80101000) != 0x22) ||
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(ReadReg(sc, 0x80201000) != 0x33) ||
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(ReadReg(sc, 0x80301000) != 0x44))
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return 7;
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if ((WriteReg(sc, 0x80001000, 0x55) != 0) ||
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(WriteReg(sc, 0x80101000, 0x66) != 0) ||
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(WriteReg(sc, 0x80201000, 0x77) != 0) ||
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(WriteReg(sc, 0x80301000, 0x88) != 0))
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return 8;
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if ((ReadReg(sc, 0x80001000) != 0x55) ||
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(ReadReg(sc, 0x80101000) != 0x66) ||
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(ReadReg(sc, 0x80201000) != 0x77) ||
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(ReadReg(sc, 0x80301000) != 0x88))
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return 9;
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return 0; /* found */
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}
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void t1_disable_irq(iavc_softc_t *sc)
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{
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iavc_write_port(sc, T1_IRQMASTER, 0x00);
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}
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void t1_reset(iavc_softc_t *sc)
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{
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b1_reset(sc);
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iavc_write_port(sc, B1_INSTAT, 0x00);
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iavc_write_port(sc, B1_OUTSTAT, 0x00);
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iavc_write_port(sc, T1_IRQMASTER, 0x00);
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iavc_write_port(sc, T1_RESETBOARD, 0x0f);
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}
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