836 lines
27 KiB
C++
836 lines
27 KiB
C++
//===- SubtargetEmitter.cpp - Generate subtarget enumerations -------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This tablegen backend emits subtarget enumerations.
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//
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//===----------------------------------------------------------------------===//
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#include "CodeGenTarget.h"
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#include "CodeGenSchedule.h"
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#include "llvm/ADT/StringExtras.h"
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#include "llvm/MC/MCInstrItineraries.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/TableGen/Record.h"
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#include "llvm/TableGen/TableGenBackend.h"
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#include <algorithm>
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#include <map>
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#include <string>
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#include <vector>
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using namespace llvm;
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namespace {
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class SubtargetEmitter {
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RecordKeeper &Records;
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CodeGenSchedModels &SchedModels;
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std::string Target;
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void Enumeration(raw_ostream &OS, const char *ClassName, bool isBits);
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unsigned FeatureKeyValues(raw_ostream &OS);
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unsigned CPUKeyValues(raw_ostream &OS);
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void FormItineraryStageString(const std::string &Names,
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Record *ItinData, std::string &ItinString,
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unsigned &NStages);
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void FormItineraryOperandCycleString(Record *ItinData, std::string &ItinString,
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unsigned &NOperandCycles);
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void FormItineraryBypassString(const std::string &Names,
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Record *ItinData,
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std::string &ItinString, unsigned NOperandCycles);
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void EmitStageAndOperandCycleData(raw_ostream &OS,
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std::vector<std::vector<InstrItinerary> >
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&ProcItinLists);
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void EmitItineraries(raw_ostream &OS,
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std::vector<std::vector<InstrItinerary> >
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&ProcItinLists);
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void EmitProcessorProp(raw_ostream &OS, const Record *R, const char *Name,
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char Separator);
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void EmitProcessorModels(raw_ostream &OS);
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void EmitProcessorLookup(raw_ostream &OS);
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void EmitSchedModel(raw_ostream &OS);
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void ParseFeaturesFunction(raw_ostream &OS, unsigned NumFeatures,
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unsigned NumProcs);
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public:
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SubtargetEmitter(RecordKeeper &R, CodeGenTarget &TGT):
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Records(R), SchedModels(TGT.getSchedModels()), Target(TGT.getName()) {}
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void run(raw_ostream &o);
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};
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} // End anonymous namespace
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//
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// Enumeration - Emit the specified class as an enumeration.
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//
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void SubtargetEmitter::Enumeration(raw_ostream &OS,
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const char *ClassName,
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bool isBits) {
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// Get all records of class and sort
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std::vector<Record*> DefList = Records.getAllDerivedDefinitions(ClassName);
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std::sort(DefList.begin(), DefList.end(), LessRecord());
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unsigned N = DefList.size();
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if (N == 0)
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return;
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if (N > 64) {
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errs() << "Too many (> 64) subtarget features!\n";
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exit(1);
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}
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OS << "namespace " << Target << " {\n";
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// For bit flag enumerations with more than 32 items, emit constants.
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// Emit an enum for everything else.
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if (isBits && N > 32) {
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// For each record
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for (unsigned i = 0; i < N; i++) {
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// Next record
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Record *Def = DefList[i];
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// Get and emit name and expression (1 << i)
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OS << " const uint64_t " << Def->getName() << " = 1ULL << " << i << ";\n";
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}
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} else {
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// Open enumeration
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OS << "enum {\n";
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// For each record
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for (unsigned i = 0; i < N;) {
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// Next record
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Record *Def = DefList[i];
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// Get and emit name
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OS << " " << Def->getName();
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// If bit flags then emit expression (1 << i)
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if (isBits) OS << " = " << " 1ULL << " << i;
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// Depending on 'if more in the list' emit comma
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if (++i < N) OS << ",";
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OS << "\n";
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}
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// Close enumeration
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OS << "};\n";
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}
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OS << "}\n";
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}
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//
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// FeatureKeyValues - Emit data of all the subtarget features. Used by the
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// command line.
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//
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unsigned SubtargetEmitter::FeatureKeyValues(raw_ostream &OS) {
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// Gather and sort all the features
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std::vector<Record*> FeatureList =
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Records.getAllDerivedDefinitions("SubtargetFeature");
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if (FeatureList.empty())
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return 0;
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std::sort(FeatureList.begin(), FeatureList.end(), LessRecordFieldName());
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// Begin feature table
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OS << "// Sorted (by key) array of values for CPU features.\n"
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<< "extern const llvm::SubtargetFeatureKV " << Target
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<< "FeatureKV[] = {\n";
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// For each feature
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unsigned NumFeatures = 0;
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for (unsigned i = 0, N = FeatureList.size(); i < N; ++i) {
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// Next feature
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Record *Feature = FeatureList[i];
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const std::string &Name = Feature->getName();
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const std::string &CommandLineName = Feature->getValueAsString("Name");
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const std::string &Desc = Feature->getValueAsString("Desc");
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if (CommandLineName.empty()) continue;
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// Emit as { "feature", "description", featureEnum, i1 | i2 | ... | in }
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OS << " { "
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<< "\"" << CommandLineName << "\", "
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<< "\"" << Desc << "\", "
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<< Target << "::" << Name << ", ";
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const std::vector<Record*> &ImpliesList =
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Feature->getValueAsListOfDefs("Implies");
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if (ImpliesList.empty()) {
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OS << "0ULL";
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} else {
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for (unsigned j = 0, M = ImpliesList.size(); j < M;) {
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OS << Target << "::" << ImpliesList[j]->getName();
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if (++j < M) OS << " | ";
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}
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}
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OS << " }";
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++NumFeatures;
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// Depending on 'if more in the list' emit comma
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if ((i + 1) < N) OS << ",";
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OS << "\n";
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}
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// End feature table
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OS << "};\n";
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return NumFeatures;
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}
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//
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// CPUKeyValues - Emit data of all the subtarget processors. Used by command
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// line.
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//
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unsigned SubtargetEmitter::CPUKeyValues(raw_ostream &OS) {
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// Gather and sort processor information
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std::vector<Record*> ProcessorList =
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Records.getAllDerivedDefinitions("Processor");
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std::sort(ProcessorList.begin(), ProcessorList.end(), LessRecordFieldName());
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// Begin processor table
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OS << "// Sorted (by key) array of values for CPU subtype.\n"
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<< "extern const llvm::SubtargetFeatureKV " << Target
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<< "SubTypeKV[] = {\n";
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// For each processor
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for (unsigned i = 0, N = ProcessorList.size(); i < N;) {
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// Next processor
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Record *Processor = ProcessorList[i];
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const std::string &Name = Processor->getValueAsString("Name");
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const std::vector<Record*> &FeatureList =
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Processor->getValueAsListOfDefs("Features");
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// Emit as { "cpu", "description", f1 | f2 | ... fn },
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OS << " { "
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<< "\"" << Name << "\", "
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<< "\"Select the " << Name << " processor\", ";
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if (FeatureList.empty()) {
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OS << "0ULL";
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} else {
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for (unsigned j = 0, M = FeatureList.size(); j < M;) {
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OS << Target << "::" << FeatureList[j]->getName();
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if (++j < M) OS << " | ";
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}
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}
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// The "0" is for the "implies" section of this data structure.
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OS << ", 0ULL }";
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// Depending on 'if more in the list' emit comma
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if (++i < N) OS << ",";
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OS << "\n";
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}
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// End processor table
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OS << "};\n";
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return ProcessorList.size();
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}
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//
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// FormItineraryStageString - Compose a string containing the stage
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// data initialization for the specified itinerary. N is the number
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// of stages.
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//
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void SubtargetEmitter::FormItineraryStageString(const std::string &Name,
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Record *ItinData,
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std::string &ItinString,
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unsigned &NStages) {
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// Get states list
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const std::vector<Record*> &StageList =
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ItinData->getValueAsListOfDefs("Stages");
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// For each stage
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unsigned N = NStages = StageList.size();
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for (unsigned i = 0; i < N;) {
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// Next stage
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const Record *Stage = StageList[i];
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// Form string as ,{ cycles, u1 | u2 | ... | un, timeinc, kind }
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int Cycles = Stage->getValueAsInt("Cycles");
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ItinString += " { " + itostr(Cycles) + ", ";
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// Get unit list
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const std::vector<Record*> &UnitList = Stage->getValueAsListOfDefs("Units");
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// For each unit
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for (unsigned j = 0, M = UnitList.size(); j < M;) {
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// Add name and bitwise or
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ItinString += Name + "FU::" + UnitList[j]->getName();
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if (++j < M) ItinString += " | ";
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}
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int TimeInc = Stage->getValueAsInt("TimeInc");
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ItinString += ", " + itostr(TimeInc);
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int Kind = Stage->getValueAsInt("Kind");
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ItinString += ", (llvm::InstrStage::ReservationKinds)" + itostr(Kind);
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// Close off stage
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ItinString += " }";
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if (++i < N) ItinString += ", ";
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}
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}
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//
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// FormItineraryOperandCycleString - Compose a string containing the
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// operand cycle initialization for the specified itinerary. N is the
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// number of operands that has cycles specified.
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//
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void SubtargetEmitter::FormItineraryOperandCycleString(Record *ItinData,
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std::string &ItinString, unsigned &NOperandCycles) {
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// Get operand cycle list
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const std::vector<int64_t> &OperandCycleList =
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ItinData->getValueAsListOfInts("OperandCycles");
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// For each operand cycle
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unsigned N = NOperandCycles = OperandCycleList.size();
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for (unsigned i = 0; i < N;) {
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// Next operand cycle
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const int OCycle = OperandCycleList[i];
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ItinString += " " + itostr(OCycle);
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if (++i < N) ItinString += ", ";
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}
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}
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void SubtargetEmitter::FormItineraryBypassString(const std::string &Name,
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Record *ItinData,
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std::string &ItinString,
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unsigned NOperandCycles) {
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const std::vector<Record*> &BypassList =
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ItinData->getValueAsListOfDefs("Bypasses");
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unsigned N = BypassList.size();
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unsigned i = 0;
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for (; i < N;) {
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ItinString += Name + "Bypass::" + BypassList[i]->getName();
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if (++i < NOperandCycles) ItinString += ", ";
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}
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for (; i < NOperandCycles;) {
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ItinString += " 0";
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if (++i < NOperandCycles) ItinString += ", ";
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}
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}
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//
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// EmitStageAndOperandCycleData - Generate unique itinerary stages and operand
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// cycle tables. Create a list of InstrItinerary objects (ProcItinLists) indexed
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// by CodeGenSchedClass::Index.
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//
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void SubtargetEmitter::
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EmitStageAndOperandCycleData(raw_ostream &OS,
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std::vector<std::vector<InstrItinerary> >
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&ProcItinLists) {
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// Multiple processor models may share an itinerary record. Emit it once.
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SmallPtrSet<Record*, 8> ItinsDefSet;
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// Emit functional units for all the itineraries.
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for (CodeGenSchedModels::ProcIter PI = SchedModels.procModelBegin(),
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PE = SchedModels.procModelEnd(); PI != PE; ++PI) {
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if (!ItinsDefSet.insert(PI->ItinsDef))
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continue;
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std::vector<Record*> FUs = PI->ItinsDef->getValueAsListOfDefs("FU");
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if (FUs.empty())
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continue;
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const std::string &Name = PI->ItinsDef->getName();
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OS << "\n// Functional units for \"" << Name << "\"\n"
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<< "namespace " << Name << "FU {\n";
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for (unsigned j = 0, FUN = FUs.size(); j < FUN; ++j)
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OS << " const unsigned " << FUs[j]->getName()
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<< " = 1 << " << j << ";\n";
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OS << "}\n";
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std::vector<Record*> BPs = PI->ItinsDef->getValueAsListOfDefs("BP");
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if (BPs.size()) {
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OS << "\n// Pipeline forwarding pathes for itineraries \"" << Name
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<< "\"\n" << "namespace " << Name << "Bypass {\n";
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OS << " const unsigned NoBypass = 0;\n";
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for (unsigned j = 0, BPN = BPs.size(); j < BPN; ++j)
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OS << " const unsigned " << BPs[j]->getName()
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<< " = 1 << " << j << ";\n";
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OS << "}\n";
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}
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}
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// Begin stages table
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std::string StageTable = "\nextern const llvm::InstrStage " + Target +
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"Stages[] = {\n";
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StageTable += " { 0, 0, 0, llvm::InstrStage::Required }, // No itinerary\n";
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// Begin operand cycle table
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std::string OperandCycleTable = "extern const unsigned " + Target +
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"OperandCycles[] = {\n";
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OperandCycleTable += " 0, // No itinerary\n";
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// Begin pipeline bypass table
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std::string BypassTable = "extern const unsigned " + Target +
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"ForwardingPaths[] = {\n";
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BypassTable += " 0, // No itinerary\n";
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// For each Itinerary across all processors, add a unique entry to the stages,
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// operand cycles, and pipepine bypess tables. Then add the new Itinerary
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// object with computed offsets to the ProcItinLists result.
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unsigned StageCount = 1, OperandCycleCount = 1;
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std::map<std::string, unsigned> ItinStageMap, ItinOperandMap;
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for (CodeGenSchedModels::ProcIter PI = SchedModels.procModelBegin(),
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PE = SchedModels.procModelEnd(); PI != PE; ++PI) {
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const CodeGenProcModel &ProcModel = *PI;
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// Add process itinerary to the list.
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ProcItinLists.resize(ProcItinLists.size()+1);
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// If this processor defines no itineraries, then leave the itinerary list
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// empty.
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std::vector<InstrItinerary> &ItinList = ProcItinLists.back();
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if (ProcModel.ItinDefList.empty())
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continue;
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// Reserve index==0 for NoItinerary.
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ItinList.resize(SchedModels.numItineraryClasses()+1);
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const std::string &Name = ProcModel.ItinsDef->getName();
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// For each itinerary data
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for (unsigned SchedClassIdx = 0,
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SchedClassEnd = ProcModel.ItinDefList.size();
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SchedClassIdx < SchedClassEnd; ++SchedClassIdx) {
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// Next itinerary data
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Record *ItinData = ProcModel.ItinDefList[SchedClassIdx];
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// Get string and stage count
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std::string ItinStageString;
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unsigned NStages = 0;
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if (ItinData)
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FormItineraryStageString(Name, ItinData, ItinStageString, NStages);
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// Get string and operand cycle count
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std::string ItinOperandCycleString;
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unsigned NOperandCycles = 0;
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std::string ItinBypassString;
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if (ItinData) {
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FormItineraryOperandCycleString(ItinData, ItinOperandCycleString,
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NOperandCycles);
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FormItineraryBypassString(Name, ItinData, ItinBypassString,
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NOperandCycles);
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}
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// Check to see if stage already exists and create if it doesn't
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unsigned FindStage = 0;
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if (NStages > 0) {
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FindStage = ItinStageMap[ItinStageString];
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if (FindStage == 0) {
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// Emit as { cycles, u1 | u2 | ... | un, timeinc }, // indices
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StageTable += ItinStageString + ", // " + itostr(StageCount);
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if (NStages > 1)
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StageTable += "-" + itostr(StageCount + NStages - 1);
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StageTable += "\n";
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// Record Itin class number.
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ItinStageMap[ItinStageString] = FindStage = StageCount;
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StageCount += NStages;
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}
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}
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// Check to see if operand cycle already exists and create if it doesn't
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unsigned FindOperandCycle = 0;
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if (NOperandCycles > 0) {
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std::string ItinOperandString = ItinOperandCycleString+ItinBypassString;
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FindOperandCycle = ItinOperandMap[ItinOperandString];
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if (FindOperandCycle == 0) {
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// Emit as cycle, // index
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OperandCycleTable += ItinOperandCycleString + ", // ";
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std::string OperandIdxComment = itostr(OperandCycleCount);
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if (NOperandCycles > 1)
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OperandIdxComment += "-"
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+ itostr(OperandCycleCount + NOperandCycles - 1);
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OperandCycleTable += OperandIdxComment + "\n";
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// Record Itin class number.
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ItinOperandMap[ItinOperandCycleString] =
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FindOperandCycle = OperandCycleCount;
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// Emit as bypass, // index
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BypassTable += ItinBypassString + ", // " + OperandIdxComment + "\n";
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OperandCycleCount += NOperandCycles;
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}
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}
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// Set up itinerary as location and location + stage count
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int NumUOps = ItinData ? ItinData->getValueAsInt("NumMicroOps") : 0;
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InstrItinerary Intinerary = { NumUOps, FindStage, FindStage + NStages,
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FindOperandCycle,
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FindOperandCycle + NOperandCycles};
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// Inject - empty slots will be 0, 0
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ItinList[SchedClassIdx] = Intinerary;
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}
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}
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// Closing stage
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StageTable += " { 0, 0, 0, llvm::InstrStage::Required } // End stages\n";
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StageTable += "};\n";
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// Closing operand cycles
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OperandCycleTable += " 0 // End operand cycles\n";
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OperandCycleTable += "};\n";
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BypassTable += " 0 // End bypass tables\n";
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BypassTable += "};\n";
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// Emit tables.
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OS << StageTable;
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OS << OperandCycleTable;
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OS << BypassTable;
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}
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//
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// EmitProcessorData - Generate data for processor itineraries that were
|
|
// computed during EmitStageAndOperandCycleData(). ProcItinLists lists all
|
|
// Itineraries for each processor. The Itinerary lists are indexed on
|
|
// CodeGenSchedClass::Index.
|
|
//
|
|
void SubtargetEmitter::
|
|
EmitItineraries(raw_ostream &OS,
|
|
std::vector<std::vector<InstrItinerary> > &ProcItinLists) {
|
|
|
|
// Multiple processor models may share an itinerary record. Emit it once.
|
|
SmallPtrSet<Record*, 8> ItinsDefSet;
|
|
|
|
// For each processor's machine model
|
|
std::vector<std::vector<InstrItinerary> >::iterator
|
|
ProcItinListsIter = ProcItinLists.begin();
|
|
for (CodeGenSchedModels::ProcIter PI = SchedModels.procModelBegin(),
|
|
PE = SchedModels.procModelEnd(); PI != PE; ++PI) {
|
|
|
|
Record *ItinsDef = PI->ItinsDef;
|
|
if (!ItinsDefSet.insert(ItinsDef))
|
|
continue;
|
|
|
|
// Get processor itinerary name
|
|
const std::string &Name = ItinsDef->getName();
|
|
|
|
// Get the itinerary list for the processor.
|
|
assert(ProcItinListsIter != ProcItinLists.end() && "bad iterator");
|
|
std::vector<InstrItinerary> &ItinList = *ProcItinListsIter++;
|
|
|
|
OS << "\n";
|
|
OS << "static const llvm::InstrItinerary ";
|
|
if (ItinList.empty()) {
|
|
OS << '*' << Name << " = 0;\n";
|
|
continue;
|
|
}
|
|
|
|
// Begin processor itinerary table
|
|
OS << Name << "[] = {\n";
|
|
|
|
// For each itinerary class in CodeGenSchedClass::Index order.
|
|
for (unsigned j = 0, M = ItinList.size(); j < M; ++j) {
|
|
InstrItinerary &Intinerary = ItinList[j];
|
|
|
|
// Emit Itinerary in the form of
|
|
// { firstStage, lastStage, firstCycle, lastCycle } // index
|
|
OS << " { " <<
|
|
Intinerary.NumMicroOps << ", " <<
|
|
Intinerary.FirstStage << ", " <<
|
|
Intinerary.LastStage << ", " <<
|
|
Intinerary.FirstOperandCycle << ", " <<
|
|
Intinerary.LastOperandCycle << " }" <<
|
|
", // " << j << " " << SchedModels.getSchedClass(j).Name << "\n";
|
|
}
|
|
// End processor itinerary table
|
|
OS << " { 0, ~0U, ~0U, ~0U, ~0U } // end marker\n";
|
|
OS << "};\n";
|
|
}
|
|
}
|
|
|
|
// Emit either the value defined in the TableGen Record, or the default
|
|
// value defined in the C++ header. The Record is null if the processor does not
|
|
// define a model.
|
|
void SubtargetEmitter::EmitProcessorProp(raw_ostream &OS, const Record *R,
|
|
const char *Name, char Separator) {
|
|
OS << " ";
|
|
int V = R ? R->getValueAsInt(Name) : -1;
|
|
if (V >= 0)
|
|
OS << V << Separator << " // " << Name;
|
|
else
|
|
OS << "MCSchedModel::Default" << Name << Separator;
|
|
OS << '\n';
|
|
}
|
|
|
|
void SubtargetEmitter::EmitProcessorModels(raw_ostream &OS) {
|
|
// For each processor model.
|
|
for (CodeGenSchedModels::ProcIter PI = SchedModels.procModelBegin(),
|
|
PE = SchedModels.procModelEnd(); PI != PE; ++PI) {
|
|
// Skip default
|
|
// Begin processor itinerary properties
|
|
OS << "\n";
|
|
OS << "static const llvm::MCSchedModel " << PI->ModelName << "(\n";
|
|
EmitProcessorProp(OS, PI->ModelDef, "IssueWidth", ',');
|
|
EmitProcessorProp(OS, PI->ModelDef, "MinLatency", ',');
|
|
EmitProcessorProp(OS, PI->ModelDef, "LoadLatency", ',');
|
|
EmitProcessorProp(OS, PI->ModelDef, "HighLatency", ',');
|
|
EmitProcessorProp(OS, PI->ModelDef, "MispredictPenalty", ',');
|
|
if (SchedModels.hasItineraryClasses())
|
|
OS << " " << PI->ItinsDef->getName();
|
|
else
|
|
OS << " 0";
|
|
OS << ");\n";
|
|
}
|
|
}
|
|
|
|
//
|
|
// EmitProcessorLookup - generate cpu name to itinerary lookup table.
|
|
//
|
|
void SubtargetEmitter::EmitProcessorLookup(raw_ostream &OS) {
|
|
// Gather and sort processor information
|
|
std::vector<Record*> ProcessorList =
|
|
Records.getAllDerivedDefinitions("Processor");
|
|
std::sort(ProcessorList.begin(), ProcessorList.end(), LessRecordFieldName());
|
|
|
|
// Begin processor table
|
|
OS << "\n";
|
|
OS << "// Sorted (by key) array of itineraries for CPU subtype.\n"
|
|
<< "extern const llvm::SubtargetInfoKV "
|
|
<< Target << "ProcSchedKV[] = {\n";
|
|
|
|
// For each processor
|
|
for (unsigned i = 0, N = ProcessorList.size(); i < N;) {
|
|
// Next processor
|
|
Record *Processor = ProcessorList[i];
|
|
|
|
const std::string &Name = Processor->getValueAsString("Name");
|
|
const std::string &ProcModelName =
|
|
SchedModels.getProcModel(Processor).ModelName;
|
|
|
|
// Emit as { "cpu", procinit },
|
|
OS << " { "
|
|
<< "\"" << Name << "\", "
|
|
<< "(void *)&" << ProcModelName;
|
|
|
|
OS << " }";
|
|
|
|
// Depending on ''if more in the list'' emit comma
|
|
if (++i < N) OS << ",";
|
|
|
|
OS << "\n";
|
|
}
|
|
|
|
// End processor table
|
|
OS << "};\n";
|
|
}
|
|
|
|
//
|
|
// EmitSchedModel - Emits all scheduling model tables, folding common patterns.
|
|
//
|
|
void SubtargetEmitter::EmitSchedModel(raw_ostream &OS) {
|
|
if (SchedModels.hasItineraryClasses()) {
|
|
std::vector<std::vector<InstrItinerary> > ProcItinLists;
|
|
// Emit the stage data
|
|
EmitStageAndOperandCycleData(OS, ProcItinLists);
|
|
EmitItineraries(OS, ProcItinLists);
|
|
}
|
|
// Emit the processor machine model
|
|
EmitProcessorModels(OS);
|
|
// Emit the processor lookup data
|
|
EmitProcessorLookup(OS);
|
|
}
|
|
|
|
//
|
|
// ParseFeaturesFunction - Produces a subtarget specific function for parsing
|
|
// the subtarget features string.
|
|
//
|
|
void SubtargetEmitter::ParseFeaturesFunction(raw_ostream &OS,
|
|
unsigned NumFeatures,
|
|
unsigned NumProcs) {
|
|
std::vector<Record*> Features =
|
|
Records.getAllDerivedDefinitions("SubtargetFeature");
|
|
std::sort(Features.begin(), Features.end(), LessRecord());
|
|
|
|
OS << "// ParseSubtargetFeatures - Parses features string setting specified\n"
|
|
<< "// subtarget options.\n"
|
|
<< "void llvm::";
|
|
OS << Target;
|
|
OS << "Subtarget::ParseSubtargetFeatures(StringRef CPU, StringRef FS) {\n"
|
|
<< " DEBUG(dbgs() << \"\\nFeatures:\" << FS);\n"
|
|
<< " DEBUG(dbgs() << \"\\nCPU:\" << CPU << \"\\n\\n\");\n";
|
|
|
|
if (Features.empty()) {
|
|
OS << "}\n";
|
|
return;
|
|
}
|
|
|
|
OS << " uint64_t Bits = ReInitMCSubtargetInfo(CPU, FS);\n";
|
|
|
|
for (unsigned i = 0; i < Features.size(); i++) {
|
|
// Next record
|
|
Record *R = Features[i];
|
|
const std::string &Instance = R->getName();
|
|
const std::string &Value = R->getValueAsString("Value");
|
|
const std::string &Attribute = R->getValueAsString("Attribute");
|
|
|
|
if (Value=="true" || Value=="false")
|
|
OS << " if ((Bits & " << Target << "::"
|
|
<< Instance << ") != 0) "
|
|
<< Attribute << " = " << Value << ";\n";
|
|
else
|
|
OS << " if ((Bits & " << Target << "::"
|
|
<< Instance << ") != 0 && "
|
|
<< Attribute << " < " << Value << ") "
|
|
<< Attribute << " = " << Value << ";\n";
|
|
}
|
|
|
|
OS << "}\n";
|
|
}
|
|
|
|
//
|
|
// SubtargetEmitter::run - Main subtarget enumeration emitter.
|
|
//
|
|
void SubtargetEmitter::run(raw_ostream &OS) {
|
|
emitSourceFileHeader("Subtarget Enumeration Source Fragment", OS);
|
|
|
|
OS << "\n#ifdef GET_SUBTARGETINFO_ENUM\n";
|
|
OS << "#undef GET_SUBTARGETINFO_ENUM\n";
|
|
|
|
OS << "namespace llvm {\n";
|
|
Enumeration(OS, "SubtargetFeature", true);
|
|
OS << "} // End llvm namespace \n";
|
|
OS << "#endif // GET_SUBTARGETINFO_ENUM\n\n";
|
|
|
|
OS << "\n#ifdef GET_SUBTARGETINFO_MC_DESC\n";
|
|
OS << "#undef GET_SUBTARGETINFO_MC_DESC\n";
|
|
|
|
OS << "namespace llvm {\n";
|
|
#if 0
|
|
OS << "namespace {\n";
|
|
#endif
|
|
unsigned NumFeatures = FeatureKeyValues(OS);
|
|
OS << "\n";
|
|
unsigned NumProcs = CPUKeyValues(OS);
|
|
OS << "\n";
|
|
EmitSchedModel(OS);
|
|
OS << "\n";
|
|
#if 0
|
|
OS << "}\n";
|
|
#endif
|
|
|
|
// MCInstrInfo initialization routine.
|
|
OS << "static inline void Init" << Target
|
|
<< "MCSubtargetInfo(MCSubtargetInfo *II, "
|
|
<< "StringRef TT, StringRef CPU, StringRef FS) {\n";
|
|
OS << " II->InitMCSubtargetInfo(TT, CPU, FS, ";
|
|
if (NumFeatures)
|
|
OS << Target << "FeatureKV, ";
|
|
else
|
|
OS << "0, ";
|
|
if (NumProcs)
|
|
OS << Target << "SubTypeKV, ";
|
|
else
|
|
OS << "0, ";
|
|
if (SchedModels.hasItineraryClasses()) {
|
|
OS << Target << "ProcSchedKV, "
|
|
<< Target << "Stages, "
|
|
<< Target << "OperandCycles, "
|
|
<< Target << "ForwardingPaths, ";
|
|
} else
|
|
OS << "0, 0, 0, 0, ";
|
|
OS << NumFeatures << ", " << NumProcs << ");\n}\n\n";
|
|
|
|
OS << "} // End llvm namespace \n";
|
|
|
|
OS << "#endif // GET_SUBTARGETINFO_MC_DESC\n\n";
|
|
|
|
OS << "\n#ifdef GET_SUBTARGETINFO_TARGET_DESC\n";
|
|
OS << "#undef GET_SUBTARGETINFO_TARGET_DESC\n";
|
|
|
|
OS << "#include \"llvm/Support/Debug.h\"\n";
|
|
OS << "#include \"llvm/Support/raw_ostream.h\"\n";
|
|
ParseFeaturesFunction(OS, NumFeatures, NumProcs);
|
|
|
|
OS << "#endif // GET_SUBTARGETINFO_TARGET_DESC\n\n";
|
|
|
|
// Create a TargetSubtargetInfo subclass to hide the MC layer initialization.
|
|
OS << "\n#ifdef GET_SUBTARGETINFO_HEADER\n";
|
|
OS << "#undef GET_SUBTARGETINFO_HEADER\n";
|
|
|
|
std::string ClassName = Target + "GenSubtargetInfo";
|
|
OS << "namespace llvm {\n";
|
|
OS << "class DFAPacketizer;\n";
|
|
OS << "struct " << ClassName << " : public TargetSubtargetInfo {\n"
|
|
<< " explicit " << ClassName << "(StringRef TT, StringRef CPU, "
|
|
<< "StringRef FS);\n"
|
|
<< "public:\n"
|
|
<< " DFAPacketizer *createDFAPacketizer(const InstrItineraryData *IID)"
|
|
<< " const;\n"
|
|
<< "};\n";
|
|
OS << "} // End llvm namespace \n";
|
|
|
|
OS << "#endif // GET_SUBTARGETINFO_HEADER\n\n";
|
|
|
|
OS << "\n#ifdef GET_SUBTARGETINFO_CTOR\n";
|
|
OS << "#undef GET_SUBTARGETINFO_CTOR\n";
|
|
|
|
OS << "namespace llvm {\n";
|
|
OS << "extern const llvm::SubtargetFeatureKV " << Target << "FeatureKV[];\n";
|
|
OS << "extern const llvm::SubtargetFeatureKV " << Target << "SubTypeKV[];\n";
|
|
if (SchedModels.hasItineraryClasses()) {
|
|
OS << "extern const llvm::SubtargetInfoKV " << Target << "ProcSchedKV[];\n";
|
|
OS << "extern const llvm::InstrStage " << Target << "Stages[];\n";
|
|
OS << "extern const unsigned " << Target << "OperandCycles[];\n";
|
|
OS << "extern const unsigned " << Target << "ForwardingPaths[];\n";
|
|
}
|
|
|
|
OS << ClassName << "::" << ClassName << "(StringRef TT, StringRef CPU, "
|
|
<< "StringRef FS)\n"
|
|
<< " : TargetSubtargetInfo() {\n"
|
|
<< " InitMCSubtargetInfo(TT, CPU, FS, ";
|
|
if (NumFeatures)
|
|
OS << Target << "FeatureKV, ";
|
|
else
|
|
OS << "0, ";
|
|
if (NumProcs)
|
|
OS << Target << "SubTypeKV, ";
|
|
else
|
|
OS << "0, ";
|
|
if (SchedModels.hasItineraryClasses()) {
|
|
OS << Target << "ProcSchedKV, "
|
|
<< Target << "Stages, "
|
|
<< Target << "OperandCycles, "
|
|
<< Target << "ForwardingPaths, ";
|
|
} else
|
|
OS << "0, 0, 0, 0, ";
|
|
OS << NumFeatures << ", " << NumProcs << ");\n}\n\n";
|
|
OS << "} // End llvm namespace \n";
|
|
|
|
OS << "#endif // GET_SUBTARGETINFO_CTOR\n\n";
|
|
}
|
|
|
|
namespace llvm {
|
|
|
|
void EmitSubtarget(RecordKeeper &RK, raw_ostream &OS) {
|
|
CodeGenTarget CGTarget(RK);
|
|
SubtargetEmitter(RK, CGTarget).run(OS);
|
|
}
|
|
|
|
} // End llvm namespace
|