806 lines
24 KiB
C
806 lines
24 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2020 Advanced Micro Devices, Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* Contact Information :
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* Rajesh Kumar <rajesh1.kumar@amd.com>
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* Shreyank Amartya <Shreyank.Amartya@amd.com>
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*
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*/
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#include <sys/cdefs.h>
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#include "xgbe.h"
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#include "xgbe-common.h"
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/*
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* IFLIB interfaces
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*/
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static int axgbe_isc_txd_encap(void *, if_pkt_info_t);
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static void axgbe_isc_txd_flush(void *, uint16_t, qidx_t);
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static int axgbe_isc_txd_credits_update(void *, uint16_t, bool);
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static void axgbe_isc_rxd_refill(void *, if_rxd_update_t);
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static void axgbe_isc_rxd_flush(void *, uint16_t, uint8_t, qidx_t);
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static int axgbe_isc_rxd_available(void *, uint16_t, qidx_t, qidx_t);
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static int axgbe_isc_rxd_pkt_get(void *, if_rxd_info_t);
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struct if_txrx axgbe_txrx = {
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.ift_txd_encap = axgbe_isc_txd_encap,
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.ift_txd_flush = axgbe_isc_txd_flush,
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.ift_txd_credits_update = axgbe_isc_txd_credits_update,
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.ift_rxd_available = axgbe_isc_rxd_available,
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.ift_rxd_pkt_get = axgbe_isc_rxd_pkt_get,
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.ift_rxd_refill = axgbe_isc_rxd_refill,
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.ift_rxd_flush = axgbe_isc_rxd_flush,
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.ift_legacy_intr = NULL
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};
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static void
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xgbe_print_pkt_info(struct xgbe_prv_data *pdata, if_pkt_info_t pi)
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{
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axgbe_printf(1, "------Packet Info Start------\n");
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axgbe_printf(1, "pi len: %d qsidx: %d nsegs: %d ndescs: %d flags: %x pidx: %d\n",
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pi->ipi_len, pi->ipi_qsidx, pi->ipi_nsegs, pi->ipi_ndescs, pi->ipi_flags, pi->ipi_pidx);
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axgbe_printf(1, "pi new_pidx: %d csum_flags: %x mflags: %x vtag: %d\n",
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pi->ipi_new_pidx, pi->ipi_csum_flags, pi->ipi_mflags, pi->ipi_vtag);
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axgbe_printf(1, "pi etype: %d ehdrlen: %d ip_hlen: %d ipproto: %d\n",
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pi->ipi_etype, pi->ipi_ehdrlen, pi->ipi_ip_hlen, pi->ipi_ipproto);
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axgbe_printf(1, "pi tcp_hlen: %d tcp_hflags: %x tcp_seq: %d tso_segsz %d\n",
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pi->ipi_tcp_hlen, pi->ipi_tcp_hflags, pi->ipi_tcp_seq, pi->ipi_tso_segsz);
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}
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static bool
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axgbe_ctx_desc_setup(struct xgbe_prv_data *pdata, struct xgbe_ring *ring,
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if_pkt_info_t pi)
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{
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struct xgbe_ring_desc *rdesc;
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struct xgbe_ring_data *rdata;
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bool inc_cur = false;
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rdata = XGBE_GET_DESC_DATA(ring, ring->cur);
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rdesc = rdata->rdesc;
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axgbe_printf(1, "ipi_tso_segsz %d cur_mss %d idx %d\n",
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pi->ipi_tso_segsz, ring->tx.cur_mss, ring->cur);
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axgbe_printf(1, "ipi_vtag 0x%x cur_vlan_ctag 0x%x\n",
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pi->ipi_vtag, ring->tx.cur_vlan_ctag);
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if ((pi->ipi_csum_flags & CSUM_TSO) &&
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(pi->ipi_tso_segsz != ring->tx.cur_mss)) {
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/*
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* Set TSO maximum segment size
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* Mark as context descriptor
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* Indicate this descriptor contains MSS
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*/
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XGMAC_SET_BITS_LE(rdesc->desc2, TX_CONTEXT_DESC2,
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MSS, pi->ipi_tso_segsz);
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XGMAC_SET_BITS_LE(rdesc->desc3, TX_CONTEXT_DESC3, CTXT, 1);
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XGMAC_SET_BITS_LE(rdesc->desc3, TX_CONTEXT_DESC3, TCMSSV, 1);
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ring->tx.cur_mss = pi->ipi_tso_segsz;
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inc_cur = true;
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}
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if (pi->ipi_vtag && (pi->ipi_vtag != ring->tx.cur_vlan_ctag)) {
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/*
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* Mark it as context descriptor
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* Set the VLAN tag
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* Indicate this descriptor contains the VLAN tag
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*/
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XGMAC_SET_BITS_LE(rdesc->desc3, TX_CONTEXT_DESC3, CTXT, 1);
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XGMAC_SET_BITS_LE(rdesc->desc3, TX_CONTEXT_DESC3,
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VT, pi->ipi_vtag);
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XGMAC_SET_BITS_LE(rdesc->desc3, TX_CONTEXT_DESC3, VLTV, 1);
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ring->tx.cur_vlan_ctag = pi->ipi_vtag;
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inc_cur = true;
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}
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return (inc_cur);
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}
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static uint16_t
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axgbe_calculate_tx_parms(struct xgbe_prv_data *pdata, if_pkt_info_t pi,
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struct xgbe_packet_data *packet)
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{
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uint32_t tcp_payload_len = 0, bytes = 0;
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uint16_t max_len, hlen, payload_len, pkts = 0;
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packet->tx_packets = packet->tx_bytes = 0;
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hlen = pi->ipi_ehdrlen + pi->ipi_ip_hlen + pi->ipi_tcp_hlen;
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if (pi->ipi_csum_flags & CSUM_TSO) {
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tcp_payload_len = pi->ipi_len - hlen;
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axgbe_printf(1, "%s: ipi_len %x elen %d iplen %d tcplen %d\n",
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__func__, pi->ipi_len, pi->ipi_ehdrlen, pi->ipi_ip_hlen,
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pi->ipi_tcp_hlen);
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max_len = if_getmtu(pdata->netdev) + ETH_HLEN;
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if (pi->ipi_vtag)
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max_len += VLAN_HLEN;
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while (tcp_payload_len) {
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payload_len = max_len - hlen;
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payload_len = min(payload_len, tcp_payload_len);
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tcp_payload_len -= payload_len;
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pkts++;
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bytes += (hlen + payload_len);
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axgbe_printf(1, "%s: max_len %d payload_len %d "
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"tcp_len %d\n", __func__, max_len, payload_len,
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tcp_payload_len);
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}
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} else {
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pkts = 1;
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bytes = pi->ipi_len;
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}
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packet->tx_packets = pkts;
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packet->tx_bytes = bytes;
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axgbe_printf(1, "%s: packets %d bytes %d hlen %d\n", __func__,
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packet->tx_packets, packet->tx_bytes, hlen);
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return (hlen);
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}
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static int
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axgbe_isc_txd_encap(void *arg, if_pkt_info_t pi)
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{
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struct axgbe_if_softc *sc = (struct axgbe_if_softc*)arg;
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struct xgbe_prv_data *pdata = &sc->pdata;
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struct xgbe_channel *channel;
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struct xgbe_ring *ring;
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struct xgbe_ring_desc *rdesc;
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struct xgbe_ring_data *rdata;
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struct xgbe_packet_data *packet;
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unsigned int cur, start, tx_set_ic;
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uint16_t offset, hlen, datalen, tcp_payload_len = 0;
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int cur_seg = 0;
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xgbe_print_pkt_info(pdata, pi);
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channel = pdata->channel[pi->ipi_qsidx];
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ring = channel->tx_ring;
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packet = &ring->packet_data;
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cur = start = ring->cur;
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axgbe_printf(1, "--> %s: txq %d cur %d dirty %d\n",
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__func__, pi->ipi_qsidx, ring->cur, ring->dirty);
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MPASS(pi->ipi_len != 0);
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if (__predict_false(pi->ipi_len == 0)) {
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axgbe_error("empty packet received from stack\n");
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return (0);
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}
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MPASS(ring->cur == pi->ipi_pidx);
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if (__predict_false(ring->cur != pi->ipi_pidx)) {
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axgbe_error("--> %s: cur(%d) ne pidx(%d)\n", __func__,
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ring->cur, pi->ipi_pidx);
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}
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/* Determine if an interrupt should be generated for this Tx:
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* Interrupt:
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* - Tx frame count exceeds the frame count setting
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* - Addition of Tx frame count to the frame count since the
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* last interrupt was set exceeds the frame count setting
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* No interrupt:
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* - No frame count setting specified (ethtool -C ethX tx-frames 0)
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* - Addition of Tx frame count to the frame count since the
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* last interrupt was set does not exceed the frame count setting
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*/
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memset(packet, 0, sizeof(*packet));
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hlen = axgbe_calculate_tx_parms(pdata, pi, packet);
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axgbe_printf(1, "%s: ipi_len %d tx_pkts %d tx_bytes %d hlen %d\n",
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__func__, pi->ipi_len, packet->tx_packets, packet->tx_bytes, hlen);
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ring->coalesce_count += packet->tx_packets;
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if (!pdata->tx_frames)
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tx_set_ic = 0;
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else if (packet->tx_packets > pdata->tx_frames)
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tx_set_ic = 1;
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else if ((ring->coalesce_count % pdata->tx_frames) < (packet->tx_packets))
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tx_set_ic = 1;
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else
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tx_set_ic = 0;
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/* Add Context descriptor if needed (for TSO, VLAN cases) */
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if (axgbe_ctx_desc_setup(pdata, ring, pi))
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cur++;
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rdata = XGBE_GET_DESC_DATA(ring, cur);
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rdesc = rdata->rdesc;
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axgbe_printf(1, "%s: cur %d lo 0x%lx hi 0x%lx ds_len 0x%x "
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"ipi_len 0x%x\n", __func__, cur,
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lower_32_bits(pi->ipi_segs[cur_seg].ds_addr),
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upper_32_bits(pi->ipi_segs[cur_seg].ds_addr),
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(int)pi->ipi_segs[cur_seg].ds_len, pi->ipi_len);
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/* Update buffer address (for TSO this is the header) */
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rdesc->desc0 = cpu_to_le32(lower_32_bits(pi->ipi_segs[cur_seg].ds_addr));
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rdesc->desc1 = cpu_to_le32(upper_32_bits(pi->ipi_segs[cur_seg].ds_addr));
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/* Update the buffer length */
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if (hlen == 0)
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hlen = pi->ipi_segs[cur_seg].ds_len;
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XGMAC_SET_BITS_LE(rdesc->desc2, TX_NORMAL_DESC2, HL_B1L, hlen);
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/* VLAN tag insertion check */
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if (pi->ipi_vtag) {
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XGMAC_SET_BITS_LE(rdesc->desc2, TX_NORMAL_DESC2, VTIR,
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TX_NORMAL_DESC2_VLAN_INSERT);
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}
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/* Mark it as First Descriptor */
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XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, FD, 1);
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/* Mark it as a NORMAL descriptor */
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XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, CTXT, 0);
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/*
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* Set the OWN bit if this is not the first descriptor. For first
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* descriptor, OWN bit will be set at last so that hardware will
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* process the descriptors only after the OWN bit for the first
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* descriptor is set
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*/
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if (cur != start)
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XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, OWN, 1);
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if (pi->ipi_csum_flags & CSUM_TSO) {
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/* Enable TSO */
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XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, TSE, 1);
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tcp_payload_len = pi->ipi_len - hlen;
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/* Set TCP payload length*/
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XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, TCPPL,
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tcp_payload_len);
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XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, TCPHDRLEN,
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pi->ipi_tcp_hlen/4);
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axgbe_printf(1, "tcp_payload %d tcp_hlen %d\n", tcp_payload_len,
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pi->ipi_tcp_hlen/4);
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} else {
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/* Enable CRC and Pad Insertion */
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XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, CPC, 0);
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/* Enable HW CSUM*/
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if (pi->ipi_csum_flags)
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XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, CIC, 0x3);
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/* Set total length to be transmitted */
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XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, FL, pi->ipi_len);
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}
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cur++;
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for (cur_seg = 0 ; cur_seg < pi->ipi_nsegs ; cur_seg++) {
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if (cur_seg == 0) {
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offset = hlen;
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datalen = pi->ipi_segs[cur_seg].ds_len - hlen;
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} else {
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offset = 0;
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datalen = pi->ipi_segs[cur_seg].ds_len;
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}
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if (datalen) {
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rdata = XGBE_GET_DESC_DATA(ring, cur);
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rdesc = rdata->rdesc;
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/* Update buffer address */
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rdesc->desc0 =
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cpu_to_le32(lower_32_bits(pi->ipi_segs[cur_seg].ds_addr + offset));
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rdesc->desc1 =
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cpu_to_le32(upper_32_bits(pi->ipi_segs[cur_seg].ds_addr + offset));
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/* Update the buffer length */
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XGMAC_SET_BITS_LE(rdesc->desc2, TX_NORMAL_DESC2, HL_B1L, datalen);
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/* Set OWN bit */
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XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, OWN, 1);
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/* Mark it as NORMAL descriptor */
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XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, CTXT, 0);
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/* Enable HW CSUM*/
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if (pi->ipi_csum_flags)
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XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, CIC, 0x3);
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axgbe_printf(1, "%s: cur %d lo 0x%lx hi 0x%lx ds_len 0x%x "
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"ipi_len 0x%x\n", __func__, cur,
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lower_32_bits(pi->ipi_segs[cur_seg].ds_addr),
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upper_32_bits(pi->ipi_segs[cur_seg].ds_addr),
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(int)pi->ipi_segs[cur_seg].ds_len, pi->ipi_len);
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cur++;
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}
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}
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/* Set LAST bit for the last descriptor */
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XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, LD, 1);
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/* Set IC bit based on Tx coalescing settings */
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if (tx_set_ic)
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XGMAC_SET_BITS_LE(rdesc->desc2, TX_NORMAL_DESC2, IC, 1);
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wmb();
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/* Set OWN bit for the first descriptor */
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rdata = XGBE_GET_DESC_DATA(ring, start);
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rdesc = rdata->rdesc;
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XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, OWN, 1);
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ring->cur = pi->ipi_new_pidx = (cur & (ring->rdesc_count - 1));
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axgbe_printf(1, "<-- %s: end cur %d dirty %d\n", __func__, ring->cur,
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ring->dirty);
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return (0);
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}
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static void
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axgbe_isc_txd_flush(void *arg, uint16_t txqid, qidx_t pidx)
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{
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struct axgbe_if_softc *sc = (struct axgbe_if_softc*)arg;
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struct xgbe_prv_data *pdata = &sc->pdata;
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struct xgbe_channel *channel = pdata->channel[txqid];
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struct xgbe_ring *ring = channel->tx_ring;
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struct xgbe_ring_data *rdata = XGBE_GET_DESC_DATA(ring, pidx);
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axgbe_printf(1, "--> %s: flush txq %d pidx %d cur %d dirty %d\n",
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__func__, txqid, pidx, ring->cur, ring->dirty);
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/* Ring Doorbell */
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XGMAC_DMA_IOWRITE(channel, DMA_CH_TDTR_LO,
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lower_32_bits(rdata->rdata_paddr));
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}
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static int
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axgbe_isc_txd_credits_update(void *arg, uint16_t txqid, bool clear)
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{
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struct axgbe_if_softc *sc = (struct axgbe_if_softc*)arg;
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struct xgbe_hw_if *hw_if = &sc->pdata.hw_if;
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struct xgbe_prv_data *pdata = &sc->pdata;
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struct xgbe_channel *channel = pdata->channel[txqid];
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struct xgbe_ring *ring = channel->tx_ring;
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struct xgbe_ring_data *rdata;
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int processed = 0;
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axgbe_printf(1, "%s: txq %d clear %d cur %d dirty %d\n",
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__func__, txqid, clear, ring->cur, ring->dirty);
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if (__predict_false(ring->cur == ring->dirty)) {
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axgbe_printf(1, "<-- %s: cur(%d) equals dirty(%d)\n",
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__func__, ring->cur, ring->dirty);
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return (0);
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}
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/* Check whether the first dirty descriptor is Tx complete */
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rdata = XGBE_GET_DESC_DATA(ring, ring->dirty);
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if (!hw_if->tx_complete(rdata->rdesc)) {
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axgbe_printf(1, "<-- %s: (dirty %d)\n", __func__, ring->dirty);
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return (0);
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}
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/*
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* If clear is false just let the caller know that there
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* are descriptors to reclaim
|
|
*/
|
|
if (!clear) {
|
|
axgbe_printf(1, "<-- %s: (!clear)\n", __func__);
|
|
return (1);
|
|
}
|
|
|
|
do {
|
|
hw_if->tx_desc_reset(rdata);
|
|
processed++;
|
|
ring->dirty = (ring->dirty + 1) & (ring->rdesc_count - 1);
|
|
|
|
/*
|
|
* tx_complete will return true for unused descriptors also.
|
|
* so, check tx_complete only until used descriptors.
|
|
*/
|
|
if (ring->cur == ring->dirty)
|
|
break;
|
|
|
|
rdata = XGBE_GET_DESC_DATA(ring, ring->dirty);
|
|
} while (hw_if->tx_complete(rdata->rdesc));
|
|
|
|
axgbe_printf(1, "<-- %s: processed %d cur %d dirty %d\n", __func__,
|
|
processed, ring->cur, ring->dirty);
|
|
|
|
return (processed);
|
|
}
|
|
|
|
static void
|
|
axgbe_isc_rxd_refill(void *arg, if_rxd_update_t iru)
|
|
{
|
|
struct axgbe_if_softc *sc = (struct axgbe_if_softc*)arg;
|
|
struct xgbe_prv_data *pdata = &sc->pdata;
|
|
struct xgbe_channel *channel = pdata->channel[iru->iru_qsidx];
|
|
struct xgbe_ring *ring = channel->rx_ring;
|
|
struct xgbe_ring_data *rdata;
|
|
struct xgbe_ring_desc *rdesc;
|
|
unsigned int rx_usecs = pdata->rx_usecs;
|
|
unsigned int rx_frames = pdata->rx_frames;
|
|
unsigned int inte;
|
|
uint8_t count = iru->iru_count;
|
|
int i, j;
|
|
bool config_intr = false;
|
|
|
|
axgbe_printf(1, "--> %s: rxq %d fl %d pidx %d count %d ring cur %d "
|
|
"dirty %d\n", __func__, iru->iru_qsidx, iru->iru_flidx,
|
|
iru->iru_pidx, count, ring->cur, ring->dirty);
|
|
|
|
for (i = iru->iru_pidx, j = 0 ; j < count ; i++, j++) {
|
|
|
|
if (i == sc->scctx->isc_nrxd[0])
|
|
i = 0;
|
|
|
|
rdata = XGBE_GET_DESC_DATA(ring, i);
|
|
rdesc = rdata->rdesc;
|
|
|
|
if (__predict_false(XGMAC_GET_BITS_LE(rdesc->desc3,
|
|
RX_NORMAL_DESC3, OWN))) {
|
|
axgbe_error("%s: refill clash, cur %d dirty %d index %d"
|
|
"pidx %d\n", __func__, ring->cur, ring->dirty, j, i);
|
|
}
|
|
|
|
if (pdata->sph_enable) {
|
|
if (iru->iru_flidx == 0) {
|
|
|
|
/* Fill header/buffer1 address */
|
|
rdesc->desc0 =
|
|
cpu_to_le32(lower_32_bits(iru->iru_paddrs[j]));
|
|
rdesc->desc1 =
|
|
cpu_to_le32(upper_32_bits(iru->iru_paddrs[j]));
|
|
} else {
|
|
|
|
/* Fill data/buffer2 address */
|
|
rdesc->desc2 =
|
|
cpu_to_le32(lower_32_bits(iru->iru_paddrs[j]));
|
|
rdesc->desc3 =
|
|
cpu_to_le32(upper_32_bits(iru->iru_paddrs[j]));
|
|
|
|
config_intr = true;
|
|
}
|
|
} else {
|
|
/* Fill header/buffer1 address */
|
|
rdesc->desc0 = rdesc->desc2 =
|
|
cpu_to_le32(lower_32_bits(iru->iru_paddrs[j]));
|
|
rdesc->desc1 = rdesc->desc3 =
|
|
cpu_to_le32(upper_32_bits(iru->iru_paddrs[j]));
|
|
|
|
config_intr = true;
|
|
}
|
|
|
|
if (config_intr) {
|
|
|
|
if (!rx_usecs && !rx_frames) {
|
|
/* No coalescing, interrupt for every descriptor */
|
|
inte = 1;
|
|
} else {
|
|
/* Set interrupt based on Rx frame coalescing setting */
|
|
if (rx_frames && !((ring->dirty + 1) % rx_frames))
|
|
inte = 1;
|
|
else
|
|
inte = 0;
|
|
}
|
|
|
|
XGMAC_SET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, INTE, inte);
|
|
|
|
XGMAC_SET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, OWN, 1);
|
|
|
|
wmb();
|
|
|
|
ring->dirty = ((ring->dirty + 1) & (ring->rdesc_count - 1));
|
|
|
|
config_intr = false;
|
|
}
|
|
}
|
|
|
|
axgbe_printf(1, "<-- %s: rxq: %d cur: %d dirty: %d\n", __func__,
|
|
channel->queue_index, ring->cur, ring->dirty);
|
|
}
|
|
|
|
static void
|
|
axgbe_isc_rxd_flush(void *arg, uint16_t qsidx, uint8_t flidx, qidx_t pidx)
|
|
{
|
|
struct axgbe_if_softc *sc = (struct axgbe_if_softc*)arg;
|
|
struct xgbe_prv_data *pdata = &sc->pdata;
|
|
struct xgbe_channel *channel = pdata->channel[qsidx];
|
|
struct xgbe_ring *ring = channel->rx_ring;
|
|
struct xgbe_ring_data *rdata;
|
|
|
|
axgbe_printf(1, "--> %s: rxq %d fl %d pidx %d cur %d dirty %d\n",
|
|
__func__, qsidx, flidx, pidx, ring->cur, ring->dirty);
|
|
|
|
rdata = XGBE_GET_DESC_DATA(ring, pidx);
|
|
|
|
/*
|
|
* update RX descriptor tail pointer in hardware to indicate
|
|
* that new buffers are present in the allocated memory region
|
|
*/
|
|
if (!pdata->sph_enable || flidx == 1) {
|
|
XGMAC_DMA_IOWRITE(channel, DMA_CH_RDTR_LO,
|
|
lower_32_bits(rdata->rdata_paddr));
|
|
}
|
|
}
|
|
|
|
static int
|
|
axgbe_isc_rxd_available(void *arg, uint16_t qsidx, qidx_t idx, qidx_t budget)
|
|
{
|
|
struct axgbe_if_softc *sc = (struct axgbe_if_softc*)arg;
|
|
struct xgbe_prv_data *pdata = &sc->pdata;
|
|
struct xgbe_channel *channel = pdata->channel[qsidx];
|
|
struct xgbe_ring *ring = channel->rx_ring;
|
|
struct xgbe_ring_data *rdata;
|
|
struct xgbe_ring_desc *rdesc;
|
|
unsigned int cur;
|
|
int count = 0;
|
|
uint8_t incomplete = 1, context_next = 0, running = 0;
|
|
|
|
axgbe_printf(1, "--> %s: rxq %d idx %d budget %d cur %d dirty %d\n",
|
|
__func__, qsidx, idx, budget, ring->cur, ring->dirty);
|
|
|
|
if (__predict_false(test_bit(XGBE_DOWN, &pdata->dev_state))) {
|
|
axgbe_printf(0, "%s: Polling when XGBE_DOWN\n", __func__);
|
|
return (count);
|
|
}
|
|
|
|
cur = ring->cur;
|
|
for (count = 0; count <= budget; ) {
|
|
|
|
rdata = XGBE_GET_DESC_DATA(ring, cur);
|
|
rdesc = rdata->rdesc;
|
|
|
|
if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, OWN))
|
|
break;
|
|
|
|
running = 1;
|
|
|
|
if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, LD))
|
|
incomplete = 0;
|
|
|
|
if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, CDA))
|
|
context_next = 1;
|
|
|
|
if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, CTXT))
|
|
context_next = 0;
|
|
|
|
cur = (cur + 1) & (ring->rdesc_count - 1);
|
|
|
|
if (incomplete || context_next)
|
|
continue;
|
|
|
|
/* Increment pkt count & reset variables for next full packet */
|
|
count++;
|
|
incomplete = 1;
|
|
context_next = 0;
|
|
running = 0;
|
|
}
|
|
|
|
axgbe_printf(1, "--> %s: rxq %d cur %d incomp %d con_next %d running %d "
|
|
"count %d\n", __func__, qsidx, cur, incomplete, context_next,
|
|
running, count);
|
|
|
|
return (count);
|
|
}
|
|
|
|
static unsigned int
|
|
xgbe_rx_buf1_len(struct xgbe_prv_data *pdata, struct xgbe_ring_data *rdata,
|
|
struct xgbe_packet_data *packet)
|
|
{
|
|
unsigned int ret = 0;
|
|
|
|
if (pdata->sph_enable) {
|
|
/* Always zero if not the first descriptor */
|
|
if (!XGMAC_GET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, FIRST)) {
|
|
axgbe_printf(1, "%s: Not First\n", __func__);
|
|
return (0);
|
|
}
|
|
}
|
|
|
|
/* First descriptor with split header, return header length */
|
|
if (rdata->rx.hdr_len) {
|
|
axgbe_printf(1, "%s: hdr_len %d\n", __func__, rdata->rx.hdr_len);
|
|
return (rdata->rx.hdr_len);
|
|
}
|
|
|
|
/* First descriptor but not the last descriptor and no split header,
|
|
* so the full buffer was used, 256 represents the hardcoded value of
|
|
* a max header split defined in the hardware
|
|
*/
|
|
if (!XGMAC_GET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, LAST)) {
|
|
axgbe_printf(1, "%s: Not last %d\n", __func__,
|
|
pdata->rx_buf_size);
|
|
if (pdata->sph_enable) {
|
|
return (256);
|
|
} else {
|
|
return (pdata->rx_buf_size);
|
|
}
|
|
}
|
|
|
|
/* First descriptor and last descriptor and no split header, so
|
|
* calculate how much of the buffer was used, we can return the
|
|
* segment length or the remaining bytes of the packet
|
|
*/
|
|
axgbe_printf(1, "%s: pkt_len %d buf_size %d\n", __func__, rdata->rx.len,
|
|
pdata->rx_buf_size);
|
|
|
|
if (pdata->sph_enable) {
|
|
ret = min_t(unsigned int, 256, rdata->rx.len);
|
|
} else {
|
|
ret = rdata->rx.len;
|
|
}
|
|
|
|
return (ret);
|
|
}
|
|
|
|
static unsigned int
|
|
xgbe_rx_buf2_len(struct xgbe_prv_data *pdata, struct xgbe_ring_data *rdata,
|
|
struct xgbe_packet_data *packet, unsigned int len)
|
|
{
|
|
|
|
/* Always the full buffer if not the last descriptor */
|
|
if (!XGMAC_GET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, LAST)) {
|
|
axgbe_printf(1, "%s: Not last %d\n", __func__, pdata->rx_buf_size);
|
|
return (pdata->rx_buf_size);
|
|
}
|
|
|
|
/* Last descriptor so calculate how much of the buffer was used
|
|
* for the last bit of data
|
|
*/
|
|
return ((rdata->rx.len != 0)? (rdata->rx.len - len) : 0);
|
|
}
|
|
|
|
static inline void
|
|
axgbe_add_frag(struct xgbe_prv_data *pdata, if_rxd_info_t ri, int idx, int len,
|
|
int pos, int flid)
|
|
{
|
|
axgbe_printf(2, "idx %d len %d pos %d flid %d\n", idx, len, pos, flid);
|
|
ri->iri_frags[pos].irf_flid = flid;
|
|
ri->iri_frags[pos].irf_idx = idx;
|
|
ri->iri_frags[pos].irf_len = len;
|
|
}
|
|
|
|
static int
|
|
axgbe_isc_rxd_pkt_get(void *arg, if_rxd_info_t ri)
|
|
{
|
|
struct axgbe_if_softc *sc = (struct axgbe_if_softc*)arg;
|
|
struct xgbe_prv_data *pdata = &sc->pdata;
|
|
struct xgbe_hw_if *hw_if = &pdata->hw_if;
|
|
struct xgbe_channel *channel = pdata->channel[ri->iri_qsidx];
|
|
struct xgbe_ring *ring = channel->rx_ring;
|
|
struct xgbe_packet_data *packet = &ring->packet_data;
|
|
struct xgbe_ring_data *rdata;
|
|
unsigned int last, context_next, context;
|
|
unsigned int buf1_len, buf2_len, max_len, len = 0, prev_cur;
|
|
int i = 0;
|
|
|
|
axgbe_printf(2, "%s: rxq %d cidx %d cur %d dirty %d\n", __func__,
|
|
ri->iri_qsidx, ri->iri_cidx, ring->cur, ring->dirty);
|
|
|
|
memset(packet, 0, sizeof(struct xgbe_packet_data));
|
|
|
|
while (1) {
|
|
|
|
read_again:
|
|
if (hw_if->dev_read(channel)) {
|
|
axgbe_printf(2, "<-- %s: OWN bit seen on %d\n",
|
|
__func__, ring->cur);
|
|
break;
|
|
}
|
|
|
|
rdata = XGBE_GET_DESC_DATA(ring, ring->cur);
|
|
prev_cur = ring->cur;
|
|
ring->cur = (ring->cur + 1) & (ring->rdesc_count - 1);
|
|
|
|
last = XGMAC_GET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
|
|
LAST);
|
|
|
|
context_next = XGMAC_GET_BITS(packet->attributes,
|
|
RX_PACKET_ATTRIBUTES, CONTEXT_NEXT);
|
|
|
|
context = XGMAC_GET_BITS(packet->attributes,
|
|
RX_PACKET_ATTRIBUTES, CONTEXT);
|
|
|
|
if (!context) {
|
|
/* Get the data length in the descriptor buffers */
|
|
buf1_len = xgbe_rx_buf1_len(pdata, rdata, packet);
|
|
len += buf1_len;
|
|
if (pdata->sph_enable) {
|
|
buf2_len = xgbe_rx_buf2_len(pdata, rdata, packet, len);
|
|
len += buf2_len;
|
|
}
|
|
} else
|
|
buf1_len = buf2_len = 0;
|
|
|
|
if (packet->errors)
|
|
axgbe_printf(1, "%s: last %d context %d con_next %d buf1 %d "
|
|
"buf2 %d len %d frags %d error %d\n", __func__, last, context,
|
|
context_next, buf1_len, buf2_len, len, i, packet->errors);
|
|
|
|
axgbe_add_frag(pdata, ri, prev_cur, buf1_len, i, 0);
|
|
i++;
|
|
if (pdata->sph_enable) {
|
|
axgbe_add_frag(pdata, ri, prev_cur, buf2_len, i, 1);
|
|
i++;
|
|
}
|
|
|
|
if (!last || context_next)
|
|
goto read_again;
|
|
|
|
break;
|
|
}
|
|
|
|
if (XGMAC_GET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, CSUM_DONE)) {
|
|
ri->iri_csum_flags |= CSUM_IP_CHECKED;
|
|
ri->iri_csum_flags |= CSUM_IP_VALID;
|
|
axgbe_printf(2, "%s: csum flags 0x%x\n", __func__, ri->iri_csum_flags);
|
|
}
|
|
|
|
max_len = if_getmtu(pdata->netdev) + ETH_HLEN;
|
|
if (XGMAC_GET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, VLAN_CTAG)) {
|
|
ri->iri_flags |= M_VLANTAG;
|
|
ri->iri_vtag = packet->vlan_ctag;
|
|
max_len += VLAN_HLEN;
|
|
axgbe_printf(2, "%s: iri_flags 0x%x vtag 0x%x\n", __func__,
|
|
ri->iri_flags, ri->iri_vtag);
|
|
}
|
|
|
|
|
|
if (XGMAC_GET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, RSS_HASH)) {
|
|
ri->iri_flowid = packet->rss_hash;
|
|
ri->iri_rsstype = packet->rss_hash_type;
|
|
axgbe_printf(2, "%s: hash 0x%x/0x%x rsstype 0x%x/0x%x\n",
|
|
__func__, packet->rss_hash, ri->iri_flowid,
|
|
packet->rss_hash_type, ri->iri_rsstype);
|
|
}
|
|
|
|
if (__predict_false(len == 0))
|
|
axgbe_printf(1, "%s: Discarding Zero len packet\n", __func__);
|
|
|
|
if (__predict_false(len > max_len))
|
|
axgbe_error("%s: Big packet %d/%d\n", __func__, len, max_len);
|
|
|
|
if (__predict_false(packet->errors))
|
|
axgbe_printf(1, "<-- %s: rxq: %d len: %d frags: %d cidx %d cur: %d "
|
|
"dirty: %d error 0x%x\n", __func__, ri->iri_qsidx, len, i,
|
|
ri->iri_cidx, ring->cur, ring->dirty, packet->errors);
|
|
|
|
axgbe_printf(1, "%s: Packet len %d frags %d\n", __func__, len, i);
|
|
|
|
ri->iri_len = len;
|
|
ri->iri_nfrags = i;
|
|
|
|
return (0);
|
|
}
|