1013 lines
25 KiB
C
1013 lines
25 KiB
C
/*-
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* SPDX-License-Identifier: BSD-3-Clause
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*
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* Copyright (c) 2007, Juniper Networks, Inc.
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* Copyright (c) 2012-2013, SRI International
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* All rights reserved.
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*
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* Portions of this software were developed by SRI International and the
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* University of Cambridge Computer Laboratory under DARPA/AFRL contract
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* (FA8750-10-C-0237) ("CTSRD"), as part of the DARPA CRASH research
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* programme.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the author nor the names of any co-contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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#include "opt_cfi.h"
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/conf.h>
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#include <sys/endian.h>
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#include <sys/kenv.h>
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#include <sys/kernel.h>
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#include <sys/malloc.h>
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#include <sys/module.h>
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#include <sys/rman.h>
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#include <sys/sysctl.h>
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#include <machine/bus.h>
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#include <dev/cfi/cfi_reg.h>
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#include <dev/cfi/cfi_var.h>
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static void cfi_add_sysctls(struct cfi_softc *);
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extern struct cdevsw cfi_cdevsw;
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char cfi_driver_name[] = "cfi";
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uint32_t
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cfi_read_raw(struct cfi_softc *sc, u_int ofs)
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{
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uint32_t val;
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ofs &= ~(sc->sc_width - 1);
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switch (sc->sc_width) {
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case 1:
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val = bus_space_read_1(sc->sc_tag, sc->sc_handle, ofs);
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break;
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case 2:
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val = bus_space_read_2(sc->sc_tag, sc->sc_handle, ofs);
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break;
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case 4:
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val = bus_space_read_4(sc->sc_tag, sc->sc_handle, ofs);
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break;
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default:
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val = ~0;
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break;
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}
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return (val);
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}
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uint32_t
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cfi_read(struct cfi_softc *sc, u_int ofs)
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{
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uint32_t val;
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uint16_t sval;
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ofs &= ~(sc->sc_width - 1);
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switch (sc->sc_width) {
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case 1:
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val = bus_space_read_1(sc->sc_tag, sc->sc_handle, ofs);
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break;
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case 2:
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sval = bus_space_read_2(sc->sc_tag, sc->sc_handle, ofs);
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#ifdef CFI_HARDWAREBYTESWAP
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val = sval;
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#else
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val = le16toh(sval);
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#endif
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break;
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case 4:
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val = bus_space_read_4(sc->sc_tag, sc->sc_handle, ofs);
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#ifndef CFI_HARDWAREBYTESWAP
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val = le32toh(val);
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#endif
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break;
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default:
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val = ~0;
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break;
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}
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return (val);
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}
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static void
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cfi_write(struct cfi_softc *sc, u_int ofs, u_int val)
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{
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ofs &= ~(sc->sc_width - 1);
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switch (sc->sc_width) {
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case 1:
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bus_space_write_1(sc->sc_tag, sc->sc_handle, ofs, val);
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break;
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case 2:
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#ifdef CFI_HARDWAREBYTESWAP
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bus_space_write_2(sc->sc_tag, sc->sc_handle, ofs, val);
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#else
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bus_space_write_2(sc->sc_tag, sc->sc_handle, ofs, htole16(val));
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#endif
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break;
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case 4:
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#ifdef CFI_HARDWAREBYTESWAP
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bus_space_write_4(sc->sc_tag, sc->sc_handle, ofs, val);
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#else
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bus_space_write_4(sc->sc_tag, sc->sc_handle, ofs, htole32(val));
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#endif
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break;
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}
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}
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/*
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* This is same workaound as NetBSD sys/dev/nor/cfi.c cfi_reset_default()
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*/
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static void
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cfi_reset_default(struct cfi_softc *sc)
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{
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cfi_write(sc, 0, CFI_BCS_READ_ARRAY2);
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cfi_write(sc, 0, CFI_BCS_READ_ARRAY);
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}
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uint8_t
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cfi_read_qry(struct cfi_softc *sc, u_int ofs)
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{
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uint8_t val;
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cfi_write(sc, CFI_QRY_CMD_ADDR * sc->sc_width, CFI_QRY_CMD_DATA);
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val = cfi_read(sc, ofs * sc->sc_width);
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cfi_reset_default(sc);
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return (val);
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}
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static void
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cfi_amd_write(struct cfi_softc *sc, u_int ofs, u_int addr, u_int data)
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{
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cfi_write(sc, ofs + AMD_ADDR_START, CFI_AMD_UNLOCK);
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cfi_write(sc, ofs + AMD_ADDR_ACK, CFI_AMD_UNLOCK_ACK);
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cfi_write(sc, ofs + addr, data);
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}
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static char *
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cfi_fmtsize(uint32_t sz)
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{
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static char buf[8];
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static const char *sfx[] = { "", "K", "M", "G" };
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int sfxidx;
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sfxidx = 0;
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while (sfxidx < 3 && sz > 1023) {
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sz /= 1024;
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sfxidx++;
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}
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sprintf(buf, "%u%sB", sz, sfx[sfxidx]);
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return (buf);
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}
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int
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cfi_probe(device_t dev)
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{
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char desc[80];
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struct cfi_softc *sc;
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char *vend_str;
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int error;
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uint16_t iface, vend;
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sc = device_get_softc(dev);
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sc->sc_dev = dev;
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sc->sc_rid = 0;
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sc->sc_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->sc_rid,
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RF_ACTIVE);
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if (sc->sc_res == NULL)
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return (ENXIO);
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sc->sc_tag = rman_get_bustag(sc->sc_res);
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sc->sc_handle = rman_get_bushandle(sc->sc_res);
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if (sc->sc_width == 0) {
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sc->sc_width = 1;
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while (sc->sc_width <= 4) {
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if (cfi_read_qry(sc, CFI_QRY_IDENT) == 'Q')
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break;
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sc->sc_width <<= 1;
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}
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} else if (cfi_read_qry(sc, CFI_QRY_IDENT) != 'Q') {
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error = ENXIO;
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goto out;
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}
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if (sc->sc_width > 4) {
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error = ENXIO;
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goto out;
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}
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/* We got a Q. Check if we also have the R and the Y. */
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if (cfi_read_qry(sc, CFI_QRY_IDENT + 1) != 'R' ||
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cfi_read_qry(sc, CFI_QRY_IDENT + 2) != 'Y') {
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error = ENXIO;
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goto out;
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}
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/* Get the vendor and command set. */
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vend = cfi_read_qry(sc, CFI_QRY_VEND) |
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(cfi_read_qry(sc, CFI_QRY_VEND + 1) << 8);
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sc->sc_cmdset = vend;
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switch (vend) {
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case CFI_VEND_AMD_ECS:
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case CFI_VEND_AMD_SCS:
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vend_str = "AMD/Fujitsu";
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break;
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case CFI_VEND_INTEL_ECS:
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vend_str = "Intel/Sharp";
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break;
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case CFI_VEND_INTEL_SCS:
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vend_str = "Intel";
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break;
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case CFI_VEND_MITSUBISHI_ECS:
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case CFI_VEND_MITSUBISHI_SCS:
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vend_str = "Mitsubishi";
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break;
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default:
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vend_str = "Unknown vendor";
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break;
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}
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/* Get the device size. */
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sc->sc_size = 1U << cfi_read_qry(sc, CFI_QRY_SIZE);
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/* Sanity-check the I/F */
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iface = cfi_read_qry(sc, CFI_QRY_IFACE) |
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(cfi_read_qry(sc, CFI_QRY_IFACE + 1) << 8);
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/*
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* Adding 1 to iface will give us a bit-wise "switch"
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* that allows us to test for the interface width by
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* testing a single bit.
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*/
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iface++;
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error = (iface & sc->sc_width) ? 0 : EINVAL;
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if (error)
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goto out;
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snprintf(desc, sizeof(desc), "%s - %s", vend_str,
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cfi_fmtsize(sc->sc_size));
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device_set_desc_copy(dev, desc);
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out:
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bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_rid, sc->sc_res);
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return (error);
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}
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int
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cfi_attach(device_t dev)
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{
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struct cfi_softc *sc;
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u_int blksz, blocks;
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u_int r, u;
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uint64_t mtoexp, ttoexp;
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#ifdef CFI_SUPPORT_STRATAFLASH
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uint64_t ppr;
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char name[KENV_MNAMELEN], value[32];
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#endif
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sc = device_get_softc(dev);
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sc->sc_dev = dev;
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sc->sc_rid = 0;
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sc->sc_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->sc_rid,
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#ifndef ATSE_CFI_HACK
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RF_ACTIVE);
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#else
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RF_ACTIVE | RF_SHAREABLE);
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#endif
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if (sc->sc_res == NULL)
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return (ENXIO);
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sc->sc_tag = rman_get_bustag(sc->sc_res);
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sc->sc_handle = rman_get_bushandle(sc->sc_res);
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/* Get time-out values for erase, write, and buffer write. */
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ttoexp = cfi_read_qry(sc, CFI_QRY_TTO_ERASE);
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mtoexp = cfi_read_qry(sc, CFI_QRY_MTO_ERASE);
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if (ttoexp == 0) {
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device_printf(dev, "erase timeout == 0, using 2^16ms\n");
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ttoexp = 16;
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}
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if (ttoexp > 41) {
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device_printf(dev, "insane timeout: 2^%jdms\n", ttoexp);
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return (EINVAL);
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}
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if (mtoexp == 0) {
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device_printf(dev, "max erase timeout == 0, using 2^%jdms\n",
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ttoexp + 4);
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mtoexp = 4;
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}
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if (ttoexp + mtoexp > 41) {
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device_printf(dev, "insane max erase timeout: 2^%jd\n",
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ttoexp + mtoexp);
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return (EINVAL);
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}
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sc->sc_typical_timeouts[CFI_TIMEOUT_ERASE] = SBT_1MS * (1ULL << ttoexp);
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sc->sc_max_timeouts[CFI_TIMEOUT_ERASE] =
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sc->sc_typical_timeouts[CFI_TIMEOUT_ERASE] * (1ULL << mtoexp);
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ttoexp = cfi_read_qry(sc, CFI_QRY_TTO_WRITE);
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mtoexp = cfi_read_qry(sc, CFI_QRY_MTO_WRITE);
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if (ttoexp == 0) {
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device_printf(dev, "write timeout == 0, using 2^18ns\n");
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ttoexp = 18;
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}
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if (ttoexp > 51) {
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device_printf(dev, "insane write timeout: 2^%jdus\n", ttoexp);
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return (EINVAL);
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}
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if (mtoexp == 0) {
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device_printf(dev, "max write timeout == 0, using 2^%jdms\n",
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ttoexp + 4);
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mtoexp = 4;
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}
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if (ttoexp + mtoexp > 51) {
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device_printf(dev, "insane max write timeout: 2^%jdus\n",
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ttoexp + mtoexp);
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return (EINVAL);
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}
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sc->sc_typical_timeouts[CFI_TIMEOUT_WRITE] = SBT_1US * (1ULL << ttoexp);
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sc->sc_max_timeouts[CFI_TIMEOUT_WRITE] =
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sc->sc_typical_timeouts[CFI_TIMEOUT_WRITE] * (1ULL << mtoexp);
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ttoexp = cfi_read_qry(sc, CFI_QRY_TTO_BUFWRITE);
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mtoexp = cfi_read_qry(sc, CFI_QRY_MTO_BUFWRITE);
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/* Don't check for 0, it means not-supported. */
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if (ttoexp > 51) {
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device_printf(dev, "insane write timeout: 2^%jdus\n", ttoexp);
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return (EINVAL);
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}
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if (ttoexp + mtoexp > 51) {
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device_printf(dev, "insane max write timeout: 2^%jdus\n",
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ttoexp + mtoexp);
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return (EINVAL);
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}
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sc->sc_typical_timeouts[CFI_TIMEOUT_BUFWRITE] =
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SBT_1US * (1ULL << cfi_read_qry(sc, CFI_QRY_TTO_BUFWRITE));
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sc->sc_max_timeouts[CFI_TIMEOUT_BUFWRITE] =
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sc->sc_typical_timeouts[CFI_TIMEOUT_BUFWRITE] *
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(1ULL << cfi_read_qry(sc, CFI_QRY_MTO_BUFWRITE));
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/* Get the maximum size of a multibyte program */
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if (sc->sc_typical_timeouts[CFI_TIMEOUT_BUFWRITE] != 0)
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sc->sc_maxbuf = 1 << (cfi_read_qry(sc, CFI_QRY_MAXBUF) |
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cfi_read_qry(sc, CFI_QRY_MAXBUF) << 8);
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else
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sc->sc_maxbuf = 0;
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/* Get erase regions. */
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sc->sc_regions = cfi_read_qry(sc, CFI_QRY_NREGIONS);
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sc->sc_region = malloc(sc->sc_regions * sizeof(struct cfi_region),
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M_TEMP, M_WAITOK | M_ZERO);
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for (r = 0; r < sc->sc_regions; r++) {
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blocks = cfi_read_qry(sc, CFI_QRY_REGION(r)) |
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(cfi_read_qry(sc, CFI_QRY_REGION(r) + 1) << 8);
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sc->sc_region[r].r_blocks = blocks + 1;
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blksz = cfi_read_qry(sc, CFI_QRY_REGION(r) + 2) |
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(cfi_read_qry(sc, CFI_QRY_REGION(r) + 3) << 8);
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sc->sc_region[r].r_blksz = (blksz == 0) ? 128 :
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blksz * 256;
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}
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/* Reset the device to a default state. */
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cfi_write(sc, 0, CFI_BCS_CLEAR_STATUS);
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if (bootverbose) {
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device_printf(dev, "[");
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for (r = 0; r < sc->sc_regions; r++) {
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printf("%ux%s%s", sc->sc_region[r].r_blocks,
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cfi_fmtsize(sc->sc_region[r].r_blksz),
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(r == sc->sc_regions - 1) ? "]\n" : ",");
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}
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}
|
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|
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if (sc->sc_cmdset == CFI_VEND_AMD_ECS ||
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sc->sc_cmdset == CFI_VEND_AMD_SCS) {
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cfi_amd_write(sc, 0, AMD_ADDR_START, CFI_AMD_AUTO_SELECT);
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sc->sc_manid = cfi_read(sc, 0);
|
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sc->sc_devid = cfi_read(sc, 2);
|
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device_printf(dev, "Manufacturer ID:%x Device ID:%x\n",
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sc->sc_manid, sc->sc_devid);
|
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cfi_write(sc, 0, CFI_BCS_READ_ARRAY2);
|
|
}
|
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|
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u = device_get_unit(dev);
|
|
sc->sc_nod = make_dev(&cfi_cdevsw, u, UID_ROOT, GID_WHEEL, 0600,
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"%s%u", cfi_driver_name, u);
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sc->sc_nod->si_drv1 = sc;
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|
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cfi_add_sysctls(sc);
|
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|
|
#ifdef CFI_SUPPORT_STRATAFLASH
|
|
/*
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* Store the Intel factory PPR in the environment. In some
|
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* cases it is the most unique ID on a board.
|
|
*/
|
|
if (cfi_intel_get_factory_pr(sc, &ppr) == 0) {
|
|
if (snprintf(name, sizeof(name), "%s.factory_ppr",
|
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device_get_nameunit(dev)) < (sizeof(name) - 1) &&
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snprintf(value, sizeof(value), "0x%016jx", ppr) <
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(sizeof(value) - 1))
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|
(void) kern_setenv(name, value);
|
|
}
|
|
#endif
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|
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device_add_child(dev, "cfid", -1);
|
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bus_generic_attach(dev);
|
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|
|
return (0);
|
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}
|
|
|
|
static void
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|
cfi_add_sysctls(struct cfi_softc *sc)
|
|
{
|
|
struct sysctl_ctx_list *ctx;
|
|
struct sysctl_oid_list *children;
|
|
|
|
ctx = device_get_sysctl_ctx(sc->sc_dev);
|
|
children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->sc_dev));
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|
|
|
SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
|
|
"typical_erase_timout_count",
|
|
CTLFLAG_RD, &sc->sc_tto_counts[CFI_TIMEOUT_ERASE],
|
|
0, "Number of times the typical erase timeout was exceeded");
|
|
SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
|
|
"max_erase_timout_count",
|
|
CTLFLAG_RD, &sc->sc_mto_counts[CFI_TIMEOUT_ERASE], 0,
|
|
"Number of times the maximum erase timeout was exceeded");
|
|
SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
|
|
"typical_write_timout_count",
|
|
CTLFLAG_RD, &sc->sc_tto_counts[CFI_TIMEOUT_WRITE], 0,
|
|
"Number of times the typical write timeout was exceeded");
|
|
SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
|
|
"max_write_timout_count",
|
|
CTLFLAG_RD, &sc->sc_mto_counts[CFI_TIMEOUT_WRITE], 0,
|
|
"Number of times the maximum write timeout was exceeded");
|
|
if (sc->sc_maxbuf > 0) {
|
|
SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
|
|
"typical_bufwrite_timout_count",
|
|
CTLFLAG_RD, &sc->sc_tto_counts[CFI_TIMEOUT_BUFWRITE], 0,
|
|
"Number of times the typical buffered write timeout was "
|
|
"exceeded");
|
|
SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
|
|
"max_bufwrite_timout_count",
|
|
CTLFLAG_RD, &sc->sc_mto_counts[CFI_TIMEOUT_BUFWRITE], 0,
|
|
"Number of times the maximum buffered write timeout was "
|
|
"exceeded");
|
|
}
|
|
}
|
|
|
|
int
|
|
cfi_detach(device_t dev)
|
|
{
|
|
struct cfi_softc *sc;
|
|
|
|
sc = device_get_softc(dev);
|
|
|
|
destroy_dev(sc->sc_nod);
|
|
free(sc->sc_region, M_TEMP);
|
|
bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_rid, sc->sc_res);
|
|
return (0);
|
|
}
|
|
|
|
static bool
|
|
cfi_check_erase(struct cfi_softc *sc, u_int ofs, u_int sz)
|
|
{
|
|
bool result;
|
|
int i;
|
|
uint32_t val;
|
|
|
|
result = FALSE;
|
|
for (i = 0; i < sz; i += sc->sc_width) {
|
|
val = cfi_read(sc, ofs + i);
|
|
switch (sc->sc_width) {
|
|
case 1:
|
|
if (val != 0xff)
|
|
goto out;
|
|
continue;
|
|
case 2:
|
|
if (val != 0xffff)
|
|
goto out;
|
|
continue;
|
|
case 4:
|
|
if (val != 0xffffffff)
|
|
goto out;
|
|
continue;
|
|
}
|
|
}
|
|
result = TRUE;
|
|
|
|
out:
|
|
return (result);
|
|
}
|
|
|
|
static int
|
|
cfi_wait_ready(struct cfi_softc *sc, u_int ofs, sbintime_t start,
|
|
enum cfi_wait_cmd cmd)
|
|
{
|
|
int done, error, tto_exceeded;
|
|
uint32_t st0 = 0, st = 0;
|
|
sbintime_t now;
|
|
|
|
done = 0;
|
|
error = 0;
|
|
tto_exceeded = 0;
|
|
while (!done && !error) {
|
|
/*
|
|
* Save time before we start so we always do one check
|
|
* after the timeout has expired.
|
|
*/
|
|
now = sbinuptime();
|
|
|
|
switch (sc->sc_cmdset) {
|
|
case CFI_VEND_INTEL_ECS:
|
|
case CFI_VEND_INTEL_SCS:
|
|
st = cfi_read(sc, ofs);
|
|
done = (st & CFI_INTEL_STATUS_WSMS);
|
|
if (done) {
|
|
/* NB: bit 0 is reserved */
|
|
st &= ~(CFI_INTEL_XSTATUS_RSVD |
|
|
CFI_INTEL_STATUS_WSMS |
|
|
CFI_INTEL_STATUS_RSVD);
|
|
if (st & CFI_INTEL_STATUS_DPS)
|
|
error = EPERM;
|
|
else if (st & CFI_INTEL_STATUS_PSLBS)
|
|
error = EIO;
|
|
else if (st & CFI_INTEL_STATUS_ECLBS)
|
|
error = ENXIO;
|
|
else if (st)
|
|
error = EACCES;
|
|
}
|
|
break;
|
|
case CFI_VEND_AMD_SCS:
|
|
case CFI_VEND_AMD_ECS:
|
|
st0 = cfi_read(sc, ofs);
|
|
st = cfi_read(sc, ofs);
|
|
done = ((st & 0x40) == (st0 & 0x40)) ? 1 : 0;
|
|
break;
|
|
}
|
|
|
|
if (tto_exceeded ||
|
|
now > start + sc->sc_typical_timeouts[cmd]) {
|
|
if (!tto_exceeded) {
|
|
tto_exceeded = 1;
|
|
sc->sc_tto_counts[cmd]++;
|
|
#ifdef CFI_DEBUG_TIMEOUT
|
|
device_printf(sc->sc_dev,
|
|
"typical timeout exceeded (cmd %d)", cmd);
|
|
#endif
|
|
}
|
|
if (now > start + sc->sc_max_timeouts[cmd]) {
|
|
sc->sc_mto_counts[cmd]++;
|
|
#ifdef CFI_DEBUG_TIMEOUT
|
|
device_printf(sc->sc_dev,
|
|
"max timeout exceeded (cmd %d)", cmd);
|
|
#endif
|
|
}
|
|
}
|
|
}
|
|
if (!done && !error)
|
|
error = ETIMEDOUT;
|
|
if (error)
|
|
printf("\nerror=%d (st 0x%x st0 0x%x)\n", error, st, st0);
|
|
return (error);
|
|
}
|
|
|
|
int
|
|
cfi_write_block(struct cfi_softc *sc)
|
|
{
|
|
union {
|
|
uint8_t *x8;
|
|
uint16_t *x16;
|
|
uint32_t *x32;
|
|
} ptr, cpyprt;
|
|
register_t intr;
|
|
int error, i, j, neederase = 0;
|
|
uint32_t st;
|
|
u_int wlen;
|
|
sbintime_t start;
|
|
u_int minsz;
|
|
uint32_t val;
|
|
|
|
/* Intel flash must be unlocked before modification */
|
|
switch (sc->sc_cmdset) {
|
|
case CFI_VEND_INTEL_ECS:
|
|
case CFI_VEND_INTEL_SCS:
|
|
cfi_write(sc, sc->sc_wrofs, CFI_INTEL_LBS);
|
|
cfi_write(sc, sc->sc_wrofs, CFI_INTEL_UB);
|
|
cfi_write(sc, sc->sc_wrofs, CFI_BCS_READ_ARRAY);
|
|
break;
|
|
}
|
|
|
|
/* Check if an erase is required. */
|
|
for (i = 0; i < sc->sc_wrbufsz; i++)
|
|
if ((sc->sc_wrbuf[i] & sc->sc_wrbufcpy[i]) != sc->sc_wrbuf[i]) {
|
|
neederase = 1;
|
|
break;
|
|
}
|
|
|
|
if (neederase) {
|
|
intr = intr_disable();
|
|
start = sbinuptime();
|
|
/* Erase the block. */
|
|
switch (sc->sc_cmdset) {
|
|
case CFI_VEND_INTEL_ECS:
|
|
case CFI_VEND_INTEL_SCS:
|
|
cfi_write(sc, sc->sc_wrofs, CFI_BCS_BLOCK_ERASE);
|
|
cfi_write(sc, sc->sc_wrofs, CFI_BCS_CONFIRM);
|
|
break;
|
|
case CFI_VEND_AMD_SCS:
|
|
case CFI_VEND_AMD_ECS:
|
|
/* find minimum sector size */
|
|
minsz = sc->sc_region[0].r_blksz;
|
|
for (i = 1; i < sc->sc_regions; i++) {
|
|
if (sc->sc_region[i].r_blksz < minsz)
|
|
minsz = sc->sc_region[i].r_blksz;
|
|
}
|
|
cfi_amd_write(sc, sc->sc_wrofs, AMD_ADDR_START,
|
|
CFI_AMD_ERASE_SECTOR);
|
|
cfi_amd_write(sc, sc->sc_wrofs,
|
|
sc->sc_wrofs >> (ffs(minsz) - 1),
|
|
CFI_AMD_BLOCK_ERASE);
|
|
for (i = 0; i < CFI_AMD_MAXCHK; ++i) {
|
|
if (cfi_check_erase(sc, sc->sc_wrofs,
|
|
sc->sc_wrbufsz))
|
|
break;
|
|
DELAY(10);
|
|
}
|
|
if (i == CFI_AMD_MAXCHK) {
|
|
printf("\nCFI Sector Erase time out error\n");
|
|
return (ENODEV);
|
|
}
|
|
break;
|
|
default:
|
|
/* Better safe than sorry... */
|
|
intr_restore(intr);
|
|
return (ENODEV);
|
|
}
|
|
intr_restore(intr);
|
|
error = cfi_wait_ready(sc, sc->sc_wrofs, start,
|
|
CFI_TIMEOUT_ERASE);
|
|
if (error)
|
|
goto out;
|
|
} else
|
|
error = 0;
|
|
|
|
/* Write the block using a multibyte write if supported. */
|
|
ptr.x8 = sc->sc_wrbuf;
|
|
cpyprt.x8 = sc->sc_wrbufcpy;
|
|
if (sc->sc_maxbuf > sc->sc_width) {
|
|
switch (sc->sc_cmdset) {
|
|
case CFI_VEND_INTEL_ECS:
|
|
case CFI_VEND_INTEL_SCS:
|
|
for (i = 0; i < sc->sc_wrbufsz; i += wlen) {
|
|
wlen = MIN(sc->sc_maxbuf, sc->sc_wrbufsz - i);
|
|
|
|
intr = intr_disable();
|
|
|
|
start = sbinuptime();
|
|
do {
|
|
cfi_write(sc, sc->sc_wrofs + i,
|
|
CFI_BCS_BUF_PROG_SETUP);
|
|
if (sbinuptime() > start + sc->sc_max_timeouts[CFI_TIMEOUT_BUFWRITE]) {
|
|
error = ETIMEDOUT;
|
|
goto out;
|
|
}
|
|
st = cfi_read(sc, sc->sc_wrofs + i);
|
|
} while (! (st & CFI_INTEL_STATUS_WSMS));
|
|
|
|
cfi_write(sc, sc->sc_wrofs + i,
|
|
(wlen / sc->sc_width) - 1);
|
|
switch (sc->sc_width) {
|
|
case 1:
|
|
bus_space_write_region_1(sc->sc_tag,
|
|
sc->sc_handle, sc->sc_wrofs + i,
|
|
ptr.x8 + i, wlen);
|
|
break;
|
|
case 2:
|
|
bus_space_write_region_2(sc->sc_tag,
|
|
sc->sc_handle, sc->sc_wrofs + i,
|
|
ptr.x16 + i / 2, wlen / 2);
|
|
break;
|
|
case 4:
|
|
bus_space_write_region_4(sc->sc_tag,
|
|
sc->sc_handle, sc->sc_wrofs + i,
|
|
ptr.x32 + i / 4, wlen / 4);
|
|
break;
|
|
}
|
|
|
|
cfi_write(sc, sc->sc_wrofs + i,
|
|
CFI_BCS_CONFIRM);
|
|
|
|
intr_restore(intr);
|
|
|
|
error = cfi_wait_ready(sc, sc->sc_wrofs + i,
|
|
start, CFI_TIMEOUT_BUFWRITE);
|
|
if (error != 0)
|
|
goto out;
|
|
}
|
|
goto out;
|
|
default:
|
|
/* Fall through to single word case */
|
|
break;
|
|
}
|
|
}
|
|
|
|
/* Write the block one byte/word at a time. */
|
|
for (i = 0; i < sc->sc_wrbufsz; i += sc->sc_width) {
|
|
/* Avoid writing unless we are actually changing bits */
|
|
if (!neederase) {
|
|
switch (sc->sc_width) {
|
|
case 1:
|
|
if(*(ptr.x8 + i) == *(cpyprt.x8 + i))
|
|
continue;
|
|
break;
|
|
case 2:
|
|
if(*(ptr.x16 + i / 2) == *(cpyprt.x16 + i / 2))
|
|
continue;
|
|
break;
|
|
case 4:
|
|
if(*(ptr.x32 + i / 4) == *(cpyprt.x32 + i / 4))
|
|
continue;
|
|
break;
|
|
}
|
|
}
|
|
|
|
/*
|
|
* Make sure the command to start a write and the
|
|
* actual write happens back-to-back without any
|
|
* excessive delays.
|
|
*/
|
|
intr = intr_disable();
|
|
|
|
start = sbinuptime();
|
|
switch (sc->sc_cmdset) {
|
|
case CFI_VEND_INTEL_ECS:
|
|
case CFI_VEND_INTEL_SCS:
|
|
cfi_write(sc, sc->sc_wrofs + i, CFI_BCS_PROGRAM);
|
|
break;
|
|
case CFI_VEND_AMD_SCS:
|
|
case CFI_VEND_AMD_ECS:
|
|
cfi_amd_write(sc, 0, AMD_ADDR_START, CFI_AMD_PROGRAM);
|
|
break;
|
|
}
|
|
switch (sc->sc_width) {
|
|
case 1:
|
|
bus_space_write_1(sc->sc_tag, sc->sc_handle,
|
|
sc->sc_wrofs + i, *(ptr.x8 + i));
|
|
break;
|
|
case 2:
|
|
bus_space_write_2(sc->sc_tag, sc->sc_handle,
|
|
sc->sc_wrofs + i, *(ptr.x16 + i / 2));
|
|
break;
|
|
case 4:
|
|
bus_space_write_4(sc->sc_tag, sc->sc_handle,
|
|
sc->sc_wrofs + i, *(ptr.x32 + i / 4));
|
|
break;
|
|
}
|
|
|
|
intr_restore(intr);
|
|
|
|
if (sc->sc_cmdset == CFI_VEND_AMD_ECS ||
|
|
sc->sc_cmdset == CFI_VEND_AMD_SCS) {
|
|
for (j = 0; j < CFI_AMD_MAXCHK; ++j) {
|
|
switch (sc->sc_width) {
|
|
case 1:
|
|
val = *(ptr.x8 + i);
|
|
break;
|
|
case 2:
|
|
val = *(ptr.x16 + i / 2);
|
|
break;
|
|
case 4:
|
|
val = *(ptr.x32 + i / 4);
|
|
break;
|
|
}
|
|
|
|
if (cfi_read(sc, sc->sc_wrofs + i) == val)
|
|
break;
|
|
|
|
DELAY(10);
|
|
}
|
|
if (j == CFI_AMD_MAXCHK) {
|
|
printf("\nCFI Program Verify time out error\n");
|
|
error = ENXIO;
|
|
goto out;
|
|
}
|
|
} else {
|
|
error = cfi_wait_ready(sc, sc->sc_wrofs, start,
|
|
CFI_TIMEOUT_WRITE);
|
|
if (error)
|
|
goto out;
|
|
}
|
|
}
|
|
|
|
/* error is 0. */
|
|
|
|
out:
|
|
cfi_reset_default(sc);
|
|
|
|
/* Relock Intel flash */
|
|
switch (sc->sc_cmdset) {
|
|
case CFI_VEND_INTEL_ECS:
|
|
case CFI_VEND_INTEL_SCS:
|
|
cfi_write(sc, sc->sc_wrofs, CFI_INTEL_LBS);
|
|
cfi_write(sc, sc->sc_wrofs, CFI_INTEL_LB);
|
|
cfi_write(sc, sc->sc_wrofs, CFI_BCS_READ_ARRAY);
|
|
break;
|
|
}
|
|
return (error);
|
|
}
|
|
|
|
#ifdef CFI_SUPPORT_STRATAFLASH
|
|
/*
|
|
* Intel StrataFlash Protection Register Support.
|
|
*
|
|
* The memory includes a 128-bit Protection Register that can be
|
|
* used for security. There are two 64-bit segments; one is programmed
|
|
* at the factory with a unique 64-bit number which is immutable.
|
|
* The other segment is left blank for User (OEM) programming.
|
|
* The User/OEM segment is One Time Programmable (OTP). It can also
|
|
* be locked to prevent any further writes by setting bit 0 of the
|
|
* Protection Lock Register (PLR). The PLR can written only once.
|
|
*/
|
|
|
|
static uint16_t
|
|
cfi_get16(struct cfi_softc *sc, int off)
|
|
{
|
|
uint16_t v = bus_space_read_2(sc->sc_tag, sc->sc_handle, off<<1);
|
|
return v;
|
|
}
|
|
|
|
#ifdef CFI_ARMEDANDDANGEROUS
|
|
static void
|
|
cfi_put16(struct cfi_softc *sc, int off, uint16_t v)
|
|
{
|
|
bus_space_write_2(sc->sc_tag, sc->sc_handle, off<<1, v);
|
|
}
|
|
#endif
|
|
|
|
/*
|
|
* Read the factory-defined 64-bit segment of the PR.
|
|
*/
|
|
int
|
|
cfi_intel_get_factory_pr(struct cfi_softc *sc, uint64_t *id)
|
|
{
|
|
if (sc->sc_cmdset != CFI_VEND_INTEL_ECS)
|
|
return EOPNOTSUPP;
|
|
KASSERT(sc->sc_width == 2, ("sc_width %d", sc->sc_width));
|
|
|
|
cfi_write(sc, 0, CFI_INTEL_READ_ID);
|
|
*id = ((uint64_t)cfi_get16(sc, CFI_INTEL_PR(0)))<<48 |
|
|
((uint64_t)cfi_get16(sc, CFI_INTEL_PR(1)))<<32 |
|
|
((uint64_t)cfi_get16(sc, CFI_INTEL_PR(2)))<<16 |
|
|
((uint64_t)cfi_get16(sc, CFI_INTEL_PR(3)));
|
|
cfi_write(sc, 0, CFI_BCS_READ_ARRAY);
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* Read the User/OEM 64-bit segment of the PR.
|
|
*/
|
|
int
|
|
cfi_intel_get_oem_pr(struct cfi_softc *sc, uint64_t *id)
|
|
{
|
|
if (sc->sc_cmdset != CFI_VEND_INTEL_ECS)
|
|
return EOPNOTSUPP;
|
|
KASSERT(sc->sc_width == 2, ("sc_width %d", sc->sc_width));
|
|
|
|
cfi_write(sc, 0, CFI_INTEL_READ_ID);
|
|
*id = ((uint64_t)cfi_get16(sc, CFI_INTEL_PR(4)))<<48 |
|
|
((uint64_t)cfi_get16(sc, CFI_INTEL_PR(5)))<<32 |
|
|
((uint64_t)cfi_get16(sc, CFI_INTEL_PR(6)))<<16 |
|
|
((uint64_t)cfi_get16(sc, CFI_INTEL_PR(7)));
|
|
cfi_write(sc, 0, CFI_BCS_READ_ARRAY);
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* Write the User/OEM 64-bit segment of the PR.
|
|
* XXX should allow writing individual words/bytes
|
|
*/
|
|
int
|
|
cfi_intel_set_oem_pr(struct cfi_softc *sc, uint64_t id)
|
|
{
|
|
#ifdef CFI_ARMEDANDDANGEROUS
|
|
register_t intr;
|
|
int i, error;
|
|
sbintime_t start;
|
|
#endif
|
|
|
|
if (sc->sc_cmdset != CFI_VEND_INTEL_ECS)
|
|
return EOPNOTSUPP;
|
|
KASSERT(sc->sc_width == 2, ("sc_width %d", sc->sc_width));
|
|
|
|
#ifdef CFI_ARMEDANDDANGEROUS
|
|
for (i = 7; i >= 4; i--, id >>= 16) {
|
|
intr = intr_disable();
|
|
start = sbinuptime();
|
|
cfi_write(sc, 0, CFI_INTEL_PP_SETUP);
|
|
cfi_put16(sc, CFI_INTEL_PR(i), id&0xffff);
|
|
intr_restore(intr);
|
|
error = cfi_wait_ready(sc, CFI_BCS_READ_STATUS, start,
|
|
CFI_TIMEOUT_WRITE);
|
|
if (error)
|
|
break;
|
|
}
|
|
cfi_write(sc, 0, CFI_BCS_READ_ARRAY);
|
|
return error;
|
|
#else
|
|
device_printf(sc->sc_dev, "%s: OEM PR not set, "
|
|
"CFI_ARMEDANDDANGEROUS not configured\n", __func__);
|
|
return ENXIO;
|
|
#endif
|
|
}
|
|
|
|
/*
|
|
* Read the contents of the Protection Lock Register.
|
|
*/
|
|
int
|
|
cfi_intel_get_plr(struct cfi_softc *sc, uint32_t *plr)
|
|
{
|
|
if (sc->sc_cmdset != CFI_VEND_INTEL_ECS)
|
|
return EOPNOTSUPP;
|
|
KASSERT(sc->sc_width == 2, ("sc_width %d", sc->sc_width));
|
|
|
|
cfi_write(sc, 0, CFI_INTEL_READ_ID);
|
|
*plr = cfi_get16(sc, CFI_INTEL_PLR);
|
|
cfi_write(sc, 0, CFI_BCS_READ_ARRAY);
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* Write the Protection Lock Register to lock down the
|
|
* user-settable segment of the Protection Register.
|
|
* NOTE: this operation is not reversible.
|
|
*/
|
|
int
|
|
cfi_intel_set_plr(struct cfi_softc *sc)
|
|
{
|
|
#ifdef CFI_ARMEDANDDANGEROUS
|
|
register_t intr;
|
|
int error;
|
|
sbintime_t start;
|
|
#endif
|
|
if (sc->sc_cmdset != CFI_VEND_INTEL_ECS)
|
|
return EOPNOTSUPP;
|
|
KASSERT(sc->sc_width == 2, ("sc_width %d", sc->sc_width));
|
|
|
|
#ifdef CFI_ARMEDANDDANGEROUS
|
|
/* worthy of console msg */
|
|
device_printf(sc->sc_dev, "set PLR\n");
|
|
intr = intr_disable();
|
|
binuptime(&start);
|
|
cfi_write(sc, 0, CFI_INTEL_PP_SETUP);
|
|
cfi_put16(sc, CFI_INTEL_PLR, 0xFFFD);
|
|
intr_restore(intr);
|
|
error = cfi_wait_ready(sc, CFI_BCS_READ_STATUS, start,
|
|
CFI_TIMEOUT_WRITE);
|
|
cfi_write(sc, 0, CFI_BCS_READ_ARRAY);
|
|
return error;
|
|
#else
|
|
device_printf(sc->sc_dev, "%s: PLR not set, "
|
|
"CFI_ARMEDANDDANGEROUS not configured\n", __func__);
|
|
return ENXIO;
|
|
#endif
|
|
}
|
|
#endif /* CFI_SUPPORT_STRATAFLASH */
|