Each channel gets its own DMA resources, cleanup and "bufferpool" tasks, and a separate cleanup taskqueue to isolate channels operation as much as possible to avoid various kernel panics under heavy network load. As a side-effect of this work, dpaa2_buf structure is simplified and all of the functions to re-seed those buffers are gathered now in dpaa2_buf.h and .c files; functions to work with channels are extracted into dpaa2_channel.h and .c files as well. Reported by: dch Reviewed by: bz Approved by: bz (mentor) MFC after: 1 week Differential Revision: https://reviews.freebsd.org/D41296
604 lines
16 KiB
C
604 lines
16 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright © 2021-2022 Dmitry Salychev
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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/*
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* QBMan command interface and the DPAA2 I/O (DPIO) driver.
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*
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* The DPIO object allows configuration of the QBMan software portal with
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* optional notification capabilities.
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*
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* Software portals are used by the driver to communicate with the QBMan. The
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* DPIO object’s main purpose is to enable the driver to perform I/O – enqueue
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* and dequeue operations, as well as buffer release and acquire operations –
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* using QBMan.
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*/
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#include "opt_rss.h"
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#include <sys/param.h>
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#include <sys/kernel.h>
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#include <sys/bus.h>
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#include <sys/rman.h>
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#include <sys/module.h>
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#include <sys/malloc.h>
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#include <sys/lock.h>
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#include <sys/mutex.h>
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#include <sys/_cpuset.h>
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#include <sys/cpuset.h>
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#include <sys/taskqueue.h>
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#include <sys/smp.h>
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#include <vm/vm.h>
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#include <machine/bus.h>
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#include <machine/resource.h>
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#include <dev/pci/pcivar.h>
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#ifdef RSS
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#include <net/rss_config.h>
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#endif
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#include "pcib_if.h"
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#include "pci_if.h"
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#include "dpaa2_mc.h"
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#include "dpaa2_mcp.h"
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#include "dpaa2_swp.h"
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#include "dpaa2_swp_if.h"
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#include "dpaa2_cmd_if.h"
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#include "dpaa2_io.h"
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#include "dpaa2_ni.h"
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#include "dpaa2_channel.h"
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#define DPIO_IRQ_INDEX 0 /* index of the only DPIO IRQ */
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#define DPIO_POLL_MAX 32
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/*
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* Memory:
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* 0: cache-enabled part of the QBMan software portal.
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* 1: cache-inhibited part of the QBMan software portal.
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* 2: control registers of the QBMan software portal?
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*
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* Note that MSI should be allocated separately using pseudo-PCI interface.
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*/
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struct resource_spec dpaa2_io_spec[] = {
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/*
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* System Memory resources.
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*/
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#define MEM_RES_NUM (3u)
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#define MEM_RID_OFF (0u)
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#define MEM_RID(rid) ((rid) + MEM_RID_OFF)
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{ SYS_RES_MEMORY, MEM_RID(0), RF_ACTIVE | RF_UNMAPPED },
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{ SYS_RES_MEMORY, MEM_RID(1), RF_ACTIVE | RF_UNMAPPED },
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{ SYS_RES_MEMORY, MEM_RID(2), RF_ACTIVE | RF_UNMAPPED | RF_OPTIONAL },
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/*
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* DPMCP resources.
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*
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* NOTE: MC command portals (MCPs) are used to send commands to, and
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* receive responses from, the MC firmware. One portal per DPIO.
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*/
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#define MCP_RES_NUM (1u)
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#define MCP_RID_OFF (MEM_RID_OFF + MEM_RES_NUM)
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#define MCP_RID(rid) ((rid) + MCP_RID_OFF)
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/* --- */
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{ DPAA2_DEV_MCP, MCP_RID(0), RF_ACTIVE | RF_SHAREABLE | RF_OPTIONAL },
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/* --- */
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RESOURCE_SPEC_END
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};
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/* Configuration routines. */
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static int dpaa2_io_setup_irqs(device_t dev);
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static int dpaa2_io_release_irqs(device_t dev);
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static int dpaa2_io_setup_msi(struct dpaa2_io_softc *sc);
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static int dpaa2_io_release_msi(struct dpaa2_io_softc *sc);
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/* Interrupt handlers */
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static void dpaa2_io_intr(void *arg);
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static int
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dpaa2_io_probe(device_t dev)
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{
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/* DPIO device will be added by a parent resource container itself. */
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device_set_desc(dev, "DPAA2 I/O");
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return (BUS_PROBE_DEFAULT);
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}
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static int
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dpaa2_io_detach(device_t dev)
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{
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device_t pdev = device_get_parent(dev);
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device_t child = dev;
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struct dpaa2_io_softc *sc = device_get_softc(dev);
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struct dpaa2_devinfo *rcinfo = device_get_ivars(pdev);
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struct dpaa2_devinfo *dinfo = device_get_ivars(dev);
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struct dpaa2_cmd cmd;
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uint16_t rc_token, io_token;
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int error;
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DPAA2_CMD_INIT(&cmd);
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/* Tear down interrupt handler and release IRQ resources. */
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dpaa2_io_release_irqs(dev);
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/* Free software portal helper object. */
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dpaa2_swp_free_portal(sc->swp);
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error = DPAA2_CMD_RC_OPEN(dev, child, &cmd, rcinfo->id, &rc_token);
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if (error) {
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device_printf(dev, "%s: failed to open DPRC: error=%d\n",
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__func__, error);
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goto err_exit;
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}
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error = DPAA2_CMD_IO_OPEN(dev, child, &cmd, dinfo->id, &io_token);
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if (error) {
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device_printf(dev, "%s: failed to open DPIO: id=%d, error=%d\n",
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__func__, dinfo->id, error);
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goto close_rc;
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}
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error = DPAA2_CMD_IO_DISABLE(dev, child, &cmd);
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if (error && bootverbose) {
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device_printf(dev, "%s: failed to disable DPIO: id=%d, "
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"error=%d\n", __func__, dinfo->id, error);
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}
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(void)DPAA2_CMD_IO_CLOSE(dev, child, &cmd);
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(void)DPAA2_CMD_RC_CLOSE(dev, child, DPAA2_CMD_TK(&cmd, rc_token));
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/* Unmap memory resources of the portal. */
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for (int i = 0; i < MEM_RES_NUM; i++) {
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if (sc->res[MEM_RID(i)] == NULL) {
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continue;
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}
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error = bus_unmap_resource(sc->dev, SYS_RES_MEMORY,
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sc->res[MEM_RID(i)], &sc->map[MEM_RID(i)]);
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if (error && bootverbose) {
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device_printf(dev, "%s: failed to unmap memory "
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"resource: rid=%d, error=%d\n", __func__, MEM_RID(i),
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error);
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}
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}
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/* Release allocated resources. */
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bus_release_resources(dev, dpaa2_io_spec, sc->res);
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return (0);
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close_rc:
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(void)DPAA2_CMD_RC_CLOSE(dev, child, DPAA2_CMD_TK(&cmd, rc_token));
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err_exit:
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return (error);
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}
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static int
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dpaa2_io_attach(device_t dev)
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{
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device_t pdev = device_get_parent(dev);
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device_t child = dev;
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device_t mcp_dev;
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struct dpaa2_io_softc *sc = device_get_softc(dev);
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struct dpaa2_devinfo *rcinfo = device_get_ivars(pdev);
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struct dpaa2_devinfo *dinfo = device_get_ivars(dev);
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struct dpaa2_devinfo *mcp_dinfo;
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struct dpaa2_cmd cmd;
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struct resource_map_request req;
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struct {
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vm_memattr_t memattr;
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char *label;
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} map_args[MEM_RES_NUM] = {
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{ VM_MEMATTR_WRITE_BACK, "cache-enabled part" },
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{ VM_MEMATTR_DEVICE, "cache-inhibited part" },
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{ VM_MEMATTR_DEVICE, "control registers" }
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};
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uint16_t rc_token, io_token;
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int error;
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sc->dev = dev;
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sc->swp = NULL;
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sc->intr = NULL;
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sc->irq_resource = NULL;
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/* Allocate resources. */
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error = bus_alloc_resources(sc->dev, dpaa2_io_spec, sc->res);
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if (error) {
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device_printf(dev, "%s: failed to allocate resources: "
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"error=%d\n", __func__, error);
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return (ENXIO);
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}
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/* Set allocated MC portal up. */
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mcp_dev = (device_t) rman_get_start(sc->res[MCP_RID(0)]);
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mcp_dinfo = device_get_ivars(mcp_dev);
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dinfo->portal = mcp_dinfo->portal;
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/* Map memory resources of the portal. */
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for (int i = 0; i < MEM_RES_NUM; i++) {
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if (sc->res[MEM_RID(i)] == NULL) {
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continue;
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}
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resource_init_map_request(&req);
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req.memattr = map_args[i].memattr;
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error = bus_map_resource(sc->dev, SYS_RES_MEMORY,
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sc->res[MEM_RID(i)], &req, &sc->map[MEM_RID(i)]);
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if (error) {
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device_printf(dev, "%s: failed to map %s: error=%d\n",
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__func__, map_args[i].label, error);
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goto err_exit;
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}
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}
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DPAA2_CMD_INIT(&cmd);
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error = DPAA2_CMD_RC_OPEN(dev, child, &cmd, rcinfo->id, &rc_token);
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if (error) {
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device_printf(dev, "%s: failed to open DPRC: error=%d\n",
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__func__, error);
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goto err_exit;
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}
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error = DPAA2_CMD_IO_OPEN(dev, child, &cmd, dinfo->id, &io_token);
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if (error) {
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device_printf(dev, "%s: failed to open DPIO: id=%d, error=%d\n",
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__func__, dinfo->id, error);
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goto close_rc;
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}
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error = DPAA2_CMD_IO_RESET(dev, child, &cmd);
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if (error) {
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device_printf(dev, "%s: failed to reset DPIO: id=%d, error=%d\n",
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__func__, dinfo->id, error);
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goto close_io;
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}
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error = DPAA2_CMD_IO_GET_ATTRIBUTES(dev, child, &cmd, &sc->attr);
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if (error) {
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device_printf(dev, "%s: failed to get DPIO attributes: id=%d, "
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"error=%d\n", __func__, dinfo->id, error);
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goto close_io;
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}
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error = DPAA2_CMD_IO_ENABLE(dev, child, &cmd);
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if (error) {
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device_printf(dev, "%s: failed to enable DPIO: id=%d, "
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"error=%d\n", __func__, dinfo->id, error);
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goto close_io;
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}
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/* Prepare descriptor of the QBMan software portal. */
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sc->swp_desc.dpio_dev = dev;
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sc->swp_desc.swp_version = sc->attr.swp_version;
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sc->swp_desc.swp_clk = sc->attr.swp_clk;
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sc->swp_desc.swp_id = sc->attr.swp_id;
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sc->swp_desc.has_notif = sc->attr.priors_num ? true : false;
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sc->swp_desc.has_8prio = sc->attr.priors_num == 8u ? true : false;
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sc->swp_desc.cena_res = sc->res[0];
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sc->swp_desc.cena_map = &sc->map[0];
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sc->swp_desc.cinh_res = sc->res[1];
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sc->swp_desc.cinh_map = &sc->map[1];
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/*
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* Compute how many 256 QBMAN cycles fit into one ns. This is because
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* the interrupt timeout period register needs to be specified in QBMAN
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* clock cycles in increments of 256.
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*/
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sc->swp_desc.swp_cycles_ratio = 256000 /
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(sc->swp_desc.swp_clk / 1000000);
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/* Initialize QBMan software portal. */
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error = dpaa2_swp_init_portal(&sc->swp, &sc->swp_desc, DPAA2_SWP_DEF);
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if (error) {
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device_printf(dev, "%s: failed to initialize dpaa2_swp: "
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"error=%d\n", __func__, error);
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goto err_exit;
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}
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error = dpaa2_io_setup_irqs(dev);
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if (error) {
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device_printf(dev, "%s: failed to setup IRQs: error=%d\n",
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__func__, error);
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goto err_exit;
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}
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if (bootverbose) {
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device_printf(dev, "dpio_id=%d, swp_id=%d, chan_mode=%s, "
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"notif_priors=%d, swp_version=0x%x\n",
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sc->attr.id, sc->attr.swp_id,
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sc->attr.chan_mode == DPAA2_IO_LOCAL_CHANNEL
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? "local_channel" : "no_channel", sc->attr.priors_num,
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sc->attr.swp_version);
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}
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(void)DPAA2_CMD_IO_CLOSE(dev, child, &cmd);
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(void)DPAA2_CMD_RC_CLOSE(dev, child, DPAA2_CMD_TK(&cmd, rc_token));
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return (0);
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close_io:
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(void)DPAA2_CMD_IO_CLOSE(dev, child, DPAA2_CMD_TK(&cmd, io_token));
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close_rc:
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(void)DPAA2_CMD_RC_CLOSE(dev, child, DPAA2_CMD_TK(&cmd, rc_token));
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err_exit:
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dpaa2_io_detach(dev);
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return (ENXIO);
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}
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/**
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* @brief Enqueue multiple frames to a frame queue using one FQID.
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*/
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static int
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dpaa2_io_enq_multiple_fq(device_t iodev, uint32_t fqid,
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struct dpaa2_fd *fd, int frames_n)
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{
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struct dpaa2_io_softc *sc = device_get_softc(iodev);
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struct dpaa2_swp *swp = sc->swp;
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struct dpaa2_eq_desc ed;
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uint32_t flags = 0;
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memset(&ed, 0, sizeof(ed));
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/* Setup enqueue descriptor. */
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dpaa2_swp_set_ed_norp(&ed, false);
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dpaa2_swp_set_ed_fq(&ed, fqid);
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return (dpaa2_swp_enq_mult(swp, &ed, fd, &flags, frames_n));
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}
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/**
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* @brief Configure the channel data availability notification (CDAN)
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* in a particular WQ channel paired with DPIO.
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*/
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static int
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dpaa2_io_conf_wq_channel(device_t iodev, struct dpaa2_io_notif_ctx *ctx)
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{
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struct dpaa2_io_softc *sc = device_get_softc(iodev);
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/* Enable generation of the CDAN notifications. */
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if (ctx->cdan_en) {
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return (dpaa2_swp_conf_wq_channel(sc->swp, ctx->fq_chan_id,
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DPAA2_WQCHAN_WE_EN | DPAA2_WQCHAN_WE_CTX, ctx->cdan_en,
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ctx->qman_ctx));
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}
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return (0);
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}
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/**
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* @brief Query current configuration/state of the buffer pool.
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*/
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static int
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dpaa2_io_query_bp(device_t iodev, uint16_t bpid, struct dpaa2_bp_conf *conf)
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{
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struct dpaa2_io_softc *sc = device_get_softc(iodev);
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return (dpaa2_swp_query_bp(sc->swp, bpid, conf));
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}
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/**
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* @brief Release one or more buffer pointers to the QBMan buffer pool.
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*/
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static int
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dpaa2_io_release_bufs(device_t iodev, uint16_t bpid, bus_addr_t *buf,
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uint32_t buf_num)
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{
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struct dpaa2_io_softc *sc = device_get_softc(iodev);
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return (dpaa2_swp_release_bufs(sc->swp, bpid, buf, buf_num));
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}
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/**
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* @brief Configure DPNI object to generate interrupts.
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*/
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static int
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dpaa2_io_setup_irqs(device_t dev)
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{
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struct dpaa2_io_softc *sc = device_get_softc(dev);
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int error;
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/*
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* Setup interrupts generated by the software portal.
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*/
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dpaa2_swp_set_intr_trigger(sc->swp, DPAA2_SWP_INTR_DQRI);
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dpaa2_swp_clear_intr_status(sc->swp, 0xFFFFFFFFu);
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/* Configure IRQs. */
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error = dpaa2_io_setup_msi(sc);
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if (error) {
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device_printf(dev, "%s: failed to allocate MSI: error=%d\n",
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__func__, error);
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return (error);
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}
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if ((sc->irq_resource = bus_alloc_resource_any(dev, SYS_RES_IRQ,
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&sc->irq_rid[0], RF_ACTIVE | RF_SHAREABLE)) == NULL) {
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device_printf(dev, "%s: failed to allocate IRQ resource\n",
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__func__);
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return (ENXIO);
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}
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if (bus_setup_intr(dev, sc->irq_resource, INTR_TYPE_NET | INTR_MPSAFE |
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INTR_ENTROPY, NULL, dpaa2_io_intr, sc, &sc->intr)) {
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device_printf(dev, "%s: failed to setup IRQ resource\n",
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__func__);
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return (ENXIO);
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}
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/* Wrap DPIO ID around number of CPUs/RSS buckets */
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||
#ifdef RSS
|
||
sc->cpu = rss_getcpu(sc->attr.id % rss_getnumbuckets());
|
||
#else
|
||
sc->cpu = sc->attr.id % mp_ncpus;
|
||
#endif
|
||
CPU_SETOF(sc->cpu, &sc->cpu_mask);
|
||
bus_bind_intr(dev, sc->irq_resource, sc->cpu);
|
||
|
||
/*
|
||
* Setup and enable Static Dequeue Command to receive CDANs from
|
||
* channel 0.
|
||
*/
|
||
if (sc->swp_desc.has_notif)
|
||
dpaa2_swp_set_push_dequeue(sc->swp, 0, true);
|
||
|
||
return (0);
|
||
}
|
||
|
||
static int
|
||
dpaa2_io_release_irqs(device_t dev)
|
||
{
|
||
struct dpaa2_io_softc *sc = device_get_softc(dev);
|
||
|
||
/* Disable receiving CDANs from channel 0. */
|
||
if (sc->swp_desc.has_notif)
|
||
dpaa2_swp_set_push_dequeue(sc->swp, 0, false);
|
||
|
||
/* Release IRQ resources. */
|
||
if (sc->intr != NULL)
|
||
bus_teardown_intr(dev, sc->irq_resource, &sc->intr);
|
||
if (sc->irq_resource != NULL)
|
||
bus_release_resource(dev, SYS_RES_IRQ, sc->irq_rid[0],
|
||
sc->irq_resource);
|
||
|
||
(void)dpaa2_io_release_msi(device_get_softc(dev));
|
||
|
||
/* Configure software portal to stop generating interrupts. */
|
||
dpaa2_swp_set_intr_trigger(sc->swp, 0);
|
||
dpaa2_swp_clear_intr_status(sc->swp, 0xFFFFFFFFu);
|
||
|
||
return (0);
|
||
}
|
||
|
||
/**
|
||
* @brief Allocate MSI interrupts for this DPAA2 I/O object.
|
||
*/
|
||
static int
|
||
dpaa2_io_setup_msi(struct dpaa2_io_softc *sc)
|
||
{
|
||
int val;
|
||
|
||
val = pci_msi_count(sc->dev);
|
||
if (val < DPAA2_IO_MSI_COUNT)
|
||
device_printf(sc->dev, "MSI: actual=%d, expected=%d\n", val,
|
||
DPAA2_IO_MSI_COUNT);
|
||
val = MIN(val, DPAA2_IO_MSI_COUNT);
|
||
|
||
if (pci_alloc_msi(sc->dev, &val) != 0)
|
||
return (EINVAL);
|
||
|
||
for (int i = 0; i < val; i++)
|
||
sc->irq_rid[i] = i + 1;
|
||
|
||
return (0);
|
||
}
|
||
|
||
static int
|
||
dpaa2_io_release_msi(struct dpaa2_io_softc *sc)
|
||
{
|
||
int error;
|
||
|
||
error = pci_release_msi(sc->dev);
|
||
if (error) {
|
||
device_printf(sc->dev, "%s: failed to release MSI: error=%d/n",
|
||
__func__, error);
|
||
return (error);
|
||
}
|
||
|
||
return (0);
|
||
}
|
||
|
||
/**
|
||
* @brief DPAA2 I/O interrupt handler.
|
||
*/
|
||
static void
|
||
dpaa2_io_intr(void *arg)
|
||
{
|
||
struct dpaa2_io_softc *sc = (struct dpaa2_io_softc *) arg;
|
||
/* struct dpaa2_ni_softc *nisc = NULL; */
|
||
struct dpaa2_io_notif_ctx *ctx[DPIO_POLL_MAX];
|
||
struct dpaa2_channel *chan;
|
||
struct dpaa2_dq dq;
|
||
uint32_t idx, status;
|
||
uint16_t flags;
|
||
int rc, cdan_n = 0;
|
||
|
||
status = dpaa2_swp_read_intr_status(sc->swp);
|
||
if (status == 0) {
|
||
return;
|
||
}
|
||
|
||
DPAA2_SWP_LOCK(sc->swp, &flags);
|
||
if (flags & DPAA2_SWP_DESTROYED) {
|
||
/* Terminate operation if portal is destroyed. */
|
||
DPAA2_SWP_UNLOCK(sc->swp);
|
||
return;
|
||
}
|
||
|
||
for (int i = 0; i < DPIO_POLL_MAX; i++) {
|
||
rc = dpaa2_swp_dqrr_next_locked(sc->swp, &dq, &idx);
|
||
if (rc) {
|
||
break;
|
||
}
|
||
|
||
if ((dq.common.verb & DPAA2_DQRR_RESULT_MASK) ==
|
||
DPAA2_DQRR_RESULT_CDAN) {
|
||
ctx[cdan_n++] = (struct dpaa2_io_notif_ctx *) dq.scn.ctx;
|
||
} else {
|
||
/* TODO: Report unknown DQRR entry. */
|
||
}
|
||
dpaa2_swp_write_reg(sc->swp, DPAA2_SWP_CINH_DCAP, idx);
|
||
}
|
||
DPAA2_SWP_UNLOCK(sc->swp);
|
||
|
||
for (int i = 0; i < cdan_n; i++) {
|
||
chan = (struct dpaa2_channel *)ctx[i]->channel;
|
||
/* nisc = device_get_softc(chan->ni_dev); */
|
||
taskqueue_enqueue(chan->cleanup_tq, &chan->cleanup_task);
|
||
}
|
||
|
||
/* Enable software portal interrupts back */
|
||
dpaa2_swp_clear_intr_status(sc->swp, status);
|
||
dpaa2_swp_write_reg(sc->swp, DPAA2_SWP_CINH_IIR, 0);
|
||
}
|
||
|
||
static device_method_t dpaa2_io_methods[] = {
|
||
/* Device interface */
|
||
DEVMETHOD(device_probe, dpaa2_io_probe),
|
||
DEVMETHOD(device_attach, dpaa2_io_attach),
|
||
DEVMETHOD(device_detach, dpaa2_io_detach),
|
||
|
||
/* QBMan software portal interface */
|
||
DEVMETHOD(dpaa2_swp_enq_multiple_fq, dpaa2_io_enq_multiple_fq),
|
||
DEVMETHOD(dpaa2_swp_conf_wq_channel, dpaa2_io_conf_wq_channel),
|
||
DEVMETHOD(dpaa2_swp_query_bp, dpaa2_io_query_bp),
|
||
DEVMETHOD(dpaa2_swp_release_bufs, dpaa2_io_release_bufs),
|
||
|
||
DEVMETHOD_END
|
||
};
|
||
|
||
static driver_t dpaa2_io_driver = {
|
||
"dpaa2_io",
|
||
dpaa2_io_methods,
|
||
sizeof(struct dpaa2_io_softc),
|
||
};
|
||
|
||
DRIVER_MODULE(dpaa2_io, dpaa2_rc, dpaa2_io_driver, 0, 0);
|