Each channel gets its own DMA resources, cleanup and "bufferpool" tasks, and a separate cleanup taskqueue to isolate channels operation as much as possible to avoid various kernel panics under heavy network load. As a side-effect of this work, dpaa2_buf structure is simplified and all of the functions to re-seed those buffers are gathered now in dpaa2_buf.h and .c files; functions to work with channels are extracted into dpaa2_channel.h and .c files as well. Reported by: dch Reviewed by: bz Approved by: bz (mentor) MFC after: 1 week Differential Revision: https://reviews.freebsd.org/D41296
533 lines
17 KiB
C
533 lines
17 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright © 2021-2023 Dmitry Salychev
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#ifndef _DPAA2_SWP_H
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#define _DPAA2_SWP_H
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include "dpaa2_types.h"
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#include "dpaa2_buf.h"
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#include "dpaa2_bp.h"
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/*
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* DPAA2 QBMan software portal.
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*/
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/* All QBMan commands and result structures use this "valid bit" encoding. */
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#define DPAA2_SWP_VALID_BIT ((uint32_t) 0x80)
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#define DPAA2_SWP_TIMEOUT 100000 /* in us */
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#define DPAA2_SWP_CMD_PARAMS_N 8u
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#define DPAA2_SWP_RSP_PARAMS_N 8u
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/*
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* Maximum number of buffers that can be acquired/released through a single
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* QBMan command.
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*/
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#define DPAA2_SWP_BUFS_PER_CMD 7u
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/*
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* Number of times to retry DPIO portal operations while waiting for portal to
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* finish executing current command and become available.
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*
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* We want to avoid being stuck in a while loop in case hardware becomes
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* unresponsive, but not give up too easily if the portal really is busy for
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* valid reasons.
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*/
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#define DPAA2_SWP_BUSY_RETRIES 1000
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/* Versions of the QBMan software portals. */
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#define DPAA2_SWP_REV_4000 0x04000000
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#define DPAA2_SWP_REV_4100 0x04010000
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#define DPAA2_SWP_REV_4101 0x04010001
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#define DPAA2_SWP_REV_5000 0x05000000
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#define DPAA2_SWP_REV_MASK 0xFFFF0000
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/* Registers in the cache-inhibited area of the software portal. */
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#define DPAA2_SWP_CINH_CR 0x600 /* Management Command reg.*/
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#define DPAA2_SWP_CINH_EQCR_PI 0x800 /* Enqueue Ring, Producer Index */
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#define DPAA2_SWP_CINH_EQCR_CI 0x840 /* Enqueue Ring, Consumer Index */
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#define DPAA2_SWP_CINH_CR_RT 0x900 /* CR Read Trigger */
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#define DPAA2_SWP_CINH_VDQCR_RT 0x940 /* VDQCR Read Trigger */
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#define DPAA2_SWP_CINH_EQCR_AM_RT 0x980
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#define DPAA2_SWP_CINH_RCR_AM_RT 0x9C0
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#define DPAA2_SWP_CINH_DQPI 0xA00 /* DQRR Producer Index reg. */
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#define DPAA2_SWP_CINH_DQRR_ITR 0xA80 /* DQRR interrupt timeout reg. */
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#define DPAA2_SWP_CINH_DCAP 0xAC0 /* DQRR Consumption Ack. reg. */
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#define DPAA2_SWP_CINH_SDQCR 0xB00 /* Static Dequeue Command reg. */
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#define DPAA2_SWP_CINH_EQCR_AM_RT2 0xB40
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#define DPAA2_SWP_CINH_RCR_PI 0xC00 /* Release Ring, Producer Index */
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#define DPAA2_SWP_CINH_RAR 0xCC0 /* Release Array Allocation reg. */
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#define DPAA2_SWP_CINH_CFG 0xD00
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#define DPAA2_SWP_CINH_ISR 0xE00
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#define DPAA2_SWP_CINH_IER 0xE40
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#define DPAA2_SWP_CINH_ISDR 0xE80
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#define DPAA2_SWP_CINH_IIR 0xEC0
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#define DPAA2_SWP_CINH_ITPR 0xF40
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/* Registers in the cache-enabled area of the software portal. */
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#define DPAA2_SWP_CENA_EQCR(n) (0x000 + ((uint32_t)(n) << 6))
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#define DPAA2_SWP_CENA_DQRR(n) (0x200 + ((uint32_t)(n) << 6))
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#define DPAA2_SWP_CENA_RCR(n) (0x400 + ((uint32_t)(n) << 6))
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#define DPAA2_SWP_CENA_CR (0x600) /* Management Command reg. */
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#define DPAA2_SWP_CENA_RR(vb) (0x700 + ((uint32_t)(vb) >> 1))
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#define DPAA2_SWP_CENA_VDQCR (0x780)
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#define DPAA2_SWP_CENA_EQCR_CI (0x840)
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/* Registers in the cache-enabled area of the software portal (memory-backed). */
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#define DPAA2_SWP_CENA_DQRR_MEM(n) (0x0800 + ((uint32_t)(n) << 6))
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#define DPAA2_SWP_CENA_RCR_MEM(n) (0x1400 + ((uint32_t)(n) << 6))
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#define DPAA2_SWP_CENA_CR_MEM (0x1600) /* Management Command reg. */
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#define DPAA2_SWP_CENA_RR_MEM (0x1680) /* Management Response reg. */
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#define DPAA2_SWP_CENA_VDQCR_MEM (0x1780)
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#define DPAA2_SWP_CENA_EQCR_CI_MEMBACK (0x1840)
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/* Shifts in the portal's configuration register. */
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#define DPAA2_SWP_CFG_DQRR_MF_SHIFT 20
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#define DPAA2_SWP_CFG_EST_SHIFT 16
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#define DPAA2_SWP_CFG_CPBS_SHIFT 15
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#define DPAA2_SWP_CFG_WN_SHIFT 14
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#define DPAA2_SWP_CFG_RPM_SHIFT 12
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#define DPAA2_SWP_CFG_DCM_SHIFT 10
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#define DPAA2_SWP_CFG_EPM_SHIFT 8
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#define DPAA2_SWP_CFG_VPM_SHIFT 7
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#define DPAA2_SWP_CFG_CPM_SHIFT 6
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#define DPAA2_SWP_CFG_SD_SHIFT 5
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#define DPAA2_SWP_CFG_SP_SHIFT 4
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#define DPAA2_SWP_CFG_SE_SHIFT 3
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#define DPAA2_SWP_CFG_DP_SHIFT 2
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#define DPAA2_SWP_CFG_DE_SHIFT 1
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#define DPAA2_SWP_CFG_EP_SHIFT 0
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/* Static Dequeue Command Register attribute codes */
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#define DPAA2_SDQCR_FC_SHIFT 29 /* Dequeue Command Frame Count */
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#define DPAA2_SDQCR_FC_MASK 0x1
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#define DPAA2_SDQCR_DCT_SHIFT 24 /* Dequeue Command Type */
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#define DPAA2_SDQCR_DCT_MASK 0x3
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#define DPAA2_SDQCR_TOK_SHIFT 16 /* Dequeue Command Token */
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#define DPAA2_SDQCR_TOK_MASK 0xff
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#define DPAA2_SDQCR_SRC_SHIFT 0 /* Dequeue Source */
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#define DPAA2_SDQCR_SRC_MASK 0xffff
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/*
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* Read trigger bit is used to trigger QMan to read a command from memory,
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* without having software perform a cache flush to force a write of the command
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* to QMan.
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*
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* NOTE: Implemented in QBMan 5.0 or above.
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*/
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#define DPAA2_SWP_RT_MODE ((uint32_t)0x100)
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/* Interrupt Enable Register bits. */
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#define DPAA2_SWP_INTR_EQRI 0x01
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#define DPAA2_SWP_INTR_EQDI 0x02
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#define DPAA2_SWP_INTR_DQRI 0x04
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#define DPAA2_SWP_INTR_RCRI 0x08
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#define DPAA2_SWP_INTR_RCDI 0x10
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#define DPAA2_SWP_INTR_VDCI 0x20
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/* "Write Enable" bitmask for a command to configure SWP WQ Channel.*/
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#define DPAA2_WQCHAN_WE_EN (0x1u) /* Enable CDAN generation */
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#define DPAA2_WQCHAN_WE_ICD (0x2u) /* Interrupt Coalescing Disable */
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#define DPAA2_WQCHAN_WE_CTX (0x4u)
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/* Definitions for parsing DQRR entries. */
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#define DPAA2_DQRR_RESULT_MASK (0x7Fu)
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#define DPAA2_DQRR_RESULT_DQ (0x60u)
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#define DPAA2_DQRR_RESULT_FQRN (0x21u)
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#define DPAA2_DQRR_RESULT_FQRNI (0x22u)
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#define DPAA2_DQRR_RESULT_FQPN (0x24u)
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#define DPAA2_DQRR_RESULT_FQDAN (0x25u)
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#define DPAA2_DQRR_RESULT_CDAN (0x26u)
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#define DPAA2_DQRR_RESULT_CSCN_MEM (0x27u)
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#define DPAA2_DQRR_RESULT_CGCU (0x28u)
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#define DPAA2_DQRR_RESULT_BPSCN (0x29u)
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#define DPAA2_DQRR_RESULT_CSCN_WQ (0x2au)
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/* Frame dequeue statuses */
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#define DPAA2_DQ_STAT_FQEMPTY (0x80u) /* FQ is empty */
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#define DPAA2_DQ_STAT_HELDACTIVE (0x40u) /* FQ is held active */
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#define DPAA2_DQ_STAT_FORCEELIGIBLE (0x20u) /* FQ force eligible */
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#define DPAA2_DQ_STAT_VALIDFRAME (0x10u) /* valid frame */
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#define DPAA2_DQ_STAT_ODPVALID (0x04u) /* FQ ODP enable */
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#define DPAA2_DQ_STAT_VOLATILE (0x02u) /* volatile dequeue (VDC) */
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#define DPAA2_DQ_STAT_EXPIRED (0x01u) /* VDC is expired */
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/*
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* Portal flags.
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*
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* TODO: Use the same flags for both MC and software portals.
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*/
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#define DPAA2_SWP_DEF 0x0u
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#define DPAA2_SWP_NOWAIT_ALLOC 0x2u /* Do not sleep during init */
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#define DPAA2_SWP_LOCKED 0x4000u /* Wait till portal's unlocked */
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#define DPAA2_SWP_DESTROYED 0x8000u /* Terminate any operations */
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/* Command return codes. */
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#define DPAA2_SWP_STAT_OK 0x0
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#define DPAA2_SWP_STAT_NO_MEMORY 0x9 /* No memory available */
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#define DPAA2_SWP_STAT_PORTAL_DISABLED 0xFD /* QBMan portal disabled */
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#define DPAA2_SWP_STAT_EINVAL 0xFE /* Invalid argument */
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#define DPAA2_SWP_STAT_ERR 0xFF /* General error */
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#define DPAA2_EQ_DESC_SIZE 32u /* Enqueue Command Descriptor */
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#define DPAA2_FDR_DESC_SIZE 32u /* Descriptor of the FDR */
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#define DPAA2_FD_SIZE 32u /* Frame Descriptor */
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#define DPAA2_FDR_SIZE 64u /* Frame Dequeue Response */
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#define DPAA2_SCN_SIZE 16u /* State Change Notification */
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#define DPAA2_FA_SIZE 64u /* SW Frame Annotation */
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#define DPAA2_SGE_SIZE 16u /* S/G table entry */
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#define DPAA2_DQ_SIZE 64u /* Dequeue Response */
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#define DPAA2_SWP_CMD_SIZE 64u /* SWP Command */
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#define DPAA2_SWP_RSP_SIZE 64u /* SWP Command Response */
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/* Opaque token for static dequeues. */
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#define DPAA2_SWP_SDQCR_TOKEN 0xBBu
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/* Opaque token for static dequeues. */
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#define DPAA2_SWP_VDQCR_TOKEN 0xCCu
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#define DPAA2_SWP_LOCK(__swp, __flags) do { \
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mtx_assert(&(__swp)->lock, MA_NOTOWNED); \
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mtx_lock(&(__swp)->lock); \
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*(__flags) = (__swp)->flags; \
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(__swp)->flags |= DPAA2_SWP_LOCKED; \
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} while (0)
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#define DPAA2_SWP_UNLOCK(__swp) do { \
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mtx_assert(&(__swp)->lock, MA_OWNED); \
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(__swp)->flags &= ~DPAA2_SWP_LOCKED; \
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mtx_unlock(&(__swp)->lock); \
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} while (0)
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enum dpaa2_fd_format {
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DPAA2_FD_SINGLE = 0,
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DPAA2_FD_LIST,
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DPAA2_FD_SG
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};
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/**
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* @brief Enqueue command descriptor.
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*/
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struct dpaa2_eq_desc {
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uint8_t verb;
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uint8_t dca;
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uint16_t seqnum;
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uint16_t orpid;
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uint16_t _reserved;
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uint32_t tgtid;
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uint32_t tag;
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uint16_t qdbin;
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uint8_t qpri;
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uint8_t _reserved1[3];
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uint8_t wae;
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uint8_t rspid;
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uint64_t rsp_addr;
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} __packed;
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CTASSERT(sizeof(struct dpaa2_eq_desc) == DPAA2_EQ_DESC_SIZE);
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/**
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* @brief Frame Dequeue Response (FDR) descriptor.
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*/
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struct dpaa2_fdr_desc {
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uint8_t verb;
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uint8_t stat;
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uint16_t seqnum;
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uint16_t oprid;
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uint8_t _reserved;
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uint8_t tok;
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uint32_t fqid;
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uint32_t _reserved1;
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uint32_t fq_byte_cnt;
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uint32_t fq_frm_cnt;
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uint64_t fqd_ctx;
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} __packed;
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CTASSERT(sizeof(struct dpaa2_fdr_desc) == DPAA2_FDR_DESC_SIZE);
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/**
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* @brief State Change Notification Message (SCNM).
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*/
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struct dpaa2_scn {
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uint8_t verb;
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uint8_t stat;
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uint8_t state;
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uint8_t _reserved;
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uint32_t rid_tok;
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uint64_t ctx;
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} __packed;
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CTASSERT(sizeof(struct dpaa2_scn) == DPAA2_SCN_SIZE);
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/**
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* @brief DPAA2 frame descriptor.
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*
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* addr: Memory address of the start of the buffer holding the
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* frame data or the buffer containing the scatter/gather
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* list.
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* data_length: Length of the frame data (in bytes).
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* bpid_ivp_bmt: Buffer pool ID (14 bit + BMT bit + IVP bit)
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* offset_fmt_sl: Frame data offset, frame format and short-length fields.
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* frame_ctx: Frame context. This field allows the sender of a frame
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* to communicate some out-of-band information to the
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* receiver of the frame.
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* ctrl: Control bits (ERR, CBMT, ASAL, PTAC, DROPP, SC, DD).
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* flow_ctx: Frame flow context. Associates the frame with a flow
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* structure. QMan may use the FLC field for 3 purposes:
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* stashing control, order definition point identification,
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* and enqueue replication control.
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*/
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struct dpaa2_fd {
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uint64_t addr;
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uint32_t data_length;
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uint16_t bpid_ivp_bmt;
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uint16_t offset_fmt_sl;
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uint32_t frame_ctx;
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uint32_t ctrl;
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uint64_t flow_ctx;
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} __packed;
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CTASSERT(sizeof(struct dpaa2_fd) == DPAA2_FD_SIZE);
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/**
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* @brief DPAA2 frame annotation.
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*/
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struct dpaa2_fa {
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uint32_t magic;
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struct dpaa2_buf *buf;
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#ifdef __notyet__
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union {
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struct { /* Tx frame annotation */
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struct dpaa2_ni_tx_ring *tx;
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};
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struct { /* Rx frame annotation */
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uint64_t _notused;
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};
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};
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#endif
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} __packed;
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CTASSERT(sizeof(struct dpaa2_fa) <= DPAA2_FA_SIZE);
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/**
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* @brief DPAA2 scatter/gather entry.
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*/
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struct dpaa2_sg_entry {
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uint64_t addr;
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uint32_t len;
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uint16_t bpid;
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uint16_t offset_fmt;
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} __packed;
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CTASSERT(sizeof(struct dpaa2_sg_entry) == DPAA2_SGE_SIZE);
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/**
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* @brief Frame Dequeue Response (FDR).
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*/
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struct dpaa2_fdr {
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struct dpaa2_fdr_desc desc;
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struct dpaa2_fd fd;
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} __packed;
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CTASSERT(sizeof(struct dpaa2_fdr) == DPAA2_FDR_SIZE);
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/**
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* @brief Dequeue Response Message.
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*/
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struct dpaa2_dq {
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union {
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struct {
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uint8_t verb;
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uint8_t _reserved[63];
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} common;
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struct dpaa2_fdr fdr; /* Frame Dequeue Response */
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struct dpaa2_scn scn; /* State Change Notification */
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};
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} __packed;
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CTASSERT(sizeof(struct dpaa2_dq) == DPAA2_DQ_SIZE);
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/**
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* @brief Descriptor of the QBMan software portal.
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*
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* cena_res: Unmapped cache-enabled part of the portal's I/O memory.
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* cena_map: Mapped cache-enabled part of the portal's I/O memory.
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* cinh_res: Unmapped cache-inhibited part of the portal's I/O memory.
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* cinh_map: Mapped cache-inhibited part of the portal's I/O memory.
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*
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* dpio_dev: Device associated with the DPIO object to manage this
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* portal.
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* swp_version: Hardware IP version of the software portal.
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* swp_clk: QBMAN clock frequency value in Hz.
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* swp_cycles_ratio: How many 256 QBMAN cycles fit into one ns.
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* swp_id: Software portal ID.
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*
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* has_notif: True if the notification mode is used.
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* has_8prio: True for a channel with 8 priority WQs. Ignored unless
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* "has_notif" is true.
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*/
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struct dpaa2_swp_desc {
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struct resource *cena_res;
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struct resource_map *cena_map;
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struct resource *cinh_res;
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struct resource_map *cinh_map;
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device_t dpio_dev;
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uint32_t swp_version;
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uint32_t swp_clk;
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uint32_t swp_cycles_ratio;
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uint16_t swp_id;
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bool has_notif;
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bool has_8prio;
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};
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/**
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* @brief Command holds data to be written to the software portal.
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*/
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struct dpaa2_swp_cmd {
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uint64_t params[DPAA2_SWP_CMD_PARAMS_N];
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};
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CTASSERT(sizeof(struct dpaa2_swp_cmd) == DPAA2_SWP_CMD_SIZE);
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/**
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* @brief Command response holds data received from the software portal.
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|
*/
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|
struct dpaa2_swp_rsp {
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uint64_t params[DPAA2_SWP_RSP_PARAMS_N];
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};
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CTASSERT(sizeof(struct dpaa2_swp_rsp) == DPAA2_SWP_RSP_SIZE);
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|
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/**
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* @brief QBMan software portal.
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*
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* res: Unmapped cache-enabled and cache-inhibited parts of the portal.
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* map: Mapped cache-enabled and cache-inhibited parts of the portal.
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* desc: Descriptor of the QBMan software portal.
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* lock: Lock to guard an access to the portal.
|
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* cv: Conditional variable helps to wait for the helper object's state
|
|
* change.
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* flags: Current state of the object.
|
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* sdq: Push dequeues status.
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* mc: Management commands data.
|
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* mr: Management response data.
|
|
* dqrr: Dequeue Response Ring is used to issue frame dequeue responses
|
|
* from the QBMan to the driver.
|
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* eqcr: Enqueue Command Ring is used to issue frame enqueue commands
|
|
* from the driver to the QBMan.
|
|
*/
|
|
struct dpaa2_swp {
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struct resource *cena_res;
|
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struct resource_map *cena_map;
|
|
struct resource *cinh_res;
|
|
struct resource_map *cinh_map;
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|
|
|
struct mtx lock;
|
|
struct dpaa2_swp_desc *desc;
|
|
uint16_t flags;
|
|
|
|
/* Static Dequeue Command Register value (to obtain CDANs). */
|
|
uint32_t sdq;
|
|
|
|
/* Volatile Dequeue Command (to obtain frames). */
|
|
struct {
|
|
uint32_t valid_bit; /* 0x00 or 0x80 */
|
|
} vdq;
|
|
|
|
struct {
|
|
bool atomic;
|
|
bool writes_cinh;
|
|
bool mem_backed;
|
|
} cfg; /* Software portal configuration. */
|
|
|
|
struct {
|
|
uint32_t valid_bit; /* 0x00 or 0x80 */
|
|
} mc;
|
|
|
|
struct {
|
|
uint32_t valid_bit; /* 0x00 or 0x80 */
|
|
} mr;
|
|
|
|
struct {
|
|
uint32_t next_idx;
|
|
uint32_t valid_bit;
|
|
uint8_t ring_size;
|
|
bool reset_bug; /* dqrr reset workaround */
|
|
uint32_t irq_threshold;
|
|
uint32_t irq_itp;
|
|
} dqrr;
|
|
|
|
struct {
|
|
uint32_t pi; /* producer index */
|
|
uint32_t pi_vb; /* PI valid bits */
|
|
uint32_t pi_ring_size;
|
|
uint32_t pi_ci_mask;
|
|
uint32_t ci;
|
|
int available;
|
|
uint32_t pend;
|
|
uint32_t no_pfdr;
|
|
} eqcr;
|
|
};
|
|
|
|
/* Management routines. */
|
|
int dpaa2_swp_init_portal(struct dpaa2_swp **swp, struct dpaa2_swp_desc *desc,
|
|
uint16_t flags);
|
|
void dpaa2_swp_free_portal(struct dpaa2_swp *swp);
|
|
uint32_t dpaa2_swp_set_cfg(uint8_t max_fill, uint8_t wn, uint8_t est,
|
|
uint8_t rpm, uint8_t dcm, uint8_t epm, int sd, int sp, int se, int dp,
|
|
int de, int ep);
|
|
|
|
/* Read/write registers of a software portal. */
|
|
void dpaa2_swp_write_reg(struct dpaa2_swp *swp, uint32_t o, uint32_t v);
|
|
uint32_t dpaa2_swp_read_reg(struct dpaa2_swp *swp, uint32_t o);
|
|
|
|
/* Helper routines. */
|
|
void dpaa2_swp_set_ed_norp(struct dpaa2_eq_desc *ed, bool resp_always);
|
|
void dpaa2_swp_set_ed_fq(struct dpaa2_eq_desc *ed, uint32_t fqid);
|
|
void dpaa2_swp_set_intr_trigger(struct dpaa2_swp *swp, uint32_t mask);
|
|
uint32_t dpaa2_swp_get_intr_trigger(struct dpaa2_swp *swp);
|
|
uint32_t dpaa2_swp_read_intr_status(struct dpaa2_swp *swp);
|
|
void dpaa2_swp_clear_intr_status(struct dpaa2_swp *swp, uint32_t mask);
|
|
void dpaa2_swp_set_push_dequeue(struct dpaa2_swp *swp, uint8_t chan_idx,
|
|
bool en);
|
|
int dpaa2_swp_set_irq_coalescing(struct dpaa2_swp *swp, uint32_t threshold,
|
|
uint32_t holdoff);
|
|
|
|
/* Software portal commands. */
|
|
int dpaa2_swp_conf_wq_channel(struct dpaa2_swp *swp, uint16_t chan_id,
|
|
uint8_t we_mask, bool cdan_en, uint64_t ctx);
|
|
int dpaa2_swp_query_bp(struct dpaa2_swp *swp, uint16_t bpid,
|
|
struct dpaa2_bp_conf *conf);
|
|
int dpaa2_swp_release_bufs(struct dpaa2_swp *swp, uint16_t bpid, bus_addr_t *buf,
|
|
uint32_t buf_num);
|
|
int dpaa2_swp_dqrr_next_locked(struct dpaa2_swp *swp, struct dpaa2_dq *dq,
|
|
uint32_t *idx);
|
|
int dpaa2_swp_pull(struct dpaa2_swp *swp, uint16_t chan_id,
|
|
struct dpaa2_buf *buf, uint32_t frames_n);
|
|
int dpaa2_swp_enq(struct dpaa2_swp *swp, struct dpaa2_eq_desc *ed,
|
|
struct dpaa2_fd *fd);
|
|
int dpaa2_swp_enq_mult(struct dpaa2_swp *swp, struct dpaa2_eq_desc *ed,
|
|
struct dpaa2_fd *fd, uint32_t *flags, int frames_n);
|
|
|
|
#endif /* _DPAA2_SWP_H */
|