1105 lines
30 KiB
C
1105 lines
30 KiB
C
/******************************************************************************
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Copyright (c) 2013-2020, Intel Corporation
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice,
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this list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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3. Neither the name of the Intel Corporation nor the names of its
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contributors may be used to endorse or promote products derived from
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this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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POSSIBILITY OF SUCH DAMAGE.
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******************************************************************************/
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#include "ixl_pf.h"
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void
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ixl_configure_tx_itr(struct ixl_pf *pf)
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{
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struct i40e_hw *hw = &pf->hw;
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struct ixl_vsi *vsi = &pf->vsi;
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struct ixl_tx_queue *que = vsi->tx_queues;
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vsi->tx_itr_setting = pf->tx_itr;
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for (int i = 0; i < vsi->num_tx_queues; i++, que++) {
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struct tx_ring *txr = &que->txr;
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wr32(hw, I40E_PFINT_ITRN(IXL_TX_ITR, i),
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vsi->tx_itr_setting);
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txr->itr = vsi->tx_itr_setting;
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txr->latency = IXL_AVE_LATENCY;
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}
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}
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void
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ixl_configure_rx_itr(struct ixl_pf *pf)
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{
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struct i40e_hw *hw = &pf->hw;
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struct ixl_vsi *vsi = &pf->vsi;
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struct ixl_rx_queue *que = vsi->rx_queues;
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vsi->rx_itr_setting = pf->rx_itr;
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for (int i = 0; i < vsi->num_rx_queues; i++, que++) {
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struct rx_ring *rxr = &que->rxr;
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wr32(hw, I40E_PFINT_ITRN(IXL_RX_ITR, i),
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vsi->rx_itr_setting);
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rxr->itr = vsi->rx_itr_setting;
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rxr->latency = IXL_AVE_LATENCY;
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}
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}
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int
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ixl_intr(void *arg)
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{
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struct ixl_pf *pf = arg;
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struct i40e_hw *hw = &pf->hw;
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struct ixl_vsi *vsi = &pf->vsi;
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struct ixl_rx_queue *que = vsi->rx_queues;
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u32 icr0;
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++que->irqs;
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/* Clear PBA at start of ISR if using legacy interrupts */
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if (vsi->shared->isc_intr == IFLIB_INTR_LEGACY)
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wr32(hw, I40E_PFINT_DYN_CTL0,
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I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
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(IXL_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT));
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icr0 = rd32(hw, I40E_PFINT_ICR0);
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#ifdef PCI_IOV
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if (icr0 & I40E_PFINT_ICR0_VFLR_MASK)
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iflib_iov_intr_deferred(vsi->ctx);
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#endif
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if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK)
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iflib_admin_intr_deferred(vsi->ctx);
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ixl_enable_intr0(hw);
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if (icr0 & I40E_PFINT_ICR0_QUEUE_0_MASK)
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return (FILTER_SCHEDULE_THREAD);
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else
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return (FILTER_HANDLED);
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}
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/*********************************************************************
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*
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* MSI-X VSI Interrupt Service routine
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*
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**********************************************************************/
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int
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ixl_msix_que(void *arg)
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{
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struct ixl_rx_queue *rx_que = arg;
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++rx_que->irqs;
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ixl_set_queue_rx_itr(rx_que);
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return (FILTER_SCHEDULE_THREAD);
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}
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/*********************************************************************
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*
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* MSI-X Admin Queue Interrupt Service routine
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*
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**********************************************************************/
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int
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ixl_msix_adminq(void *arg)
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{
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struct ixl_pf *pf = arg;
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struct i40e_hw *hw = &pf->hw;
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device_t dev = pf->dev;
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u32 reg, mask, rstat_reg;
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bool do_task = FALSE;
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DDPRINTF(dev, "begin");
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++pf->admin_irq;
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reg = rd32(hw, I40E_PFINT_ICR0);
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/*
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* For masking off interrupt causes that need to be handled before
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* they can be re-enabled
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*/
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mask = rd32(hw, I40E_PFINT_ICR0_ENA);
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/* Check on the cause */
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if (reg & I40E_PFINT_ICR0_ADMINQ_MASK) {
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mask &= ~I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
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do_task = TRUE;
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}
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if (reg & I40E_PFINT_ICR0_MAL_DETECT_MASK) {
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mask &= ~I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK;
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ixl_set_state(&pf->state, IXL_STATE_MDD_PENDING);
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do_task = TRUE;
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}
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if (reg & I40E_PFINT_ICR0_GRST_MASK) {
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const char *reset_type;
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mask &= ~I40E_PFINT_ICR0_ENA_GRST_MASK;
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rstat_reg = rd32(hw, I40E_GLGEN_RSTAT);
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rstat_reg = (rstat_reg & I40E_GLGEN_RSTAT_RESET_TYPE_MASK)
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>> I40E_GLGEN_RSTAT_RESET_TYPE_SHIFT;
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switch (rstat_reg) {
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/* These others might be handled similarly to an EMPR reset */
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case I40E_RESET_CORER:
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reset_type = "CORER";
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break;
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case I40E_RESET_GLOBR:
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reset_type = "GLOBR";
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break;
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case I40E_RESET_EMPR:
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reset_type = "EMPR";
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break;
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default:
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reset_type = "POR";
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break;
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}
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device_printf(dev, "Reset Requested! (%s)\n", reset_type);
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/* overload admin queue task to check reset progress */
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ixl_set_state(&pf->state, IXL_STATE_RESETTING);
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do_task = TRUE;
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}
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/*
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* PE / PCI / ECC exceptions are all handled in the same way:
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* mask out these three causes, then request a PF reset
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*/
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if (reg & I40E_PFINT_ICR0_ECC_ERR_MASK)
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device_printf(dev, "ECC Error detected!\n");
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if (reg & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
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device_printf(dev, "PCI Exception detected!\n");
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if (reg & I40E_PFINT_ICR0_PE_CRITERR_MASK)
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device_printf(dev, "Critical Protocol Engine Error detected!\n");
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/* Checks against the conditions above */
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if (reg & IXL_ICR0_CRIT_ERR_MASK) {
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mask &= ~IXL_ICR0_CRIT_ERR_MASK;
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ixl_set_state(&pf->state,
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IXL_STATE_PF_RESET_REQ | IXL_STATE_PF_CRIT_ERR);
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do_task = TRUE;
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}
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if (reg & I40E_PFINT_ICR0_HMC_ERR_MASK) {
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reg = rd32(hw, I40E_PFHMC_ERRORINFO);
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if (reg & I40E_PFHMC_ERRORINFO_ERROR_DETECTED_MASK) {
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device_printf(dev, "HMC Error detected!\n");
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device_printf(dev, "INFO 0x%08x\n", reg);
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reg = rd32(hw, I40E_PFHMC_ERRORDATA);
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device_printf(dev, "DATA 0x%08x\n", reg);
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wr32(hw, I40E_PFHMC_ERRORINFO, 0);
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}
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}
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#ifdef PCI_IOV
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if (reg & I40E_PFINT_ICR0_VFLR_MASK) {
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mask &= ~I40E_PFINT_ICR0_ENA_VFLR_MASK;
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iflib_iov_intr_deferred(pf->vsi.ctx);
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}
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#endif
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wr32(hw, I40E_PFINT_ICR0_ENA, mask);
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ixl_enable_intr0(hw);
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if (do_task)
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return (FILTER_SCHEDULE_THREAD);
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else
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return (FILTER_HANDLED);
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}
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/*
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* Configure queue interrupt cause registers in hardware.
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*
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* Linked list for each vector LNKLSTN(i) -> RQCTL(i) -> TQCTL(i) -> EOL
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*/
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void
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ixl_configure_queue_intr_msix(struct ixl_pf *pf)
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{
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struct i40e_hw *hw = &pf->hw;
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struct ixl_vsi *vsi = &pf->vsi;
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u32 reg;
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u16 vector = 1;
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for (int i = 0; i < max(vsi->num_rx_queues, vsi->num_tx_queues); i++, vector++) {
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/* Make sure interrupt is disabled */
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wr32(hw, I40E_PFINT_DYN_CTLN(i), 0);
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/* Set linked list head to point to corresponding RX queue
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* e.g. vector 1 (LNKLSTN register 0) points to queue pair 0's RX queue */
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reg = ((i << I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT)
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& I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK) |
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((I40E_QUEUE_TYPE_RX << I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT)
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& I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_MASK);
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wr32(hw, I40E_PFINT_LNKLSTN(i), reg);
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reg = I40E_QINT_RQCTL_CAUSE_ENA_MASK |
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(IXL_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) |
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(vector << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
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(i << I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
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(I40E_QUEUE_TYPE_TX << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT);
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wr32(hw, I40E_QINT_RQCTL(i), reg);
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reg = I40E_QINT_TQCTL_CAUSE_ENA_MASK |
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(IXL_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) |
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(vector << I40E_QINT_TQCTL_MSIX_INDX_SHIFT) |
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(IXL_QUEUE_EOL << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT) |
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(I40E_QUEUE_TYPE_RX << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT);
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wr32(hw, I40E_QINT_TQCTL(i), reg);
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}
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}
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/*
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* Configure for single interrupt vector operation
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*/
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void
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ixl_configure_legacy(struct ixl_pf *pf)
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{
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struct i40e_hw *hw = &pf->hw;
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struct ixl_vsi *vsi = &pf->vsi;
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u32 reg;
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vsi->rx_queues[0].rxr.itr = vsi->rx_itr_setting;
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/* Setup "other" causes */
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reg = I40E_PFINT_ICR0_ENA_ECC_ERR_MASK
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| I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK
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| I40E_PFINT_ICR0_ENA_GRST_MASK
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| I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK
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| I40E_PFINT_ICR0_ENA_HMC_ERR_MASK
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| I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK
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| I40E_PFINT_ICR0_ENA_VFLR_MASK
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| I40E_PFINT_ICR0_ENA_ADMINQ_MASK
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;
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wr32(hw, I40E_PFINT_ICR0_ENA, reg);
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/* No ITR for non-queue interrupts */
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wr32(hw, I40E_PFINT_STAT_CTL0,
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IXL_ITR_NONE << I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_SHIFT);
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/* FIRSTQ_INDX = 0, FIRSTQ_TYPE = 0 (rx) */
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wr32(hw, I40E_PFINT_LNKLST0, 0);
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/* Associate the queue pair to the vector and enable the q int */
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reg = I40E_QINT_RQCTL_CAUSE_ENA_MASK
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| (IXL_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT)
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| (I40E_QUEUE_TYPE_TX << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT);
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wr32(hw, I40E_QINT_RQCTL(0), reg);
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reg = I40E_QINT_TQCTL_CAUSE_ENA_MASK
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| (IXL_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT)
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| (IXL_QUEUE_EOL << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT);
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wr32(hw, I40E_QINT_TQCTL(0), reg);
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}
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void
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ixl_free_pci_resources(struct ixl_pf *pf)
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{
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struct ixl_vsi *vsi = &pf->vsi;
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device_t dev = iflib_get_dev(vsi->ctx);
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struct ixl_rx_queue *rx_que = vsi->rx_queues;
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/* We may get here before stations are set up */
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if (rx_que == NULL)
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goto early;
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/*
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** Release all MSI-X VSI resources:
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*/
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iflib_irq_free(vsi->ctx, &vsi->irq);
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for (int i = 0; i < vsi->num_rx_queues; i++, rx_que++)
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iflib_irq_free(vsi->ctx, &rx_que->que_irq);
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early:
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if (pf->pci_mem != NULL)
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bus_release_resource(dev, SYS_RES_MEMORY,
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rman_get_rid(pf->pci_mem), pf->pci_mem);
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}
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/*********************************************************************
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*
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* Setup networking device structure and register an interface.
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*
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**********************************************************************/
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int
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ixl_setup_interface(device_t dev, struct ixl_pf *pf)
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{
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struct ixl_vsi *vsi = &pf->vsi;
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if_ctx_t ctx = vsi->ctx;
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struct i40e_hw *hw = &pf->hw;
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if_t ifp = iflib_get_ifp(ctx);
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struct i40e_aq_get_phy_abilities_resp abilities;
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enum i40e_status_code aq_error = 0;
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INIT_DBG_DEV(dev, "begin");
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vsi->shared->isc_max_frame_size =
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if_getmtu(ifp) + ETHER_HDR_LEN + ETHER_CRC_LEN
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+ ETHER_VLAN_ENCAP_LEN;
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if (IXL_PF_IN_RECOVERY_MODE(pf))
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goto only_auto;
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aq_error = i40e_aq_get_phy_capabilities(hw,
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FALSE, TRUE, &abilities, NULL);
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/* May need delay to detect fiber correctly */
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if (aq_error == I40E_ERR_UNKNOWN_PHY) {
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i40e_msec_delay(200);
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aq_error = i40e_aq_get_phy_capabilities(hw, FALSE,
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TRUE, &abilities, NULL);
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}
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if (aq_error) {
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if (aq_error == I40E_ERR_UNKNOWN_PHY)
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device_printf(dev, "Unknown PHY type detected!\n");
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else
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device_printf(dev,
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"Error getting supported media types, err %d,"
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" AQ error %d\n", aq_error, hw->aq.asq_last_status);
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} else {
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pf->supported_speeds = abilities.link_speed;
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if_setbaudrate(ifp, ixl_max_aq_speed_to_value(pf->supported_speeds));
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ixl_add_ifmedia(vsi->media, hw->phy.phy_types);
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}
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only_auto:
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/* Use autoselect media by default */
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ifmedia_add(vsi->media, IFM_ETHER | IFM_AUTO, 0, NULL);
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ifmedia_set(vsi->media, IFM_ETHER | IFM_AUTO);
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return (0);
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}
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/*
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** Run when the Admin Queue gets a link state change interrupt.
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*/
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void
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ixl_link_event(struct ixl_pf *pf, struct i40e_arq_event_info *e)
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{
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struct i40e_hw *hw = &pf->hw;
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device_t dev = iflib_get_dev(pf->vsi.ctx);
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struct i40e_link_status *link_info = &hw->phy.link_info;
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/* Driver needs to re-enable delivering of link status events
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* by FW after each event reception. Call i40e_get_link_status
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* to do that. To not lose information about link state changes,
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* which happened between receiving an event and the call,
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* do not rely on status from event but use most recent
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* status information retrieved by the call. */
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hw->phy.get_link_info = TRUE;
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i40e_get_link_status(hw, &pf->link_up);
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/* Print out message if an unqualified module is found */
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if ((link_info->link_info & I40E_AQ_MEDIA_AVAILABLE) &&
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(pf->advertised_speed) &&
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(if_getflags(pf->vsi.ifp) & IFF_UP) &&
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(!(link_info->an_info & I40E_AQ_QUALIFIED_MODULE)) &&
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(!(link_info->link_info & I40E_AQ_LINK_UP)))
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device_printf(dev, "Link failed because "
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"an unqualified module was detected!\n");
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/* OS link info is updated elsewhere */
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}
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|
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/*********************************************************************
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*
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* Initialize the VSI: this handles contexts, which means things
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* like the number of descriptors, buffer size,
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* plus we init the rings thru this function.
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*
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**********************************************************************/
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int
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ixl_initialize_vsi(struct ixl_vsi *vsi)
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{
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struct ixl_pf *pf = vsi->back;
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if_softc_ctx_t scctx = iflib_get_softc_ctx(vsi->ctx);
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struct ixl_tx_queue *tx_que = vsi->tx_queues;
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struct ixl_rx_queue *rx_que = vsi->rx_queues;
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device_t dev = iflib_get_dev(vsi->ctx);
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struct i40e_hw *hw = vsi->hw;
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struct i40e_vsi_context ctxt;
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int tc_queues;
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int err = 0;
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memset(&ctxt, 0, sizeof(ctxt));
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ctxt.seid = vsi->seid;
|
|
if (pf->veb_seid != 0)
|
|
ctxt.uplink_seid = pf->veb_seid;
|
|
ctxt.pf_num = hw->pf_id;
|
|
err = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
|
|
if (err) {
|
|
device_printf(dev, "i40e_aq_get_vsi_params() failed, error %d"
|
|
" aq_error %d\n", err, hw->aq.asq_last_status);
|
|
return (err);
|
|
}
|
|
ixl_dbg(pf, IXL_DBG_SWITCH_INFO,
|
|
"get_vsi_params: seid: %d, uplinkseid: %d, vsi_number: %d, "
|
|
"vsis_allocated: %d, vsis_unallocated: %d, flags: 0x%x, "
|
|
"pfnum: %d, vfnum: %d, stat idx: %d, enabled: %d\n", ctxt.seid,
|
|
ctxt.uplink_seid, ctxt.vsi_number,
|
|
ctxt.vsis_allocated, ctxt.vsis_unallocated,
|
|
ctxt.flags, ctxt.pf_num, ctxt.vf_num,
|
|
ctxt.info.stat_counter_idx, ctxt.info.up_enable_bits);
|
|
/*
|
|
** Set the queue and traffic class bits
|
|
** - when multiple traffic classes are supported
|
|
** this will need to be more robust.
|
|
*/
|
|
ctxt.info.valid_sections = I40E_AQ_VSI_PROP_QUEUE_MAP_VALID;
|
|
ctxt.info.mapping_flags |= I40E_AQ_VSI_QUE_MAP_CONTIG;
|
|
/* In contig mode, que_mapping[0] is first queue index used by this VSI */
|
|
ctxt.info.queue_mapping[0] = 0;
|
|
/*
|
|
* This VSI will only use traffic class 0; start traffic class 0's
|
|
* queue allocation at queue 0, and assign it 2^tc_queues queues (though
|
|
* the driver may not use all of them).
|
|
*/
|
|
tc_queues = fls(pf->qtag.num_allocated) - 1;
|
|
ctxt.info.tc_mapping[0] = ((pf->qtag.first_qidx << I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT)
|
|
& I40E_AQ_VSI_TC_QUE_OFFSET_MASK) |
|
|
((tc_queues << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT)
|
|
& I40E_AQ_VSI_TC_QUE_NUMBER_MASK);
|
|
|
|
/* Set VLAN receive stripping mode */
|
|
ctxt.info.valid_sections |= I40E_AQ_VSI_PROP_VLAN_VALID;
|
|
ctxt.info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL;
|
|
if (if_getcapenable(vsi->ifp) & IFCAP_VLAN_HWTAGGING)
|
|
ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
|
|
else
|
|
ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
|
|
|
|
#ifdef IXL_IW
|
|
/* Set TCP Enable for iWARP capable VSI */
|
|
if (ixl_enable_iwarp && pf->iw_enabled) {
|
|
ctxt.info.valid_sections |=
|
|
htole16(I40E_AQ_VSI_PROP_QUEUE_OPT_VALID);
|
|
ctxt.info.queueing_opt_flags |= I40E_AQ_VSI_QUE_OPT_TCP_ENA;
|
|
}
|
|
#endif
|
|
/* Save VSI number and info for use later */
|
|
vsi->vsi_num = ctxt.vsi_number;
|
|
bcopy(&ctxt.info, &vsi->info, sizeof(vsi->info));
|
|
|
|
ctxt.flags = htole16(I40E_AQ_VSI_TYPE_PF);
|
|
|
|
err = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
|
|
if (err) {
|
|
device_printf(dev, "i40e_aq_update_vsi_params() failed, error %d,"
|
|
" aq_error %d\n", err, hw->aq.asq_last_status);
|
|
return (err);
|
|
}
|
|
|
|
for (int i = 0; i < vsi->num_tx_queues; i++, tx_que++) {
|
|
struct tx_ring *txr = &tx_que->txr;
|
|
struct i40e_hmc_obj_txq tctx;
|
|
u32 txctl;
|
|
|
|
/* Setup the HMC TX Context */
|
|
bzero(&tctx, sizeof(tctx));
|
|
tctx.new_context = 1;
|
|
tctx.base = (txr->tx_paddr/IXL_TX_CTX_BASE_UNITS);
|
|
tctx.qlen = scctx->isc_ntxd[0];
|
|
tctx.fc_ena = 0; /* Disable FCoE */
|
|
/*
|
|
* This value needs to pulled from the VSI that this queue
|
|
* is assigned to. Index into array is traffic class.
|
|
*/
|
|
tctx.rdylist = vsi->info.qs_handle[0];
|
|
/*
|
|
* Set these to enable Head Writeback
|
|
* - Address is last entry in TX ring (reserved for HWB index)
|
|
* Leave these as 0 for Descriptor Writeback
|
|
*/
|
|
if (vsi->enable_head_writeback) {
|
|
tctx.head_wb_ena = 1;
|
|
tctx.head_wb_addr = txr->tx_paddr +
|
|
(scctx->isc_ntxd[0] * sizeof(struct i40e_tx_desc));
|
|
} else {
|
|
tctx.head_wb_ena = 0;
|
|
tctx.head_wb_addr = 0;
|
|
}
|
|
tctx.rdylist_act = 0;
|
|
err = i40e_clear_lan_tx_queue_context(hw, i);
|
|
if (err) {
|
|
device_printf(dev, "Unable to clear TX context\n");
|
|
break;
|
|
}
|
|
err = i40e_set_lan_tx_queue_context(hw, i, &tctx);
|
|
if (err) {
|
|
device_printf(dev, "Unable to set TX context\n");
|
|
break;
|
|
}
|
|
/* Associate the ring with this PF */
|
|
txctl = I40E_QTX_CTL_PF_QUEUE;
|
|
txctl |= ((hw->pf_id << I40E_QTX_CTL_PF_INDX_SHIFT) &
|
|
I40E_QTX_CTL_PF_INDX_MASK);
|
|
wr32(hw, I40E_QTX_CTL(i), txctl);
|
|
ixl_flush(hw);
|
|
|
|
/* Do ring (re)init */
|
|
ixl_init_tx_ring(vsi, tx_que);
|
|
}
|
|
for (int i = 0; i < vsi->num_rx_queues; i++, rx_que++) {
|
|
struct rx_ring *rxr = &rx_que->rxr;
|
|
struct i40e_hmc_obj_rxq rctx;
|
|
|
|
/* Next setup the HMC RX Context */
|
|
rxr->mbuf_sz = iflib_get_rx_mbuf_sz(vsi->ctx);
|
|
|
|
u16 max_rxmax = rxr->mbuf_sz * hw->func_caps.rx_buf_chain_len;
|
|
|
|
/* Set up an RX context for the HMC */
|
|
memset(&rctx, 0, sizeof(struct i40e_hmc_obj_rxq));
|
|
rctx.dbuff = rxr->mbuf_sz >> I40E_RXQ_CTX_DBUFF_SHIFT;
|
|
/* ignore header split for now */
|
|
rctx.hbuff = 0 >> I40E_RXQ_CTX_HBUFF_SHIFT;
|
|
rctx.rxmax = (scctx->isc_max_frame_size < max_rxmax) ?
|
|
scctx->isc_max_frame_size : max_rxmax;
|
|
rctx.dtype = 0;
|
|
rctx.dsize = 1; /* do 32byte descriptors */
|
|
rctx.hsplit_0 = 0; /* no header split */
|
|
rctx.base = (rxr->rx_paddr/IXL_RX_CTX_BASE_UNITS);
|
|
rctx.qlen = scctx->isc_nrxd[0];
|
|
rctx.tphrdesc_ena = 1;
|
|
rctx.tphwdesc_ena = 1;
|
|
rctx.tphdata_ena = 0; /* Header Split related */
|
|
rctx.tphhead_ena = 0; /* Header Split related */
|
|
rctx.lrxqthresh = 1; /* Interrupt at <64 desc avail */
|
|
rctx.crcstrip = 1;
|
|
rctx.l2tsel = 1;
|
|
rctx.showiv = 1; /* Strip inner VLAN header */
|
|
rctx.fc_ena = 0; /* Disable FCoE */
|
|
rctx.prefena = 1; /* Prefetch descriptors */
|
|
|
|
err = i40e_clear_lan_rx_queue_context(hw, i);
|
|
if (err) {
|
|
device_printf(dev,
|
|
"Unable to clear RX context %d\n", i);
|
|
break;
|
|
}
|
|
err = i40e_set_lan_rx_queue_context(hw, i, &rctx);
|
|
if (err) {
|
|
device_printf(dev, "Unable to set RX context %d\n", i);
|
|
break;
|
|
}
|
|
wr32(vsi->hw, I40E_QRX_TAIL(i), 0);
|
|
}
|
|
return (err);
|
|
}
|
|
|
|
|
|
/*
|
|
** Provide a update to the queue RX
|
|
** interrupt moderation value.
|
|
*/
|
|
void
|
|
ixl_set_queue_rx_itr(struct ixl_rx_queue *que)
|
|
{
|
|
struct ixl_vsi *vsi = que->vsi;
|
|
struct ixl_pf *pf = (struct ixl_pf *)vsi->back;
|
|
struct i40e_hw *hw = vsi->hw;
|
|
struct rx_ring *rxr = &que->rxr;
|
|
u16 rx_itr;
|
|
u16 rx_latency = 0;
|
|
int rx_bytes;
|
|
|
|
/* Idle, do nothing */
|
|
if (rxr->bytes == 0)
|
|
return;
|
|
|
|
if (pf->dynamic_rx_itr) {
|
|
rx_bytes = rxr->bytes/rxr->itr;
|
|
rx_itr = rxr->itr;
|
|
|
|
/* Adjust latency range */
|
|
switch (rxr->latency) {
|
|
case IXL_LOW_LATENCY:
|
|
if (rx_bytes > 10) {
|
|
rx_latency = IXL_AVE_LATENCY;
|
|
rx_itr = IXL_ITR_20K;
|
|
}
|
|
break;
|
|
case IXL_AVE_LATENCY:
|
|
if (rx_bytes > 20) {
|
|
rx_latency = IXL_BULK_LATENCY;
|
|
rx_itr = IXL_ITR_8K;
|
|
} else if (rx_bytes <= 10) {
|
|
rx_latency = IXL_LOW_LATENCY;
|
|
rx_itr = IXL_ITR_100K;
|
|
}
|
|
break;
|
|
case IXL_BULK_LATENCY:
|
|
if (rx_bytes <= 20) {
|
|
rx_latency = IXL_AVE_LATENCY;
|
|
rx_itr = IXL_ITR_20K;
|
|
}
|
|
break;
|
|
}
|
|
|
|
rxr->latency = rx_latency;
|
|
|
|
if (rx_itr != rxr->itr) {
|
|
/* do an exponential smoothing */
|
|
rx_itr = (10 * rx_itr * rxr->itr) /
|
|
((9 * rx_itr) + rxr->itr);
|
|
rxr->itr = min(rx_itr, IXL_MAX_ITR);
|
|
wr32(hw, I40E_PFINT_ITRN(IXL_RX_ITR,
|
|
rxr->me), rxr->itr);
|
|
}
|
|
} else { /* We may have have toggled to non-dynamic */
|
|
if (vsi->rx_itr_setting & IXL_ITR_DYNAMIC)
|
|
vsi->rx_itr_setting = pf->rx_itr;
|
|
/* Update the hardware if needed */
|
|
if (rxr->itr != vsi->rx_itr_setting) {
|
|
rxr->itr = vsi->rx_itr_setting;
|
|
wr32(hw, I40E_PFINT_ITRN(IXL_RX_ITR,
|
|
rxr->me), rxr->itr);
|
|
}
|
|
}
|
|
rxr->bytes = 0;
|
|
rxr->packets = 0;
|
|
}
|
|
|
|
|
|
/*
|
|
** Provide a update to the queue TX
|
|
** interrupt moderation value.
|
|
*/
|
|
void
|
|
ixl_set_queue_tx_itr(struct ixl_tx_queue *que)
|
|
{
|
|
struct ixl_vsi *vsi = que->vsi;
|
|
struct ixl_pf *pf = (struct ixl_pf *)vsi->back;
|
|
struct i40e_hw *hw = vsi->hw;
|
|
struct tx_ring *txr = &que->txr;
|
|
u16 tx_itr;
|
|
u16 tx_latency = 0;
|
|
int tx_bytes;
|
|
|
|
|
|
/* Idle, do nothing */
|
|
if (txr->bytes == 0)
|
|
return;
|
|
|
|
if (pf->dynamic_tx_itr) {
|
|
tx_bytes = txr->bytes/txr->itr;
|
|
tx_itr = txr->itr;
|
|
|
|
switch (txr->latency) {
|
|
case IXL_LOW_LATENCY:
|
|
if (tx_bytes > 10) {
|
|
tx_latency = IXL_AVE_LATENCY;
|
|
tx_itr = IXL_ITR_20K;
|
|
}
|
|
break;
|
|
case IXL_AVE_LATENCY:
|
|
if (tx_bytes > 20) {
|
|
tx_latency = IXL_BULK_LATENCY;
|
|
tx_itr = IXL_ITR_8K;
|
|
} else if (tx_bytes <= 10) {
|
|
tx_latency = IXL_LOW_LATENCY;
|
|
tx_itr = IXL_ITR_100K;
|
|
}
|
|
break;
|
|
case IXL_BULK_LATENCY:
|
|
if (tx_bytes <= 20) {
|
|
tx_latency = IXL_AVE_LATENCY;
|
|
tx_itr = IXL_ITR_20K;
|
|
}
|
|
break;
|
|
}
|
|
|
|
txr->latency = tx_latency;
|
|
|
|
if (tx_itr != txr->itr) {
|
|
/* do an exponential smoothing */
|
|
tx_itr = (10 * tx_itr * txr->itr) /
|
|
((9 * tx_itr) + txr->itr);
|
|
txr->itr = min(tx_itr, IXL_MAX_ITR);
|
|
wr32(hw, I40E_PFINT_ITRN(IXL_TX_ITR,
|
|
txr->me), txr->itr);
|
|
}
|
|
|
|
} else { /* We may have have toggled to non-dynamic */
|
|
if (vsi->tx_itr_setting & IXL_ITR_DYNAMIC)
|
|
vsi->tx_itr_setting = pf->tx_itr;
|
|
/* Update the hardware if needed */
|
|
if (txr->itr != vsi->tx_itr_setting) {
|
|
txr->itr = vsi->tx_itr_setting;
|
|
wr32(hw, I40E_PFINT_ITRN(IXL_TX_ITR,
|
|
txr->me), txr->itr);
|
|
}
|
|
}
|
|
txr->bytes = 0;
|
|
txr->packets = 0;
|
|
return;
|
|
}
|
|
|
|
#ifdef IXL_DEBUG
|
|
/**
|
|
* ixl_sysctl_qtx_tail_handler
|
|
* Retrieves I40E_QTX_TAIL value from hardware
|
|
* for a sysctl.
|
|
*/
|
|
int
|
|
ixl_sysctl_qtx_tail_handler(SYSCTL_HANDLER_ARGS)
|
|
{
|
|
struct ixl_tx_queue *tx_que;
|
|
int error;
|
|
u32 val;
|
|
|
|
tx_que = ((struct ixl_tx_queue *)oidp->oid_arg1);
|
|
if (!tx_que) return 0;
|
|
|
|
val = rd32(tx_que->vsi->hw, tx_que->txr.tail);
|
|
error = sysctl_handle_int(oidp, &val, 0, req);
|
|
if (error || !req->newptr)
|
|
return error;
|
|
return (0);
|
|
}
|
|
|
|
/**
|
|
* ixl_sysctl_qrx_tail_handler
|
|
* Retrieves I40E_QRX_TAIL value from hardware
|
|
* for a sysctl.
|
|
*/
|
|
int
|
|
ixl_sysctl_qrx_tail_handler(SYSCTL_HANDLER_ARGS)
|
|
{
|
|
struct ixl_rx_queue *rx_que;
|
|
int error;
|
|
u32 val;
|
|
|
|
rx_que = ((struct ixl_rx_queue *)oidp->oid_arg1);
|
|
if (!rx_que) return 0;
|
|
|
|
val = rd32(rx_que->vsi->hw, rx_que->rxr.tail);
|
|
error = sysctl_handle_int(oidp, &val, 0, req);
|
|
if (error || !req->newptr)
|
|
return error;
|
|
return (0);
|
|
}
|
|
#endif
|
|
|
|
void
|
|
ixl_add_hw_stats(struct ixl_pf *pf)
|
|
{
|
|
struct ixl_vsi *vsi = &pf->vsi;
|
|
device_t dev = iflib_get_dev(vsi->ctx);
|
|
struct i40e_hw_port_stats *pf_stats = &pf->stats;
|
|
|
|
struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(dev);
|
|
struct sysctl_oid *tree = device_get_sysctl_tree(dev);
|
|
struct sysctl_oid_list *child = SYSCTL_CHILDREN(tree);
|
|
|
|
/* Driver statistics */
|
|
SYSCTL_ADD_UQUAD(ctx, child, OID_AUTO, "admin_irq",
|
|
CTLFLAG_RD, &pf->admin_irq,
|
|
"Admin Queue IRQs received");
|
|
|
|
sysctl_ctx_init(&vsi->sysctl_ctx);
|
|
ixl_vsi_add_sysctls(vsi, "pf", true);
|
|
|
|
ixl_add_sysctls_mac_stats(ctx, child, pf_stats);
|
|
}
|
|
|
|
void
|
|
ixl_set_rss_hlut(struct ixl_pf *pf)
|
|
{
|
|
struct i40e_hw *hw = &pf->hw;
|
|
struct ixl_vsi *vsi = &pf->vsi;
|
|
device_t dev = iflib_get_dev(vsi->ctx);
|
|
int i, que_id;
|
|
int lut_entry_width;
|
|
u32 lut = 0;
|
|
enum i40e_status_code status;
|
|
|
|
lut_entry_width = pf->hw.func_caps.rss_table_entry_width;
|
|
|
|
/* Populate the LUT with max no. of queues in round robin fashion */
|
|
u8 hlut_buf[512];
|
|
for (i = 0; i < pf->hw.func_caps.rss_table_size; i++) {
|
|
#ifdef RSS
|
|
/*
|
|
* Fetch the RSS bucket id for the given indirection entry.
|
|
* Cap it at the number of configured buckets (which is
|
|
* num_queues.)
|
|
*/
|
|
que_id = rss_get_indirection_to_bucket(i);
|
|
que_id = que_id % vsi->num_rx_queues;
|
|
#else
|
|
que_id = i % vsi->num_rx_queues;
|
|
#endif
|
|
lut = (que_id & ((0x1 << lut_entry_width) - 1));
|
|
hlut_buf[i] = lut;
|
|
}
|
|
|
|
if (hw->mac.type == I40E_MAC_X722) {
|
|
status = i40e_aq_set_rss_lut(hw, vsi->vsi_num, TRUE, hlut_buf, sizeof(hlut_buf));
|
|
if (status)
|
|
device_printf(dev, "i40e_aq_set_rss_lut status %s, error %s\n",
|
|
i40e_stat_str(hw, status), i40e_aq_str(hw, hw->aq.asq_last_status));
|
|
} else {
|
|
for (i = 0; i < pf->hw.func_caps.rss_table_size >> 2; i++)
|
|
wr32(hw, I40E_PFQF_HLUT(i), ((u32 *)hlut_buf)[i]);
|
|
ixl_flush(hw);
|
|
}
|
|
}
|
|
|
|
/* For PF VSI only */
|
|
int
|
|
ixl_enable_rings(struct ixl_vsi *vsi)
|
|
{
|
|
struct ixl_pf *pf = vsi->back;
|
|
int error = 0;
|
|
|
|
for (int i = 0; i < vsi->num_tx_queues; i++)
|
|
error = ixl_enable_tx_ring(pf, &pf->qtag, i);
|
|
|
|
for (int i = 0; i < vsi->num_rx_queues; i++)
|
|
error = ixl_enable_rx_ring(pf, &pf->qtag, i);
|
|
|
|
return (error);
|
|
}
|
|
|
|
int
|
|
ixl_disable_rings(struct ixl_pf *pf, struct ixl_vsi *vsi, struct ixl_pf_qtag *qtag)
|
|
{
|
|
int error = 0;
|
|
|
|
for (int i = 0; i < vsi->num_tx_queues; i++)
|
|
error = ixl_disable_tx_ring(pf, qtag, i);
|
|
|
|
for (int i = 0; i < vsi->num_rx_queues; i++)
|
|
error = ixl_disable_rx_ring(pf, qtag, i);
|
|
|
|
return (error);
|
|
}
|
|
|
|
void
|
|
ixl_enable_intr(struct ixl_vsi *vsi)
|
|
{
|
|
struct i40e_hw *hw = vsi->hw;
|
|
struct ixl_rx_queue *que = vsi->rx_queues;
|
|
|
|
if (vsi->shared->isc_intr == IFLIB_INTR_MSIX) {
|
|
for (int i = 0; i < vsi->num_rx_queues; i++, que++)
|
|
ixl_enable_queue(hw, que->rxr.me);
|
|
} else
|
|
ixl_enable_intr0(hw);
|
|
}
|
|
|
|
void
|
|
ixl_disable_rings_intr(struct ixl_vsi *vsi)
|
|
{
|
|
struct i40e_hw *hw = vsi->hw;
|
|
struct ixl_rx_queue *que = vsi->rx_queues;
|
|
|
|
for (int i = 0; i < vsi->num_rx_queues; i++, que++)
|
|
ixl_disable_queue(hw, que->rxr.me);
|
|
}
|
|
|
|
int
|
|
ixl_prepare_for_reset(struct ixl_pf *pf, bool is_up)
|
|
{
|
|
struct i40e_hw *hw = &pf->hw;
|
|
device_t dev = pf->dev;
|
|
int error = 0;
|
|
|
|
if (is_up)
|
|
ixl_if_stop(pf->vsi.ctx);
|
|
|
|
ixl_shutdown_hmc(pf);
|
|
|
|
ixl_disable_intr0(hw);
|
|
|
|
error = i40e_shutdown_adminq(hw);
|
|
if (error)
|
|
device_printf(dev,
|
|
"Shutdown Admin queue failed with code %d\n", error);
|
|
|
|
ixl_pf_qmgr_release(&pf->qmgr, &pf->qtag);
|
|
return (error);
|
|
}
|
|
|
|
int
|
|
ixl_rebuild_hw_structs_after_reset(struct ixl_pf *pf, bool is_up)
|
|
{
|
|
struct i40e_hw *hw = &pf->hw;
|
|
struct ixl_vsi *vsi = &pf->vsi;
|
|
device_t dev = pf->dev;
|
|
enum i40e_get_fw_lldp_status_resp lldp_status;
|
|
int error = 0;
|
|
|
|
device_printf(dev, "Rebuilding driver state...\n");
|
|
|
|
/* Setup */
|
|
error = i40e_init_adminq(hw);
|
|
if (error != 0 && error != I40E_ERR_FIRMWARE_API_VERSION) {
|
|
device_printf(dev, "Unable to initialize Admin Queue, error %d\n",
|
|
error);
|
|
goto ixl_rebuild_hw_structs_after_reset_err;
|
|
}
|
|
|
|
if (IXL_PF_IN_RECOVERY_MODE(pf)) {
|
|
/* Keep admin queue interrupts active while driver is loaded */
|
|
if (vsi->shared->isc_intr == IFLIB_INTR_MSIX) {
|
|
ixl_configure_intr0_msix(pf);
|
|
ixl_enable_intr0(hw);
|
|
}
|
|
|
|
return (0);
|
|
}
|
|
|
|
i40e_clear_pxe_mode(hw);
|
|
|
|
error = ixl_get_hw_capabilities(pf);
|
|
if (error) {
|
|
device_printf(dev, "ixl_get_hw_capabilities failed: %d\n", error);
|
|
goto ixl_rebuild_hw_structs_after_reset_err;
|
|
}
|
|
|
|
error = ixl_setup_hmc(pf);
|
|
if (error)
|
|
goto ixl_rebuild_hw_structs_after_reset_err;
|
|
|
|
/* reserve a contiguous allocation for the PF's VSI */
|
|
error = ixl_pf_qmgr_alloc_contiguous(&pf->qmgr, vsi->num_tx_queues, &pf->qtag);
|
|
if (error) {
|
|
device_printf(dev, "Failed to reserve queues for PF LAN VSI, error %d\n",
|
|
error);
|
|
}
|
|
|
|
error = ixl_switch_config(pf);
|
|
if (error) {
|
|
device_printf(dev, "ixl_rebuild_hw_structs_after_reset: ixl_switch_config() failed: %d\n",
|
|
error);
|
|
error = EIO;
|
|
goto ixl_rebuild_hw_structs_after_reset_err;
|
|
}
|
|
|
|
error = i40e_aq_set_phy_int_mask(hw, IXL_DEFAULT_PHY_INT_MASK,
|
|
NULL);
|
|
if (error) {
|
|
device_printf(dev, "init: i40e_aq_set_phy_mask() failed: err %d,"
|
|
" aq_err %d\n", error, hw->aq.asq_last_status);
|
|
error = EIO;
|
|
goto ixl_rebuild_hw_structs_after_reset_err;
|
|
}
|
|
|
|
u8 set_fc_err_mask;
|
|
error = i40e_set_fc(hw, &set_fc_err_mask, true);
|
|
if (error) {
|
|
device_printf(dev, "init: setting link flow control failed; retcode %d,"
|
|
" fc_err_mask 0x%02x\n", error, set_fc_err_mask);
|
|
error = EIO;
|
|
goto ixl_rebuild_hw_structs_after_reset_err;
|
|
}
|
|
|
|
/* Remove default filters reinstalled by FW on reset */
|
|
ixl_del_default_hw_filters(vsi);
|
|
|
|
/* Receive broadcast Ethernet frames */
|
|
i40e_aq_set_vsi_broadcast(&pf->hw, vsi->seid, TRUE, NULL);
|
|
|
|
/* Determine link state */
|
|
ixl_attach_get_link_status(pf);
|
|
|
|
i40e_aq_set_dcb_parameters(hw, TRUE, NULL);
|
|
|
|
/* Query device FW LLDP status */
|
|
if (i40e_get_fw_lldp_status(hw, &lldp_status) == I40E_SUCCESS) {
|
|
if (lldp_status == I40E_GET_FW_LLDP_STATUS_DISABLED) {
|
|
ixl_set_state(&pf->state,
|
|
IXL_STATE_FW_LLDP_DISABLED);
|
|
} else {
|
|
ixl_clear_state(&pf->state,
|
|
IXL_STATE_FW_LLDP_DISABLED);
|
|
}
|
|
}
|
|
|
|
/* Keep admin queue interrupts active while driver is loaded */
|
|
if (vsi->shared->isc_intr == IFLIB_INTR_MSIX) {
|
|
ixl_configure_intr0_msix(pf);
|
|
ixl_enable_intr0(hw);
|
|
}
|
|
|
|
if (is_up) {
|
|
iflib_request_reset(vsi->ctx);
|
|
iflib_admin_intr_deferred(vsi->ctx);
|
|
}
|
|
|
|
device_printf(dev, "Rebuilding driver state done.\n");
|
|
return (0);
|
|
|
|
ixl_rebuild_hw_structs_after_reset_err:
|
|
device_printf(dev, "Reload the driver to recover\n");
|
|
return (error);
|
|
}
|
|
|
|
/*
|
|
** Set flow control using sysctl:
|
|
** 0 - off
|
|
** 1 - rx pause
|
|
** 2 - tx pause
|
|
** 3 - full
|
|
*/
|
|
int
|
|
ixl_sysctl_set_flowcntl(SYSCTL_HANDLER_ARGS)
|
|
{
|
|
struct ixl_pf *pf = (struct ixl_pf *)arg1;
|
|
struct i40e_hw *hw = &pf->hw;
|
|
device_t dev = pf->dev;
|
|
int requested_fc, error = 0;
|
|
enum i40e_status_code aq_error = 0;
|
|
u8 fc_aq_err = 0;
|
|
|
|
/* Get request */
|
|
requested_fc = pf->fc;
|
|
error = sysctl_handle_int(oidp, &requested_fc, 0, req);
|
|
if ((error) || (req->newptr == NULL))
|
|
return (error);
|
|
if (requested_fc < 0 || requested_fc > 3) {
|
|
device_printf(dev,
|
|
"Invalid fc mode; valid modes are 0 through 3\n");
|
|
return (EINVAL);
|
|
}
|
|
|
|
/* Set fc ability for port */
|
|
hw->fc.requested_mode = requested_fc;
|
|
aq_error = i40e_set_fc(hw, &fc_aq_err, TRUE);
|
|
if (aq_error) {
|
|
device_printf(dev,
|
|
"%s: Error setting Flow Control mode %d; fc_err %#x\n",
|
|
__func__, aq_error, fc_aq_err);
|
|
return (EIO);
|
|
}
|
|
pf->fc = requested_fc;
|
|
|
|
return (0);
|
|
}
|