511 lines
13 KiB
C
511 lines
13 KiB
C
/*-
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* Copyright (c) 2015 Ruslan Bukin <br@bsdpad.com>
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* Copyright (c) 2014,2016 The FreeBSD Foundation
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* All rights reserved.
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*
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* This software was developed by Andrew Turner under
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* the sponsorship of the FreeBSD Foundation.
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*
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* This software was developed by Semihalf under
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* the sponsorship of the FreeBSD Foundation.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/* Generic ECAM PCIe driver FDT attachment */
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#include <sys/cdefs.h>
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#include "opt_platform.h"
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/malloc.h>
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#include <sys/module.h>
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#include <sys/rman.h>
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#if defined(INTRNG)
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#include <machine/intr.h>
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#endif
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#include <dev/ofw/openfirm.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include <dev/ofw/ofw_pci.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pcireg.h>
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#include <dev/pci/pcib_private.h>
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#include <dev/pci/pci_host_generic.h>
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#include <dev/pci/pci_host_generic_fdt.h>
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#include <machine/intr.h>
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#include "pcib_if.h"
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#define SPACE_CODE_SHIFT 24
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#define SPACE_CODE_MASK 0x3
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#define SPACE_CODE_IO_SPACE 0x1
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#define PROPS_CELL_SIZE 1
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#define PCI_ADDR_CELL_SIZE 2
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struct pci_ofw_devinfo {
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STAILQ_ENTRY(pci_ofw_devinfo) pci_ofw_link;
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struct ofw_bus_devinfo di_dinfo;
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uint8_t slot;
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uint8_t func;
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uint8_t bus;
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};
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/* Forward prototypes */
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static int generic_pcie_fdt_probe(device_t dev);
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static int parse_pci_mem_ranges(device_t, struct generic_pcie_core_softc *);
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static int generic_pcie_ofw_bus_attach(device_t);
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static const struct ofw_bus_devinfo *generic_pcie_ofw_get_devinfo(device_t,
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device_t);
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static int
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generic_pcie_fdt_probe(device_t dev)
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{
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if (!ofw_bus_status_okay(dev))
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return (ENXIO);
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if (ofw_bus_is_compatible(dev, "pci-host-ecam-generic")) {
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device_set_desc(dev, "Generic PCI host controller");
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return (BUS_PROBE_GENERIC);
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}
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if (ofw_bus_is_compatible(dev, "arm,gem5_pcie")) {
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device_set_desc(dev, "GEM5 PCIe host controller");
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return (BUS_PROBE_DEFAULT);
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}
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return (ENXIO);
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}
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int
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pci_host_generic_setup_fdt(device_t dev)
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{
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struct generic_pcie_fdt_softc *sc;
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phandle_t node;
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int error;
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sc = device_get_softc(dev);
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STAILQ_INIT(&sc->pci_ofw_devlist);
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/* Retrieve 'ranges' property from FDT */
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if (bootverbose)
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device_printf(dev, "parsing FDT for ECAM%d:\n", sc->base.ecam);
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if (parse_pci_mem_ranges(dev, &sc->base))
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return (ENXIO);
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/* Attach OFW bus */
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if (generic_pcie_ofw_bus_attach(dev) != 0)
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return (ENXIO);
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node = ofw_bus_get_node(dev);
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if (sc->base.coherent == 0) {
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sc->base.coherent = OF_hasprop(node, "dma-coherent");
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}
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if (bootverbose)
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device_printf(dev, "Bus is%s cache-coherent\n",
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sc->base.coherent ? "" : " not");
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/* TODO parse FDT bus ranges */
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sc->base.bus_start = 0;
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sc->base.bus_end = 0xFF;
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/*
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* ofw_pcib uses device unit as PCI domain number.
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* Do the same. Some boards have multiple RCs handled
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* by different drivers, this ensures that there are
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* no collisions.
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*/
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sc->base.ecam = device_get_unit(dev);
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error = pci_host_generic_core_attach(dev);
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if (error != 0)
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return (error);
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if (ofw_bus_is_compatible(dev, "marvell,armada8k-pcie-ecam") ||
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ofw_bus_is_compatible(dev, "socionext,synquacer-pcie-ecam") ||
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ofw_bus_is_compatible(dev, "snps,dw-pcie-ecam")) {
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device_set_desc(dev, "Synopsys DesignWare PCIe Controller");
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sc->base.quirks |= PCIE_ECAM_DESIGNWARE_QUIRK;
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}
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ofw_bus_setup_iinfo(node, &sc->pci_iinfo, sizeof(cell_t));
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return (0);
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}
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int
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pci_host_generic_fdt_attach(device_t dev)
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{
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int error;
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error = pci_host_generic_setup_fdt(dev);
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if (error != 0)
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return (error);
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device_add_child(dev, "pci", -1);
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return (bus_generic_attach(dev));
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}
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static int
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parse_pci_mem_ranges(device_t dev, struct generic_pcie_core_softc *sc)
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{
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pcell_t pci_addr_cells, parent_addr_cells;
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pcell_t attributes, size_cells;
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cell_t *base_ranges;
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int nbase_ranges;
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phandle_t node;
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int i, j, k;
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int tuple;
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node = ofw_bus_get_node(dev);
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OF_getencprop(node, "#address-cells", &pci_addr_cells,
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sizeof(pci_addr_cells));
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OF_getencprop(node, "#size-cells", &size_cells,
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sizeof(size_cells));
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OF_getencprop(OF_parent(node), "#address-cells", &parent_addr_cells,
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sizeof(parent_addr_cells));
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if (parent_addr_cells > 2 || pci_addr_cells != 3 || size_cells > 2) {
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device_printf(dev,
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"Unexpected number of address or size cells in FDT\n");
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return (ENXIO);
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}
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nbase_ranges = OF_getproplen(node, "ranges");
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sc->nranges = nbase_ranges / sizeof(cell_t) /
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(parent_addr_cells + pci_addr_cells + size_cells);
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base_ranges = malloc(nbase_ranges, M_DEVBUF, M_WAITOK);
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OF_getencprop(node, "ranges", base_ranges, nbase_ranges);
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for (i = 0, j = 0; i < sc->nranges; i++) {
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attributes = (base_ranges[j++] >> SPACE_CODE_SHIFT) & \
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SPACE_CODE_MASK;
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if (attributes == SPACE_CODE_IO_SPACE) {
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sc->ranges[i].flags |= FLAG_TYPE_IO;
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} else {
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sc->ranges[i].flags |= FLAG_TYPE_MEM;
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}
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sc->ranges[i].pci_base = 0;
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for (k = 0; k < (pci_addr_cells - 1); k++) {
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sc->ranges[i].pci_base <<= 32;
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sc->ranges[i].pci_base |= base_ranges[j++];
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}
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sc->ranges[i].phys_base = 0;
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for (k = 0; k < parent_addr_cells; k++) {
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sc->ranges[i].phys_base <<= 32;
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sc->ranges[i].phys_base |= base_ranges[j++];
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}
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sc->ranges[i].size = 0;
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for (k = 0; k < size_cells; k++) {
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sc->ranges[i].size <<= 32;
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sc->ranges[i].size |= base_ranges[j++];
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}
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}
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for (; i < MAX_RANGES_TUPLES; i++) {
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/* zero-fill remaining tuples to mark empty elements in array */
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sc->ranges[i].pci_base = 0;
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sc->ranges[i].phys_base = 0;
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sc->ranges[i].size = 0;
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}
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if (bootverbose) {
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for (tuple = 0; tuple < MAX_RANGES_TUPLES; tuple++) {
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device_printf(dev,
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"\tPCI addr: 0x%jx, CPU addr: 0x%jx, Size: 0x%jx\n",
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sc->ranges[tuple].pci_base,
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sc->ranges[tuple].phys_base,
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sc->ranges[tuple].size);
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}
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}
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free(base_ranges, M_DEVBUF);
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return (0);
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}
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static int
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generic_pcie_fdt_route_interrupt(device_t bus, device_t dev, int pin)
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{
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struct generic_pcie_fdt_softc *sc;
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struct ofw_pci_register reg;
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uint32_t pintr, mintr[4];
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phandle_t iparent;
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int intrcells;
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sc = device_get_softc(bus);
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pintr = pin;
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bzero(®, sizeof(reg));
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reg.phys_hi = (pci_get_bus(dev) << OFW_PCI_PHYS_HI_BUSSHIFT) |
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(pci_get_slot(dev) << OFW_PCI_PHYS_HI_DEVICESHIFT) |
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(pci_get_function(dev) << OFW_PCI_PHYS_HI_FUNCTIONSHIFT);
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intrcells = ofw_bus_lookup_imap(ofw_bus_get_node(dev),
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&sc->pci_iinfo, ®, sizeof(reg), &pintr, sizeof(pintr),
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mintr, sizeof(mintr), &iparent);
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if (intrcells) {
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pintr = ofw_bus_map_intr(dev, iparent, intrcells, mintr);
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return (pintr);
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}
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device_printf(bus, "could not route pin %d for device %d.%d\n",
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pin, pci_get_slot(dev), pci_get_function(dev));
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return (PCI_INVALID_IRQ);
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}
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static int
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generic_pcie_fdt_alloc_msi(device_t pci, device_t child, int count,
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int maxcount, int *irqs)
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{
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#if defined(INTRNG)
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phandle_t msi_parent;
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int err;
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err = ofw_bus_msimap(ofw_bus_get_node(pci), pci_get_rid(child),
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&msi_parent, NULL);
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if (err != 0)
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return (err);
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return (intr_alloc_msi(pci, child, msi_parent, count, maxcount,
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irqs));
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#else
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return (ENXIO);
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#endif
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}
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static int
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generic_pcie_fdt_release_msi(device_t pci, device_t child, int count, int *irqs)
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{
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#if defined(INTRNG)
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phandle_t msi_parent;
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int err;
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err = ofw_bus_msimap(ofw_bus_get_node(pci), pci_get_rid(child),
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&msi_parent, NULL);
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if (err != 0)
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return (err);
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return (intr_release_msi(pci, child, msi_parent, count, irqs));
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#else
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return (ENXIO);
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#endif
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}
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static int
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generic_pcie_fdt_map_msi(device_t pci, device_t child, int irq, uint64_t *addr,
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uint32_t *data)
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{
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#if defined(INTRNG)
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phandle_t msi_parent;
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int err;
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err = ofw_bus_msimap(ofw_bus_get_node(pci), pci_get_rid(child),
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&msi_parent, NULL);
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if (err != 0)
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return (err);
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return (intr_map_msi(pci, child, msi_parent, irq, addr, data));
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#else
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return (ENXIO);
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#endif
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}
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static int
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generic_pcie_fdt_alloc_msix(device_t pci, device_t child, int *irq)
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{
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#if defined(INTRNG)
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phandle_t msi_parent;
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int err;
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err = ofw_bus_msimap(ofw_bus_get_node(pci), pci_get_rid(child),
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&msi_parent, NULL);
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if (err != 0)
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return (err);
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return (intr_alloc_msix(pci, child, msi_parent, irq));
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#else
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return (ENXIO);
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#endif
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}
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static int
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generic_pcie_fdt_release_msix(device_t pci, device_t child, int irq)
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{
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#if defined(INTRNG)
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phandle_t msi_parent;
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int err;
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err = ofw_bus_msimap(ofw_bus_get_node(pci), pci_get_rid(child),
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&msi_parent, NULL);
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if (err != 0)
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return (err);
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return (intr_release_msix(pci, child, msi_parent, irq));
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#else
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return (ENXIO);
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#endif
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}
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static int
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generic_pcie_get_iommu(device_t pci, device_t child, uintptr_t *id)
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{
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struct pci_id_ofw_iommu *iommu;
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uint32_t iommu_rid;
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uint32_t iommu_xref;
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uint16_t pci_rid;
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phandle_t node;
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int err;
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node = ofw_bus_get_node(pci);
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pci_rid = pci_get_rid(child);
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iommu = (struct pci_id_ofw_iommu *)id;
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err = ofw_bus_iommu_map(node, pci_rid, &iommu_xref, &iommu_rid);
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if (err == 0) {
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iommu->id = iommu_rid;
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iommu->xref = iommu_xref;
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}
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return (err);
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}
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int
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generic_pcie_get_id(device_t pci, device_t child, enum pci_id_type type,
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uintptr_t *id)
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{
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phandle_t node;
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int err;
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uint32_t rid;
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uint16_t pci_rid;
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if (type == PCI_ID_OFW_IOMMU)
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return (generic_pcie_get_iommu(pci, child, id));
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if (type != PCI_ID_MSI)
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return (pcib_get_id(pci, child, type, id));
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node = ofw_bus_get_node(pci);
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pci_rid = pci_get_rid(child);
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err = ofw_bus_msimap(node, pci_rid, NULL, &rid);
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if (err != 0)
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return (err);
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*id = rid;
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return (0);
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}
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static const struct ofw_bus_devinfo *
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generic_pcie_ofw_get_devinfo(device_t bus, device_t child)
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{
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struct generic_pcie_fdt_softc *sc;
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struct pci_ofw_devinfo *di;
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uint8_t slot, func, busno;
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sc = device_get_softc(bus);
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slot = pci_get_slot(child);
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func = pci_get_function(child);
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busno = pci_get_bus(child);
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STAILQ_FOREACH(di, &sc->pci_ofw_devlist, pci_ofw_link)
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if (slot == di->slot && func == di->func && busno == di->bus)
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return (&di->di_dinfo);
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return (NULL);
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}
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/* Helper functions */
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static int
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generic_pcie_ofw_bus_attach(device_t dev)
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{
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struct generic_pcie_fdt_softc *sc;
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struct pci_ofw_devinfo *di;
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phandle_t parent, node;
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pcell_t reg[5];
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ssize_t len;
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sc = device_get_softc(dev);
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parent = ofw_bus_get_node(dev);
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if (parent == 0)
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return (0);
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/* Iterate through all bus subordinates */
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for (node = OF_child(parent); node > 0; node = OF_peer(node)) {
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len = OF_getencprop(node, "reg", reg, sizeof(reg));
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if (len != 5 * sizeof(pcell_t))
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continue;
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/* Allocate and populate devinfo. */
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di = malloc(sizeof(*di), M_DEVBUF, M_WAITOK | M_ZERO);
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if (ofw_bus_gen_setup_devinfo(&di->di_dinfo, node) != 0) {
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free(di, M_DEVBUF);
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continue;
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}
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di->func = OFW_PCI_PHYS_HI_FUNCTION(reg[0]);
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di->slot = OFW_PCI_PHYS_HI_DEVICE(reg[0]);
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di->bus = OFW_PCI_PHYS_HI_BUS(reg[0]);
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STAILQ_INSERT_TAIL(&sc->pci_ofw_devlist, di, pci_ofw_link);
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}
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return (0);
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}
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static device_method_t generic_pcie_fdt_methods[] = {
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DEVMETHOD(device_probe, generic_pcie_fdt_probe),
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DEVMETHOD(device_attach, pci_host_generic_fdt_attach),
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DEVMETHOD(bus_alloc_resource, pci_host_generic_core_alloc_resource),
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DEVMETHOD(bus_release_resource, pci_host_generic_core_release_resource),
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/* pcib interface */
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DEVMETHOD(pcib_route_interrupt, generic_pcie_fdt_route_interrupt),
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DEVMETHOD(pcib_alloc_msi, generic_pcie_fdt_alloc_msi),
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DEVMETHOD(pcib_release_msi, generic_pcie_fdt_release_msi),
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DEVMETHOD(pcib_alloc_msix, generic_pcie_fdt_alloc_msix),
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DEVMETHOD(pcib_release_msix, generic_pcie_fdt_release_msix),
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DEVMETHOD(pcib_map_msi, generic_pcie_fdt_map_msi),
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DEVMETHOD(pcib_get_id, generic_pcie_get_id),
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DEVMETHOD(pcib_request_feature, pcib_request_feature_allow),
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DEVMETHOD(ofw_bus_get_devinfo, generic_pcie_ofw_get_devinfo),
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DEVMETHOD(ofw_bus_get_compat, ofw_bus_gen_get_compat),
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DEVMETHOD(ofw_bus_get_model, ofw_bus_gen_get_model),
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DEVMETHOD(ofw_bus_get_name, ofw_bus_gen_get_name),
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DEVMETHOD(ofw_bus_get_node, ofw_bus_gen_get_node),
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DEVMETHOD(ofw_bus_get_type, ofw_bus_gen_get_type),
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DEVMETHOD_END
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};
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DEFINE_CLASS_1(pcib, generic_pcie_fdt_driver, generic_pcie_fdt_methods,
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sizeof(struct generic_pcie_fdt_softc), generic_pcie_core_driver);
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DRIVER_MODULE(pcib, simplebus, generic_pcie_fdt_driver, 0, 0);
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DRIVER_MODULE(pcib, ofwbus, generic_pcie_fdt_driver, 0, 0);
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