283 lines
7.4 KiB
C
283 lines
7.4 KiB
C
/*-
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* Copyright (c) 2021 Adrian Chadd <adrian@FreeBSD.org>.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/lock.h>
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#include <sys/mutex.h>
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#include <sys/rman.h>
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#include <machine/bus.h>
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#include <dev/extres/clk/clk.h>
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#include <dev/extres/clk/clk_div.h>
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#include <dev/extres/clk/clk_fixed.h>
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#include <dev/extres/clk/clk_mux.h>
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#include "qcom_clk_freqtbl.h"
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#include "qcom_clk_apssdiv.h"
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#include "clkdev_if.h"
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/*
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* This is a combination gate, divisor/PLL configuration
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* for the APSS CPU clock.
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*/
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#if 0
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#define DPRINTF(dev, msg...) device_printf(dev, "cpufreq_dt: " msg);
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#else
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#define DPRINTF(dev, msg...)
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#endif
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struct qcom_clk_apssdiv_sc {
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struct clknode *clknode;
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uint32_t div_offset;
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uint32_t div_width;
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uint32_t div_shift;
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uint32_t enable_offset;
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uint32_t enable_shift;
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const struct qcom_clk_freq_tbl *freq_tbl;
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};
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static uint64_t
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qcom_clk_apssdiv_calc_rate(struct clknode *clk, uint64_t freq, uint32_t cdiv)
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{
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uint32_t pre_div;
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/*
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* The divisor isn't a linear map with a linear pre-divisor.
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*/
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if (cdiv > 10) {
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pre_div = (cdiv + 1) * 2;
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} else {
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pre_div = cdiv + 12;
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}
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/*
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* Multiplier is a fixed "2" here.
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*/
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return (freq * 2L) / pre_div;
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}
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static int
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qcom_clk_apssdiv_recalc(struct clknode *clk, uint64_t *freq)
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{
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struct qcom_clk_apssdiv_sc *sc;
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uint32_t reg, cdiv;
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sc = clknode_get_softc(clk);
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if (freq == NULL || *freq == 0) {
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printf("%s: called; NULL or 0 frequency\n", __func__);
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return (ENXIO);
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}
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CLKDEV_DEVICE_LOCK(clknode_get_device(sc->clknode));
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CLKDEV_READ_4(clknode_get_device(sc->clknode), sc->div_offset, ®);
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CLKDEV_DEVICE_UNLOCK(clknode_get_device(sc->clknode));
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cdiv = (reg >> sc->div_shift) & ((1U << sc->div_width) - 1);
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DPRINTF(clknode_get_device(sc->clknode),
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"%s: called; cdiv=0x%x, freq=%llu\n", __func__, cdiv, *freq);
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*freq = qcom_clk_apssdiv_calc_rate(clk, *freq, cdiv);
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DPRINTF(clknode_get_device(sc->clknode),
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"%s: called; freq is %llu\n", __func__, *freq);
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return (0);
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}
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#if 0
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static bool
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qcom_clk_apssdiv_get_gate_locked(struct qcom_clk_apssdiv_sc *sc)
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{
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uint32_t reg;
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if (sc->enable_offset == 0)
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return (false);
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CLKDEV_READ_4(clknode_get_device(sc->clknode), sc->enable_offset,
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®);
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return (!! (reg & (1U << sc->enable_shift)));
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}
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#endif
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static int
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qcom_clk_apssdiv_init(struct clknode *clk, device_t dev)
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{
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/*
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* There's only a single parent here for an fixed divisor,
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* so just set it to 0; the caller doesn't need to supply it.
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*
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* Note that the freqtbl entries have an upstream clock,
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* but the APSS div/gate only has a single upstream and we
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* don't program anything else specific in here.
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*/
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clknode_init_parent_idx(clk, 0);
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return (0);
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}
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static int
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qcom_clk_apssdiv_set_gate(struct clknode *clk, bool enable)
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{
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struct qcom_clk_apssdiv_sc *sc;
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uint32_t reg;
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sc = clknode_get_softc(clk);
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if (sc->enable_offset == 0) {
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return (ENXIO);
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}
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DPRINTF(clknode_get_device(sc->clknode),
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"%s: called; enable=%d\n", __func__, enable);
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CLKDEV_DEVICE_LOCK(clknode_get_device(sc->clknode));
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CLKDEV_READ_4(clknode_get_device(sc->clknode), sc->enable_offset,
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®);
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if (enable) {
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reg |= (1U << sc->enable_shift);
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} else {
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reg &= ~(1U << sc->enable_shift);
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}
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CLKDEV_WRITE_4(clknode_get_device(sc->clknode), sc->enable_offset,
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reg);
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CLKDEV_DEVICE_UNLOCK(clknode_get_device(sc->clknode));
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return (0);
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}
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/*
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* Set frequency
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*
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* fin - the parent frequency, if exists
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* fout - starts as the requested frequency, ends with the configured
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* or dry-run frequency
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* Flags - CLK_SET_DRYRUN, CLK_SET_ROUND_UP, CLK_SET_ROUND_DOWN
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* retval - 0, ERANGE
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*/
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static int
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qcom_clk_apssdiv_set_freq(struct clknode *clk, uint64_t fin, uint64_t *fout,
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int flags, int *stop)
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{
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const struct qcom_clk_freq_tbl *f;
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struct qcom_clk_apssdiv_sc *sc;
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uint64_t f_freq;
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uint32_t reg;
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sc = clknode_get_softc(clk);
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/* There are no further PLLs to set in this chain */
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*stop = 1;
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/* Search the table for a suitable frequency */
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f = qcom_clk_freq_tbl_lookup(sc->freq_tbl, *fout);
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if (f == NULL) {
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return (ERANGE);
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}
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/*
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* Calculate what the resultant frequency would be based on the
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* parent PLL.
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*/
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f_freq = qcom_clk_apssdiv_calc_rate(clk, fin, f->pre_div);
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DPRINTF(clknode_get_device(sc->clknode),
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"%s: dryrun: %d, fin=%llu fout=%llu f_freq=%llu pre_div=%u"
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" target_freq=%llu\n",
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__func__,
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!! (flags & CLK_SET_DRYRUN),
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fin, *fout, f_freq, f->pre_div, f->freq);
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if (flags & CLK_SET_DRYRUN) {
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*fout = f_freq;
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return (0);
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}
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/*
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* Program in the new pre-divisor.
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*/
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CLKDEV_DEVICE_LOCK(clknode_get_device(sc->clknode));
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CLKDEV_READ_4(clknode_get_device(sc->clknode), sc->div_offset, ®);
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reg &= ~(((1U << sc->div_width) - 1) << sc->div_shift);
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reg |= (f->pre_div << sc->div_shift);
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CLKDEV_WRITE_4(clknode_get_device(sc->clknode), sc->div_offset, reg);
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CLKDEV_DEVICE_UNLOCK(clknode_get_device(sc->clknode));
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/*
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* The linux driver notes there's no status/completion bit to poll.
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* So sleep for a bit and hope that's enough time for it to
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* settle.
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*/
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DELAY(1);
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*fout = f_freq;
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return (0);
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}
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static clknode_method_t qcom_clk_apssdiv_methods[] = {
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/* Device interface */
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CLKNODEMETHOD(clknode_init, qcom_clk_apssdiv_init),
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CLKNODEMETHOD(clknode_recalc_freq, qcom_clk_apssdiv_recalc),
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CLKNODEMETHOD(clknode_set_gate, qcom_clk_apssdiv_set_gate),
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CLKNODEMETHOD(clknode_set_freq, qcom_clk_apssdiv_set_freq),
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CLKNODEMETHOD_END
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};
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DEFINE_CLASS_1(qcom_clk_apssdiv, qcom_clk_apssdiv_class,
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qcom_clk_apssdiv_methods, sizeof(struct qcom_clk_apssdiv_sc),
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clknode_class);
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int
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qcom_clk_apssdiv_register(struct clkdom *clkdom,
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struct qcom_clk_apssdiv_def *clkdef)
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{
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struct clknode *clk;
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struct qcom_clk_apssdiv_sc *sc;
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clk = clknode_create(clkdom, &qcom_clk_apssdiv_class, &clkdef->clkdef);
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if (clk == NULL)
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return (1);
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sc = clknode_get_softc(clk);
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sc->clknode = clk;
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sc->div_offset = clkdef->div_offset;
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sc->div_width = clkdef->div_width;
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sc->div_shift = clkdef->div_shift;
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sc->freq_tbl = clkdef->freq_tbl;
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sc->enable_offset = clkdef->enable_offset;
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sc->enable_shift = clkdef->enable_shift;
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clknode_register(clkdom, clk);
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return (0);
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}
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