152 lines
4.4 KiB
C
152 lines
4.4 KiB
C
/*-
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* Copyright (c) 2021 Adrian Chadd <adrian@FreeBSD.org>.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/lock.h>
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#include <sys/mutex.h>
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#include <sys/rman.h>
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#include <machine/bus.h>
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#include <dev/extres/clk/clk.h>
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#include <dev/extres/clk/clk_div.h>
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#include <dev/extres/clk/clk_fixed.h>
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#include <dev/extres/clk/clk_mux.h>
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#include "qcom_clk_fepll.h"
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#include "clkdev_if.h"
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#if 0
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#define DPRINTF(dev, msg...) device_printf(dev, "cpufreq_dt: " msg);
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#else
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#define DPRINTF(dev, msg...)
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#endif
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/*
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* This is the top-level PLL clock on the IPQ4018/IPQ4019.
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* It's a fixed PLL clock that feeds a bunch of divisors into
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* downstrem FEPLL* and DDR clocks.
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*
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* Now, on Linux the clock code creates multiple instances of this
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* with an inbuilt divisor. Here instead there'll be a single
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* instance of the FEPLL, and then normal divisors will feed into
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* the multiple PLL nodes.
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*/
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struct qcom_clk_fepll_sc {
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struct clknode *clknode;
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uint32_t offset;
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uint32_t fdbkdiv_shift; /* FDBKDIV base */
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uint32_t fdbkdiv_width; /* FDBKDIV width */
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uint32_t refclkdiv_shift; /* REFCLKDIV base */
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uint32_t refclkdiv_width; /* REFCLKDIV width */
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};
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static int
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qcom_clk_fepll_recalc(struct clknode *clk, uint64_t *freq)
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{
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struct qcom_clk_fepll_sc *sc;
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uint64_t vco, parent_rate;
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uint32_t reg, fdbkdiv, refclkdiv;
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sc = clknode_get_softc(clk);
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if (freq == NULL || *freq == 0) {
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device_printf(clknode_get_device(sc->clknode),
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"%s: called; NULL or 0 frequency\n",
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__func__);
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return (ENXIO);
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}
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parent_rate = *freq;
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CLKDEV_DEVICE_LOCK(clknode_get_device(sc->clknode));
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CLKDEV_READ_4(clknode_get_device(sc->clknode), sc->offset, ®);
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CLKDEV_DEVICE_UNLOCK(clknode_get_device(sc->clknode));
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fdbkdiv = (reg >> sc->fdbkdiv_shift) &
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((1U << sc->fdbkdiv_width) - 1);
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refclkdiv = (reg >> sc->refclkdiv_shift) &
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((1U << sc->refclkdiv_width) - 1);
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vco = parent_rate / refclkdiv;
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vco = vco * 2;
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vco = vco * fdbkdiv;
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*freq = vco;
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return (0);
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}
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static int
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qcom_clk_fepll_init(struct clknode *clk, device_t dev)
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{
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/*
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* There's only a single parent here for an FEPLL, so just set it
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* to 0; the caller doesn't need to supply it.
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*/
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clknode_init_parent_idx(clk, 0);
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return (0);
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}
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static clknode_method_t qcom_clk_fepll_methods[] = {
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/* Device interface */
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CLKNODEMETHOD(clknode_init, qcom_clk_fepll_init),
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CLKNODEMETHOD(clknode_recalc_freq, qcom_clk_fepll_recalc),
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CLKNODEMETHOD_END
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};
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DEFINE_CLASS_1(qcom_clk_fepll, qcom_clk_fepll_class, qcom_clk_fepll_methods,
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sizeof(struct qcom_clk_fepll_sc), clknode_class);
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int
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qcom_clk_fepll_register(struct clkdom *clkdom,
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struct qcom_clk_fepll_def *clkdef)
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{
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struct clknode *clk;
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struct qcom_clk_fepll_sc *sc;
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clk = clknode_create(clkdom, &qcom_clk_fepll_class, &clkdef->clkdef);
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if (clk == NULL)
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return (1);
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sc = clknode_get_softc(clk);
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sc->clknode = clk;
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sc->offset = clkdef->offset;
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sc->fdbkdiv_shift = clkdef->fdbkdiv_shift;
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sc->fdbkdiv_width = clkdef->fdbkdiv_width;
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sc->refclkdiv_shift = clkdef->refclkdiv_shift;
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sc->refclkdiv_width = clkdef->refclkdiv_width;
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clknode_register(clkdom, clk);
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return (0);
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}
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