161 lines
5.6 KiB
C
161 lines
5.6 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2021 Adrian Chadd <adrian@FreeBSD.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#ifndef __QCOM_SPI_VAR_H__
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#define __QCOM_SPI_VAR_H__
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typedef enum {
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QCOM_SPI_HW_QPI_V1_1 = 1,
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QCOM_SPI_HW_QPI_V2_1 = 2,
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QCOM_SPI_HW_QPI_V2_2 = 3,
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} qcom_spi_hw_version_t;
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#define CS_MAX 4
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struct qcom_spi_softc {
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device_t sc_dev;
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device_t spibus;
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uint32_t sc_debug;
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struct resource *sc_mem_res;
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struct resource *sc_irq_res;
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void *sc_irq_h;
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struct mtx sc_mtx;
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bool sc_busy; /* an SPI transfer (cmd+data)
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* is active */
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qcom_spi_hw_version_t hw_version;
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clk_t clk_core; /* QUP/SPI core */
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clk_t clk_iface; /* SPI interface */
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/* For GPIO chip selects .. */
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gpio_pin_t cs_pins[CS_MAX];
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struct {
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/*
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* FIFO size / block size in bytes.
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*
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* The FIFO slots are DWORD sized, not byte sized.
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* So if the transfer size is set to 8 bits per
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* word (which is what we'll support initially)
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* the effective available FIFO is
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* fifo_size / sizeof(uint32_t).
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*/
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uint32_t input_block_size;
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uint32_t output_block_size;
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uint32_t input_fifo_size;
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uint32_t output_fifo_size;
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uint32_t cs_select;
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uint32_t num_cs;
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uint32_t max_frequency;
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} config;
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struct {
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uint32_t transfer_mode; /* QUP_IO_M_MODE_* */
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uint32_t transfer_word_size; /* how many bytes in a transfer word */
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uint32_t frequency;
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bool cs_high; /* true if CS is high for active */
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} state;
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struct {
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bool tx_dma_done;
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bool rx_dma_done;
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bool done;
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bool do_tx;
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bool do_rx;
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bool error;
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} intr;
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struct {
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bool active; /* a (sub) transfer is active */
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uint32_t num_words; /* number of word_size words to transfer */
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const char *tx_buf;
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int tx_len;
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int tx_offset;
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char *rx_buf;
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int rx_len;
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int rx_offset;
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bool done;
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} transfer;
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};
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#define QCOM_SPI_QUP_VERSION_V1(sc) \
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((sc)->hw_version == QCOM_SPI_HW_QPI_V1_1)
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#define QCOM_SPI_LOCK(sc) mtx_lock(&(sc)->sc_mtx)
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#define QCOM_SPI_UNLOCK(sc) mtx_unlock(&(sc)->sc_mtx)
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#define QCOM_SPI_ASSERT_LOCKED(sc) mtx_assert(&(sc)->sc_mtx, MA_OWNED)
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#define QCOM_SPI_READ_4(sc, reg) bus_read_4((sc)->sc_mem_res, (reg))
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#define QCOM_SPI_WRITE_4(sc, reg, val) bus_write_4((sc)->sc_mem_res, \
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(reg), (val))
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/* XXX TODO: the region size should be in the tag or softc */
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#define QCOM_SPI_BARRIER_WRITE(sc) bus_barrier((sc)->sc_mem_res, \
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0, 0x600, BUS_SPACE_BARRIER_WRITE)
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#define QCOM_SPI_BARRIER_READ(sc) bus_barrier((sc)->sc_mem_res, \
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0, 0x600, BUS_SPACE_BARRIER_READ)
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#define QCOM_SPI_BARRIER_RW(sc) bus_barrier((sc)->sc_mem_res, \
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0, 0x600, BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE)
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extern int qcom_spi_hw_read_controller_transfer_sizes(
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struct qcom_spi_softc *sc);
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extern int qcom_spi_hw_qup_set_state_locked(struct qcom_spi_softc *sc,
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uint32_t state);
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extern int qcom_spi_hw_qup_init_locked(struct qcom_spi_softc *sc);
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extern int qcom_spi_hw_spi_init_locked(struct qcom_spi_softc *sc);
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extern int qcom_spi_hw_spi_cs_force(struct qcom_spi_softc *sc, int cs,
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bool enable);
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extern int qcom_spi_hw_interrupt_handle(struct qcom_spi_softc *sc);
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extern int qcom_spi_hw_setup_transfer_selection(struct qcom_spi_softc *sc,
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uint32_t len);
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extern int qcom_spi_hw_complete_transfer(struct qcom_spi_softc *sc);
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extern int qcom_spi_hw_setup_current_transfer(struct qcom_spi_softc *sc);
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extern int qcom_spi_hw_setup_pio_transfer_cnt(struct qcom_spi_softc *sc);
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extern int qcom_spi_hw_setup_block_transfer_cnt(struct qcom_spi_softc *sc);
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extern int qcom_spi_hw_setup_io_modes(struct qcom_spi_softc *sc);
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extern int qcom_spi_hw_setup_spi_io_clock_polarity(
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struct qcom_spi_softc *sc, bool cpol);
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extern int qcom_spi_hw_setup_spi_config(struct qcom_spi_softc *sc,
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uint32_t clock_val, bool cpha);
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extern int qcom_spi_hw_setup_qup_config(struct qcom_spi_softc *sc,
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bool is_tx, bool is_rx);
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extern int qcom_spi_hw_setup_operational_mask(struct qcom_spi_softc *sc);
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extern int qcom_spi_hw_ack_write_pio_fifo(struct qcom_spi_softc *sc);
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extern int qcom_spi_hw_ack_opmode(struct qcom_spi_softc *sc);
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extern int qcom_spi_hw_write_pio_fifo(struct qcom_spi_softc *sc);
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extern int qcom_spi_hw_write_pio_block(struct qcom_spi_softc *sc);
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extern int qcom_spi_hw_read_pio_fifo(struct qcom_spi_softc *sc);
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extern int qcom_spi_hw_read_pio_block(struct qcom_spi_softc *sc);
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extern int qcom_spi_hw_do_full_reset(struct qcom_spi_softc *sc);
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#endif /* __QCOM_SPI_VAR_H__ */
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