615 lines
15 KiB
C
615 lines
15 KiB
C
/*-
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* Copyright (c) 2017 Semihalf.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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#include <sys/param.h>
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#include <sys/bus.h>
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#include <sys/conf.h>
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#include <sys/kernel.h>
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#include <sys/sysctl.h>
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#include <sys/systm.h>
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#include <machine/bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include <dev/uart/uart.h>
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#include <dev/uart/uart_bus.h>
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#include <dev/uart/uart_cpu.h>
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#include <dev/uart/uart_cpu_fdt.h>
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#include "uart_if.h"
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#define UART_RBR 0x00 /* Receiver Buffer */
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#define RBR_BRK_DET (1 << 15) /* Break Detect */
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#define RBR_FRM_ERR_DET (1 << 14) /* Frame Error Detect */
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#define RBR_PAR_ERR_DET (1 << 13) /* Parity Error Detect */
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#define RBR_OVR_ERR_DET (1 << 12) /* Overrun Error */
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#define UART_TSH 0x04 /* Transmitter Holding Register */
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#define UART_CTRL 0x08 /* Control Register */
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#define CTRL_SOFT_RST (1 << 31) /* Soft Reset */
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#define CTRL_TX_FIFO_RST (1 << 15) /* TX FIFO Reset */
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#define CTRL_RX_FIFO_RST (1 << 14) /* RX FIFO Reset */
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#define CTRL_ST_MIRR_EN (1 << 13) /* Status Mirror Enable */
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#define CTRL_LPBK_EN (1 << 12) /* Loopback Mode Enable */
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#define CTRL_SND_BRK_SEQ (1 << 11) /* Send Break Sequence */
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#define CTRL_PAR_EN (1 << 10) /* Parity Enable */
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#define CTRL_TWO_STOP (1 << 9) /* Two Stop Bits */
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#define CTRL_TX_HALF_INT (1 << 8) /* TX Half-Full Interrupt Enable */
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#define CTRL_RX_HALF_INT (1 << 7) /* RX Half-Full Interrupt Enable */
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#define CTRL_TX_EMPT_INT (1 << 6) /* TX Empty Interrupt Enable */
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#define CTRL_TX_RDY_INT (1 << 5) /* TX Ready Interrupt Enable */
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#define CTRL_RX_RDY_INT (1 << 4) /* RX Ready Interrupt Enable */
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#define CTRL_BRK_DET_INT (1 << 3) /* Break Detect Interrupt Enable */
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#define CTRL_FRM_ERR_INT (1 << 2) /* Frame Error Interrupt Enable */
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#define CTRL_PAR_ERR_INT (1 << 1) /* Parity Error Interrupt Enable */
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#define CTRL_OVR_ERR_INT (1 << 0) /* Overrun Error Interrupt Enable */
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#define CTRL_INTR_MASK 0x1ff
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#define CTRL_TX_IDLE_INT CTRL_TX_RDY_INT
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#define CTRL_IPEND_MASK (CTRL_OVR_ERR_INT | CTRL_BRK_DET_INT | \
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CTRL_RX_RDY_INT)
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#define UART_STAT 0x0c /* Status Register */
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#define STAT_TX_FIFO_EMPT (1 << 13) /* TX FIFO Empty */
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#define STAT_RX_FIFO_EMPT (1 << 12) /* RX FIFO Empty */
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#define STAT_TX_FIFO_FULL (1 << 11) /* TX FIFO Full */
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#define STAT_TX_FIFO_HALF (1 << 10) /* TX FIFO Half Full */
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#define STAT_RX_TOGL (1 << 9) /* RX Toogled */
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#define STAT_RX_FIFO_FULL (1 << 8) /* RX FIFO Full */
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#define STAT_RX_FIFO_HALF (1 << 7) /* RX FIFO Half Full */
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#define STAT_TX_EMPT (1 << 6) /* TX Empty */
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#define STAT_TX_RDY (1 << 5) /* TX Ready */
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#define STAT_RX_RDY (1 << 4) /* RX Ready */
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#define STAT_BRK_DET (1 << 3) /* Break Detect */
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#define STAT_FRM_ERR (1 << 2) /* Frame Error */
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#define STAT_PAR_ERR (1 << 1) /* Parity Error */
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#define STAT_OVR_ERR (1 << 0) /* Overrun Error */
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#define STAT_TX_IDLE STAT_TX_RDY
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#define STAT_TRANS_MASK (STAT_OVR_ERR | STAT_BRK_DET | STAT_RX_RDY)
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#define UART_CCR 0x10 /* Clock Control Register */
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#define CCR_BAUDRATE_DIV 0x3ff /* Baud Rate Divisor */
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#define DEFAULT_RCLK 25804800
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#define ONE_FRAME_TIME 87
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#define stat_ipend_trans(i) ( \
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(i & STAT_OVR_ERR) << 16 | \
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(i & STAT_BRK_DET) << 14 | \
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(i & STAT_RX_RDY) << 14)
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/*
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* For debugging purposes
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*/
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#if 0
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#ifdef EARLY_PRINTF
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#if defined(SOCDEV_PA) && defined(SOCDEV_VA)
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#define UART_REG_OFFSET 0x12000
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static void
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uart_mvebu_early_putc(int c)
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{
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volatile uint32_t *tsh;
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volatile uint32_t *stat;
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tsh = (uint32_t *)(SOCDEV_VA + UART_REG_OFFSET + UART_TSH);
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stat = (uint32_t *)(SOCDEV_VA + UART_REG_OFFSET + UART_STAT);
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while(!(*stat & STAT_TX_RDY))
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;
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*tsh = c & 0xff;
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}
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early_putc_t *early_putc = uart_mvebu_early_putc;
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#endif
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#endif
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#endif
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/*
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* Low-level UART interface.
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*/
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static int uart_mvebu_probe(struct uart_bas *);
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static void uart_mvebu_init(struct uart_bas *, int, int, int, int);
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static void uart_mvebu_putc(struct uart_bas *, int);
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static int uart_mvebu_rxready(struct uart_bas *);
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static int uart_mvebu_getc(struct uart_bas *, struct mtx *);
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static struct uart_ops uart_mvebu_ops = {
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.probe = uart_mvebu_probe,
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.init = uart_mvebu_init,
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.term = NULL,
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.putc = uart_mvebu_putc,
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.rxready = uart_mvebu_rxready,
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.getc = uart_mvebu_getc,
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};
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static int
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uart_mvebu_probe(struct uart_bas *bas)
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{
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return (0);
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}
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static int
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uart_mvebu_divisor(int rclk, int baudrate)
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{
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int divisor;
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if (baudrate == 0)
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return (0);
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divisor = (rclk >> 4) / baudrate;
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if (divisor <= 1 || divisor >= 1024)
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return (0);
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return (divisor);
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}
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static int
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uart_mvebu_param(struct uart_bas *bas, int baudrate, int databits, int stopbits,
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int parity)
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{
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uint32_t ctrl = 0;
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uint32_t ccr;
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int divisor, ret = 0;
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/* Reset UART */
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ctrl = uart_getreg(bas, UART_CTRL);
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uart_setreg(bas, UART_CTRL, ctrl | CTRL_TX_FIFO_RST | CTRL_RX_FIFO_RST |
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CTRL_LPBK_EN);
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uart_barrier(bas);
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switch (stopbits) {
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case 2:
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ctrl |= CTRL_TWO_STOP;
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break;
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case 1:
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default:
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ctrl &=~ CTRL_TWO_STOP;
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}
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switch (parity) {
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case 3: /* Even parity bit */
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ctrl |= CTRL_PAR_EN;
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break;
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default:
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ctrl &=~ CTRL_PAR_EN;
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}
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/* Set baudrate. */
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if (baudrate > 0) {
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divisor = uart_mvebu_divisor(bas->rclk, baudrate);
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if (divisor == 0) {
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ret = EINVAL;
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} else {
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ccr = uart_getreg(bas, UART_CCR);
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ccr &=~CCR_BAUDRATE_DIV;
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uart_setreg(bas, UART_CCR, ccr | divisor);
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uart_barrier(bas);
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}
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}
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/* Set mirroring of status bits */
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ctrl |= CTRL_ST_MIRR_EN;
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uart_setreg(bas, UART_CTRL, ctrl);
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uart_barrier(bas);
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return (ret);
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}
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static void
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uart_mvebu_init(struct uart_bas *bas, int baudrate, int databits, int stopbits,
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int parity)
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{
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/* Set default frequency */
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bas->rclk = DEFAULT_RCLK;
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/* Mask interrupts */
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uart_setreg(bas, UART_CTRL, uart_getreg(bas, UART_CTRL) &
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~CTRL_INTR_MASK);
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uart_barrier(bas);
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uart_mvebu_param(bas, baudrate, databits, stopbits, parity);
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}
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static void
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uart_mvebu_putc(struct uart_bas *bas, int c)
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{
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while (uart_getreg(bas, UART_STAT) & STAT_TX_FIFO_FULL)
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;
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uart_setreg(bas, UART_TSH, c & 0xff);
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}
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static int
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uart_mvebu_rxready(struct uart_bas *bas)
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{
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if (uart_getreg(bas, UART_STAT) & STAT_RX_RDY)
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return 1;
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return 0;
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}
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static int
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uart_mvebu_getc(struct uart_bas *bas, struct mtx *hwmtx)
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{
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int c;
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uart_lock(hwmtx);
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while (!(uart_getreg(bas, UART_STAT) & STAT_RX_RDY))
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;
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c = uart_getreg(bas, UART_RBR) & 0xff;
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uart_unlock(hwmtx);
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return c;
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}
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/*
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* UART driver methods implementation.
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*/
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struct uart_mvebu_softc {
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struct uart_softc base;
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uint16_t intrm;
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};
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static int uart_mvebu_bus_attach(struct uart_softc *);
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static int uart_mvebu_bus_detach(struct uart_softc *);
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static int uart_mvebu_bus_flush(struct uart_softc *, int);
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static int uart_mvebu_bus_getsig(struct uart_softc *);
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static int uart_mvebu_bus_ioctl(struct uart_softc *, int, intptr_t);
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static int uart_mvebu_bus_ipend(struct uart_softc *);
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static int uart_mvebu_bus_param(struct uart_softc *, int, int, int, int);
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static int uart_mvebu_bus_probe(struct uart_softc *);
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static int uart_mvebu_bus_receive(struct uart_softc *);
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static int uart_mvebu_bus_setsig(struct uart_softc *, int);
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static int uart_mvebu_bus_transmit(struct uart_softc *);
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static void uart_mvebu_bus_grab(struct uart_softc *);
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static void uart_mvebu_bus_ungrab(struct uart_softc *);
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static kobj_method_t uart_mvebu_methods[] = {
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KOBJMETHOD(uart_attach, uart_mvebu_bus_attach),
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KOBJMETHOD(uart_detach, uart_mvebu_bus_detach),
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KOBJMETHOD(uart_flush, uart_mvebu_bus_flush),
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KOBJMETHOD(uart_getsig, uart_mvebu_bus_getsig),
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KOBJMETHOD(uart_ioctl, uart_mvebu_bus_ioctl),
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KOBJMETHOD(uart_ipend, uart_mvebu_bus_ipend),
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KOBJMETHOD(uart_param, uart_mvebu_bus_param),
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KOBJMETHOD(uart_probe, uart_mvebu_bus_probe),
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KOBJMETHOD(uart_receive, uart_mvebu_bus_receive),
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KOBJMETHOD(uart_setsig, uart_mvebu_bus_setsig),
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KOBJMETHOD(uart_transmit, uart_mvebu_bus_transmit),
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KOBJMETHOD(uart_grab, uart_mvebu_bus_grab),
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KOBJMETHOD(uart_ungrab, uart_mvebu_bus_ungrab),
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{ 0, 0 }
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};
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struct uart_class uart_mvebu_class = {
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"mvebu-uart",
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uart_mvebu_methods,
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sizeof(struct uart_mvebu_softc),
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.uc_ops = &uart_mvebu_ops,
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.uc_range = 0x14,
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.uc_rclk = DEFAULT_RCLK,
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.uc_rshift = 0,
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.uc_riowidth = 4
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};
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static struct ofw_compat_data compat_data[] = {
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{"marvell,armada-3700-uart", (uintptr_t)&uart_mvebu_class},
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{NULL, (uintptr_t)NULL},
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};
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UART_FDT_CLASS_AND_DEVICE(compat_data);
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static int
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uart_mvebu_bus_attach(struct uart_softc *sc)
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{
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struct uart_bas *bas;
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int ctrl;
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bas = &sc->sc_bas;
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uart_lock(sc->sc_hwmtx);
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ctrl = uart_getreg(bas, UART_CTRL);
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/* Enable interrupts */
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ctrl &=~ CTRL_INTR_MASK;
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ctrl |= CTRL_IPEND_MASK;
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/* Set interrupts */
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uart_setreg(bas, UART_CTRL, ctrl);
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uart_barrier(bas);
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uart_unlock(sc->sc_hwmtx);
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return (0);
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}
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static int
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uart_mvebu_bus_detach(struct uart_softc *sc)
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{
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return (0);
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}
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static int
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uart_mvebu_bus_flush(struct uart_softc *sc, int what)
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{
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struct uart_bas *bas;
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int ctrl, ret = 0;
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bas = &sc->sc_bas;
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uart_lock(sc->sc_hwmtx);
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ctrl = uart_getreg(bas, UART_CTRL);
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switch (what) {
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case UART_FLUSH_RECEIVER:
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uart_setreg(bas, UART_CTRL, ctrl | CTRL_RX_FIFO_RST);
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uart_barrier(bas);
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break;
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case UART_FLUSH_TRANSMITTER:
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uart_setreg(bas, UART_CTRL, ctrl | CTRL_TX_FIFO_RST);
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uart_barrier(bas);
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break;
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default:
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ret = EINVAL;
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break;
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}
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/* Back to normal operation */
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if (!ret) {
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uart_setreg(bas, UART_CTRL, ctrl);
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uart_barrier(bas);
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}
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uart_unlock(sc->sc_hwmtx);
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return (ret);
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}
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static int
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uart_mvebu_bus_getsig(struct uart_softc *sc)
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{
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return (0);
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}
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static int
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uart_mvebu_bus_ioctl(struct uart_softc *sc, int request, intptr_t data)
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{
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struct uart_bas *bas;
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int ctrl, ret = 0;
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int divisor, baudrate;
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bas = &sc->sc_bas;
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uart_lock(sc->sc_hwmtx);
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switch (request) {
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case UART_IOCTL_BREAK:
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ctrl = uart_getreg(bas, UART_CTRL);
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if (data)
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ctrl |= CTRL_SND_BRK_SEQ;
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else
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ctrl &=~ CTRL_SND_BRK_SEQ;
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uart_setreg(bas, UART_CTRL, ctrl);
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uart_barrier(bas);
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break;
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case UART_IOCTL_BAUD:
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divisor = uart_getreg(bas, UART_CCR) & CCR_BAUDRATE_DIV;
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baudrate = bas->rclk/(divisor * 16);
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*(int *)data = baudrate;
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break;
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default:
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ret = ENOTTY;
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break;
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}
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uart_unlock(sc->sc_hwmtx);
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return (ret);
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}
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static int
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uart_mvebu_bus_ipend(struct uart_softc *sc)
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{
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struct uart_bas *bas;
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int ipend, ctrl, ret = 0;
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bas = &sc->sc_bas;
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uart_lock(sc->sc_hwmtx);
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ipend = uart_getreg(bas, UART_STAT);
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ctrl = uart_getreg(bas, UART_CTRL);
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if (((ipend & STAT_TX_IDLE) == STAT_TX_IDLE) &&
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(ctrl & CTRL_TX_IDLE_INT) == CTRL_TX_IDLE_INT) {
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/* Disable TX IDLE Interrupt generation */
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uart_setreg(bas, UART_CTRL, ctrl & ~CTRL_TX_IDLE_INT);
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uart_barrier(bas);
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/* SER_INT_TXIDLE means empty TX FIFO. Wait until it cleans */
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while(!(uart_getreg(bas, UART_STAT) & STAT_TX_FIFO_EMPT))
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DELAY(ONE_FRAME_TIME/2);
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ret |= SER_INT_TXIDLE;
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}
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ret |= stat_ipend_trans(ipend & STAT_TRANS_MASK);
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uart_unlock(sc->sc_hwmtx);
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return (ret);
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}
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static int
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uart_mvebu_bus_param(struct uart_softc *sc, int baudrate, int databits,
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int stopbits, int parity)
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{
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int ret;
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uart_lock(sc->sc_hwmtx);
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ret = uart_mvebu_param(&sc->sc_bas, baudrate, databits, stopbits, parity);
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uart_unlock(sc->sc_hwmtx);
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return (ret);
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}
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static int
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uart_mvebu_bus_probe(struct uart_softc *sc)
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{
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if (!ofw_bus_status_okay(sc->sc_dev))
|
|
return (ENXIO);
|
|
|
|
if (!ofw_bus_search_compatible(sc->sc_dev, compat_data)->ocd_data)
|
|
return (ENXIO);
|
|
|
|
device_set_desc(sc->sc_dev, "Marvell Armada 3700 UART");
|
|
|
|
sc->sc_txfifosz = 32;
|
|
sc->sc_rxfifosz = 64;
|
|
sc->sc_hwiflow = 0;
|
|
sc->sc_hwoflow = 0;
|
|
|
|
return (0);
|
|
}
|
|
|
|
int
|
|
uart_mvebu_bus_receive(struct uart_softc *sc)
|
|
{
|
|
struct uart_bas *bas;
|
|
uint32_t xc;
|
|
int rx, er;
|
|
|
|
bas = &sc->sc_bas;
|
|
uart_lock(sc->sc_hwmtx);
|
|
|
|
while (!(uart_getreg(bas, UART_STAT) & STAT_RX_FIFO_EMPT)) {
|
|
if (uart_rx_full(sc)) {
|
|
sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN;
|
|
break;
|
|
}
|
|
|
|
xc = uart_getreg(bas, UART_RBR);
|
|
rx = xc & 0xff;
|
|
er = xc & 0xf000;
|
|
/*
|
|
* Formula which translates marvell error bits
|
|
* Only valid when CTRL_ST_MIRR_EN is set
|
|
*/
|
|
er = (er & RBR_BRK_DET) >> 7 |
|
|
(er & RBR_FRM_ERR_DET) >> 5 |
|
|
(er & RBR_PAR_ERR_DET) >> 2 |
|
|
(er & RBR_OVR_ERR_DET) >> 2;
|
|
|
|
uart_rx_put(sc, rx | er);
|
|
uart_barrier(bas);
|
|
}
|
|
/*
|
|
* uart_if.m says that receive interrupt
|
|
* should be cleared, so we need to reset
|
|
* RX FIFO
|
|
*/
|
|
|
|
if (!(uart_getreg(bas, UART_STAT) & STAT_RX_FIFO_EMPT)) {
|
|
uart_mvebu_bus_flush(sc, UART_FLUSH_RECEIVER);
|
|
}
|
|
|
|
uart_unlock(sc->sc_hwmtx);
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
uart_mvebu_bus_setsig(struct uart_softc *sc, int sig)
|
|
{
|
|
/* Not supported by hardware */
|
|
return (0);
|
|
}
|
|
|
|
int
|
|
uart_mvebu_bus_transmit(struct uart_softc *sc)
|
|
{
|
|
struct uart_bas *bas;
|
|
int i, ctrl;
|
|
|
|
bas = &sc->sc_bas;
|
|
uart_lock(sc->sc_hwmtx);
|
|
|
|
/* Turn off all interrupts during send */
|
|
ctrl = uart_getreg(bas, UART_CTRL);
|
|
uart_setreg(bas, UART_CTRL, ctrl & ~CTRL_INTR_MASK);
|
|
uart_barrier(bas);
|
|
|
|
for (i = 0; i < sc->sc_txdatasz; i++) {
|
|
uart_setreg(bas, UART_TSH, sc->sc_txbuf[i] & 0xff);
|
|
uart_barrier(bas);
|
|
}
|
|
|
|
/*
|
|
* Make sure that interrupt is generated
|
|
* when FIFO can get more data.
|
|
*/
|
|
uart_setreg(bas, UART_CTRL, ctrl | CTRL_TX_IDLE_INT);
|
|
uart_barrier(bas);
|
|
|
|
/* Mark busy */
|
|
sc->sc_txbusy = 1;
|
|
|
|
uart_unlock(sc->sc_hwmtx);
|
|
return (0);
|
|
}
|
|
|
|
static void
|
|
uart_mvebu_bus_grab(struct uart_softc *sc)
|
|
{
|
|
struct uart_mvebu_softc *msc = (struct uart_mvebu_softc *)sc;
|
|
struct uart_bas *bas = &sc->sc_bas;
|
|
uint32_t ctrl;
|
|
|
|
/* Mask all interrupts */
|
|
uart_lock(sc->sc_hwmtx);
|
|
ctrl = uart_getreg(bas, UART_CTRL);
|
|
msc->intrm = ctrl & CTRL_INTR_MASK;
|
|
uart_setreg(bas, UART_CTRL, ctrl & ~CTRL_INTR_MASK);
|
|
uart_barrier(bas);
|
|
uart_unlock(sc->sc_hwmtx);
|
|
}
|
|
|
|
static void
|
|
uart_mvebu_bus_ungrab(struct uart_softc *sc)
|
|
{
|
|
struct uart_mvebu_softc *msc = (struct uart_mvebu_softc *)sc;
|
|
struct uart_bas *bas = &sc->sc_bas;
|
|
uint32_t ctrl;
|
|
|
|
/* Restore interrupts */
|
|
uart_lock(sc->sc_hwmtx);
|
|
ctrl = uart_getreg(bas, UART_CTRL) & ~CTRL_INTR_MASK;
|
|
uart_setreg(bas, UART_CTRL, ctrl | msc->intrm);
|
|
uart_barrier(bas);
|
|
uart_unlock(sc->sc_hwmtx);
|
|
}
|