1151 lines
24 KiB
C
1151 lines
24 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2019 Ruslan Bukin <br@bsdpad.com>
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*
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* This software was developed by SRI International and the University of
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* Cambridge Computer Laboratory (Department of Computer Science and
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* Technology) under DARPA contract HR0011-18-C-0016 ("ECATS"), as part of the
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* DARPA SSITH research programme.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/lock.h>
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#include <sys/malloc.h>
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#include <sys/mbuf.h>
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#include <sys/module.h>
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#include <sys/mutex.h>
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#include <sys/rman.h>
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#include <sys/socket.h>
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#include <sys/sockio.h>
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#include <net/bpf.h>
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#include <net/if.h>
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#include <net/ethernet.h>
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#include <net/if_dl.h>
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#include <net/if_media.h>
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#include <net/if_types.h>
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#include <net/if_var.h>
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#include <machine/bus.h>
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#include <dev/mii/mii.h>
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#include <dev/mii/miivar.h>
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#include <dev/mii/tiphy.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include <dev/xilinx/if_xaereg.h>
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#include <dev/xilinx/if_xaevar.h>
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#include <dev/xilinx/axidma.h>
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#include "miibus_if.h"
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#define READ4(_sc, _reg) \
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bus_read_4((_sc)->res[0], _reg)
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#define WRITE4(_sc, _reg, _val) \
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bus_write_4((_sc)->res[0], _reg, _val)
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#define READ8(_sc, _reg) \
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bus_read_8((_sc)->res[0], _reg)
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#define WRITE8(_sc, _reg, _val) \
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bus_write_8((_sc)->res[0], _reg, _val)
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#define XAE_LOCK(sc) mtx_lock(&(sc)->mtx)
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#define XAE_UNLOCK(sc) mtx_unlock(&(sc)->mtx)
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#define XAE_ASSERT_LOCKED(sc) mtx_assert(&(sc)->mtx, MA_OWNED)
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#define XAE_ASSERT_UNLOCKED(sc) mtx_assert(&(sc)->mtx, MA_NOTOWNED)
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#define XAE_DEBUG
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#undef XAE_DEBUG
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#ifdef XAE_DEBUG
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#define dprintf(fmt, ...) printf(fmt, ##__VA_ARGS__)
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#else
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#define dprintf(fmt, ...)
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#endif
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#define RX_QUEUE_SIZE 64
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#define TX_QUEUE_SIZE 64
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#define NUM_RX_MBUF 16
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#define BUFRING_SIZE 8192
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#define MDIO_CLK_DIV_DEFAULT 29
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#define PHY1_RD(sc, _r) \
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xae_miibus_read_reg(sc->dev, 1, _r)
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#define PHY1_WR(sc, _r, _v) \
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xae_miibus_write_reg(sc->dev, 1, _r, _v)
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#define PHY_RD(sc, _r) \
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xae_miibus_read_reg(sc->dev, sc->phy_addr, _r)
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#define PHY_WR(sc, _r, _v) \
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xae_miibus_write_reg(sc->dev, sc->phy_addr, _r, _v)
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/* Use this macro to access regs > 0x1f */
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#define WRITE_TI_EREG(sc, reg, data) { \
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PHY_WR(sc, MII_MMDACR, MMDACR_DADDRMASK); \
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PHY_WR(sc, MII_MMDAADR, reg); \
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PHY_WR(sc, MII_MMDACR, MMDACR_DADDRMASK | MMDACR_FN_DATANPI); \
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PHY_WR(sc, MII_MMDAADR, data); \
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}
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/* Not documented, Xilinx VCU118 workaround */
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#define CFG4_SGMII_TMR 0x160 /* bits 8:7 MUST be '10' */
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#define DP83867_SGMIICTL1 0xD3 /* not documented register */
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#define SGMIICTL1_SGMII_6W (1 << 14) /* no idea what it is */
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static struct resource_spec xae_spec[] = {
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{ SYS_RES_MEMORY, 0, RF_ACTIVE },
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{ SYS_RES_IRQ, 0, RF_ACTIVE },
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{ -1, 0 }
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};
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static void xae_stop_locked(struct xae_softc *sc);
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static void xae_setup_rxfilter(struct xae_softc *sc);
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static int
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xae_rx_enqueue(struct xae_softc *sc, uint32_t n)
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{
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struct mbuf *m;
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int i;
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for (i = 0; i < n; i++) {
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m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
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if (m == NULL) {
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device_printf(sc->dev,
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"%s: Can't alloc rx mbuf\n", __func__);
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return (-1);
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}
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m->m_pkthdr.len = m->m_len = m->m_ext.ext_size;
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xdma_enqueue_mbuf(sc->xchan_rx, &m, 0, 4, 4, XDMA_DEV_TO_MEM);
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}
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return (0);
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}
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static int
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xae_get_phyaddr(phandle_t node, int *phy_addr)
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{
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phandle_t phy_node;
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pcell_t phy_handle, phy_reg;
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if (OF_getencprop(node, "phy-handle", (void *)&phy_handle,
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sizeof(phy_handle)) <= 0)
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return (ENXIO);
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phy_node = OF_node_from_xref(phy_handle);
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if (OF_getencprop(phy_node, "reg", (void *)&phy_reg,
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sizeof(phy_reg)) <= 0)
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return (ENXIO);
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*phy_addr = phy_reg;
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return (0);
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}
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static int
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xae_xdma_tx_intr(void *arg, xdma_transfer_status_t *status)
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{
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xdma_transfer_status_t st;
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struct xae_softc *sc;
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if_t ifp;
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struct mbuf *m;
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int err;
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sc = arg;
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XAE_LOCK(sc);
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ifp = sc->ifp;
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for (;;) {
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err = xdma_dequeue_mbuf(sc->xchan_tx, &m, &st);
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if (err != 0) {
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break;
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}
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if (st.error != 0) {
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if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
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}
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m_freem(m);
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}
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if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE);
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XAE_UNLOCK(sc);
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return (0);
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}
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static int
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xae_xdma_rx_intr(void *arg, xdma_transfer_status_t *status)
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{
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xdma_transfer_status_t st;
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struct xae_softc *sc;
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if_t ifp;
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struct mbuf *m;
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int err;
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uint32_t cnt_processed;
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sc = arg;
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dprintf("%s\n", __func__);
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XAE_LOCK(sc);
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ifp = sc->ifp;
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cnt_processed = 0;
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for (;;) {
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err = xdma_dequeue_mbuf(sc->xchan_rx, &m, &st);
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if (err != 0) {
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break;
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}
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cnt_processed++;
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if (st.error != 0) {
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if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
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m_freem(m);
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continue;
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}
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m->m_pkthdr.len = m->m_len = st.transferred;
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m->m_pkthdr.rcvif = ifp;
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XAE_UNLOCK(sc);
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if_input(ifp, m);
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XAE_LOCK(sc);
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}
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xae_rx_enqueue(sc, cnt_processed);
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XAE_UNLOCK(sc);
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return (0);
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}
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static void
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xae_qflush(if_t ifp)
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{
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}
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static int
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xae_transmit_locked(if_t ifp)
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{
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struct xae_softc *sc;
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struct mbuf *m;
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struct buf_ring *br;
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int error;
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int enq;
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dprintf("%s\n", __func__);
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sc = if_getsoftc(ifp);
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br = sc->br;
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enq = 0;
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while ((m = drbr_peek(ifp, br)) != NULL) {
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error = xdma_enqueue_mbuf(sc->xchan_tx,
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&m, 0, 4, 4, XDMA_MEM_TO_DEV);
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if (error != 0) {
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/* No space in request queue available yet. */
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drbr_putback(ifp, br, m);
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break;
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}
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drbr_advance(ifp, br);
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enq++;
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/* If anyone is interested give them a copy. */
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ETHER_BPF_MTAP(ifp, m);
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}
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if (enq > 0)
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xdma_queue_submit(sc->xchan_tx);
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return (0);
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}
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static int
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xae_transmit(if_t ifp, struct mbuf *m)
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{
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struct xae_softc *sc;
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int error;
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dprintf("%s\n", __func__);
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sc = if_getsoftc(ifp);
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XAE_LOCK(sc);
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error = drbr_enqueue(ifp, sc->br, m);
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if (error) {
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XAE_UNLOCK(sc);
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return (error);
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}
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if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
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IFF_DRV_RUNNING) {
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XAE_UNLOCK(sc);
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return (0);
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}
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if (!sc->link_is_up) {
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XAE_UNLOCK(sc);
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return (0);
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}
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error = xae_transmit_locked(ifp);
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XAE_UNLOCK(sc);
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return (error);
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}
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static void
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xae_stop_locked(struct xae_softc *sc)
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{
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if_t ifp;
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uint32_t reg;
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XAE_ASSERT_LOCKED(sc);
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ifp = sc->ifp;
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if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING | IFF_DRV_OACTIVE));
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callout_stop(&sc->xae_callout);
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/* Stop the transmitter */
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reg = READ4(sc, XAE_TC);
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reg &= ~TC_TX;
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WRITE4(sc, XAE_TC, reg);
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/* Stop the receiver. */
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reg = READ4(sc, XAE_RCW1);
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reg &= ~RCW1_RX;
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WRITE4(sc, XAE_RCW1, reg);
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}
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static uint64_t
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xae_stat(struct xae_softc *sc, int counter_id)
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{
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uint64_t new, old;
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uint64_t delta;
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KASSERT(counter_id < XAE_MAX_COUNTERS,
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("counter %d is out of range", counter_id));
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new = READ8(sc, XAE_STATCNT(counter_id));
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old = sc->counters[counter_id];
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if (new >= old)
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delta = new - old;
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else
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delta = UINT64_MAX - old + new;
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sc->counters[counter_id] = new;
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return (delta);
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}
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static void
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xae_harvest_stats(struct xae_softc *sc)
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{
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if_t ifp;
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ifp = sc->ifp;
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if_inc_counter(ifp, IFCOUNTER_IPACKETS, xae_stat(sc, RX_GOOD_FRAMES));
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if_inc_counter(ifp, IFCOUNTER_IMCASTS, xae_stat(sc, RX_GOOD_MCASTS));
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if_inc_counter(ifp, IFCOUNTER_IERRORS,
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xae_stat(sc, RX_FRAME_CHECK_SEQ_ERROR) +
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xae_stat(sc, RX_LEN_OUT_OF_RANGE) +
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xae_stat(sc, RX_ALIGNMENT_ERRORS));
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if_inc_counter(ifp, IFCOUNTER_OBYTES, xae_stat(sc, TX_BYTES));
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if_inc_counter(ifp, IFCOUNTER_OPACKETS, xae_stat(sc, TX_GOOD_FRAMES));
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if_inc_counter(ifp, IFCOUNTER_OMCASTS, xae_stat(sc, TX_GOOD_MCASTS));
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if_inc_counter(ifp, IFCOUNTER_OERRORS,
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xae_stat(sc, TX_GOOD_UNDERRUN_ERRORS));
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if_inc_counter(ifp, IFCOUNTER_COLLISIONS,
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xae_stat(sc, TX_SINGLE_COLLISION_FRAMES) +
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xae_stat(sc, TX_MULTI_COLLISION_FRAMES) +
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xae_stat(sc, TX_LATE_COLLISIONS) +
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xae_stat(sc, TX_EXCESS_COLLISIONS));
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}
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static void
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xae_tick(void *arg)
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{
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struct xae_softc *sc;
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if_t ifp;
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int link_was_up;
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sc = arg;
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XAE_ASSERT_LOCKED(sc);
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ifp = sc->ifp;
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if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING))
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return;
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/* Gather stats from hardware counters. */
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xae_harvest_stats(sc);
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/* Check the media status. */
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link_was_up = sc->link_is_up;
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mii_tick(sc->mii_softc);
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if (sc->link_is_up && !link_was_up)
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xae_transmit_locked(sc->ifp);
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/* Schedule another check one second from now. */
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callout_reset(&sc->xae_callout, hz, xae_tick, sc);
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}
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static void
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xae_init_locked(struct xae_softc *sc)
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{
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if_t ifp;
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XAE_ASSERT_LOCKED(sc);
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ifp = sc->ifp;
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if (if_getdrvflags(ifp) & IFF_DRV_RUNNING)
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return;
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if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0);
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xae_setup_rxfilter(sc);
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/* Enable the transmitter */
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WRITE4(sc, XAE_TC, TC_TX);
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/* Enable the receiver. */
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WRITE4(sc, XAE_RCW1, RCW1_RX);
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/*
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* Call mii_mediachg() which will call back into xae_miibus_statchg()
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* to set up the remaining config registers based on current media.
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*/
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mii_mediachg(sc->mii_softc);
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callout_reset(&sc->xae_callout, hz, xae_tick, sc);
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}
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static void
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xae_init(void *arg)
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{
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struct xae_softc *sc;
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sc = arg;
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XAE_LOCK(sc);
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xae_init_locked(sc);
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XAE_UNLOCK(sc);
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}
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static void
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xae_media_status(if_t ifp, struct ifmediareq *ifmr)
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{
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struct xae_softc *sc;
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struct mii_data *mii;
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sc = if_getsoftc(ifp);
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mii = sc->mii_softc;
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XAE_LOCK(sc);
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mii_pollstat(mii);
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ifmr->ifm_active = mii->mii_media_active;
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ifmr->ifm_status = mii->mii_media_status;
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XAE_UNLOCK(sc);
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}
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static int
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xae_media_change_locked(struct xae_softc *sc)
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{
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return (mii_mediachg(sc->mii_softc));
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}
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static int
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xae_media_change(if_t ifp)
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{
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struct xae_softc *sc;
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int error;
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sc = if_getsoftc(ifp);
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XAE_LOCK(sc);
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error = xae_media_change_locked(sc);
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XAE_UNLOCK(sc);
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return (error);
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}
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static u_int
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xae_write_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt)
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{
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struct xae_softc *sc = arg;
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uint32_t reg;
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uint8_t *ma;
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if (cnt >= XAE_MULTICAST_TABLE_SIZE)
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return (1);
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ma = LLADDR(sdl);
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|
|
reg = READ4(sc, XAE_FFC) & 0xffffff00;
|
|
reg |= cnt;
|
|
WRITE4(sc, XAE_FFC, reg);
|
|
|
|
reg = (ma[0]);
|
|
reg |= (ma[1] << 8);
|
|
reg |= (ma[2] << 16);
|
|
reg |= (ma[3] << 24);
|
|
WRITE4(sc, XAE_FFV(0), reg);
|
|
|
|
reg = ma[4];
|
|
reg |= ma[5] << 8;
|
|
WRITE4(sc, XAE_FFV(1), reg);
|
|
|
|
return (1);
|
|
}
|
|
|
|
static void
|
|
xae_setup_rxfilter(struct xae_softc *sc)
|
|
{
|
|
if_t ifp;
|
|
uint32_t reg;
|
|
|
|
XAE_ASSERT_LOCKED(sc);
|
|
|
|
ifp = sc->ifp;
|
|
|
|
/*
|
|
* Set the multicast (group) filter hash.
|
|
*/
|
|
if ((if_getflags(ifp) & (IFF_ALLMULTI | IFF_PROMISC)) != 0) {
|
|
reg = READ4(sc, XAE_FFC);
|
|
reg |= FFC_PM;
|
|
WRITE4(sc, XAE_FFC, reg);
|
|
} else {
|
|
reg = READ4(sc, XAE_FFC);
|
|
reg &= ~FFC_PM;
|
|
WRITE4(sc, XAE_FFC, reg);
|
|
|
|
if_foreach_llmaddr(ifp, xae_write_maddr, sc);
|
|
}
|
|
|
|
/*
|
|
* Set the primary address.
|
|
*/
|
|
reg = sc->macaddr[0];
|
|
reg |= (sc->macaddr[1] << 8);
|
|
reg |= (sc->macaddr[2] << 16);
|
|
reg |= (sc->macaddr[3] << 24);
|
|
WRITE4(sc, XAE_UAW0, reg);
|
|
|
|
reg = sc->macaddr[4];
|
|
reg |= (sc->macaddr[5] << 8);
|
|
WRITE4(sc, XAE_UAW1, reg);
|
|
}
|
|
|
|
static int
|
|
xae_ioctl(if_t ifp, u_long cmd, caddr_t data)
|
|
{
|
|
struct xae_softc *sc;
|
|
struct mii_data *mii;
|
|
struct ifreq *ifr;
|
|
int mask, error;
|
|
|
|
sc = if_getsoftc(ifp);
|
|
ifr = (struct ifreq *)data;
|
|
|
|
error = 0;
|
|
switch (cmd) {
|
|
case SIOCSIFFLAGS:
|
|
XAE_LOCK(sc);
|
|
if (if_getflags(ifp) & IFF_UP) {
|
|
if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
|
|
if ((if_getflags(ifp) ^ sc->if_flags) &
|
|
(IFF_PROMISC | IFF_ALLMULTI))
|
|
xae_setup_rxfilter(sc);
|
|
} else {
|
|
if (!sc->is_detaching)
|
|
xae_init_locked(sc);
|
|
}
|
|
} else {
|
|
if (if_getdrvflags(ifp) & IFF_DRV_RUNNING)
|
|
xae_stop_locked(sc);
|
|
}
|
|
sc->if_flags = if_getflags(ifp);
|
|
XAE_UNLOCK(sc);
|
|
break;
|
|
case SIOCADDMULTI:
|
|
case SIOCDELMULTI:
|
|
if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
|
|
XAE_LOCK(sc);
|
|
xae_setup_rxfilter(sc);
|
|
XAE_UNLOCK(sc);
|
|
}
|
|
break;
|
|
case SIOCSIFMEDIA:
|
|
case SIOCGIFMEDIA:
|
|
mii = sc->mii_softc;
|
|
error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd);
|
|
break;
|
|
case SIOCSIFCAP:
|
|
mask = if_getcapenable(ifp) ^ ifr->ifr_reqcap;
|
|
if (mask & IFCAP_VLAN_MTU) {
|
|
/* No work to do except acknowledge the change took */
|
|
if_togglecapenable(ifp, IFCAP_VLAN_MTU);
|
|
}
|
|
break;
|
|
|
|
default:
|
|
error = ether_ioctl(ifp, cmd, data);
|
|
break;
|
|
}
|
|
|
|
return (error);
|
|
}
|
|
|
|
static void
|
|
xae_intr(void *arg)
|
|
{
|
|
|
|
}
|
|
|
|
static int
|
|
xae_get_hwaddr(struct xae_softc *sc, uint8_t *hwaddr)
|
|
{
|
|
phandle_t node;
|
|
int len;
|
|
|
|
node = ofw_bus_get_node(sc->dev);
|
|
|
|
/* Check if there is property */
|
|
if ((len = OF_getproplen(node, "local-mac-address")) <= 0)
|
|
return (EINVAL);
|
|
|
|
if (len != ETHER_ADDR_LEN)
|
|
return (EINVAL);
|
|
|
|
OF_getprop(node, "local-mac-address", hwaddr,
|
|
ETHER_ADDR_LEN);
|
|
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
mdio_wait(struct xae_softc *sc)
|
|
{
|
|
uint32_t reg;
|
|
int timeout;
|
|
|
|
timeout = 200;
|
|
|
|
do {
|
|
reg = READ4(sc, XAE_MDIO_CTRL);
|
|
if (reg & MDIO_CTRL_READY)
|
|
break;
|
|
DELAY(1);
|
|
} while (timeout--);
|
|
|
|
if (timeout <= 0) {
|
|
printf("Failed to get MDIO ready\n");
|
|
return (1);
|
|
}
|
|
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
xae_miibus_read_reg(device_t dev, int phy, int reg)
|
|
{
|
|
struct xae_softc *sc;
|
|
uint32_t mii;
|
|
int rv;
|
|
|
|
sc = device_get_softc(dev);
|
|
|
|
if (mdio_wait(sc))
|
|
return (0);
|
|
|
|
mii = MDIO_CTRL_TX_OP_READ | MDIO_CTRL_INITIATE;
|
|
mii |= (reg << MDIO_TX_REGAD_S);
|
|
mii |= (phy << MDIO_TX_PHYAD_S);
|
|
|
|
WRITE4(sc, XAE_MDIO_CTRL, mii);
|
|
|
|
if (mdio_wait(sc))
|
|
return (0);
|
|
|
|
rv = READ4(sc, XAE_MDIO_READ);
|
|
|
|
return (rv);
|
|
}
|
|
|
|
static int
|
|
xae_miibus_write_reg(device_t dev, int phy, int reg, int val)
|
|
{
|
|
struct xae_softc *sc;
|
|
uint32_t mii;
|
|
|
|
sc = device_get_softc(dev);
|
|
|
|
if (mdio_wait(sc))
|
|
return (1);
|
|
|
|
mii = MDIO_CTRL_TX_OP_WRITE | MDIO_CTRL_INITIATE;
|
|
mii |= (reg << MDIO_TX_REGAD_S);
|
|
mii |= (phy << MDIO_TX_PHYAD_S);
|
|
|
|
WRITE4(sc, XAE_MDIO_WRITE, val);
|
|
WRITE4(sc, XAE_MDIO_CTRL, mii);
|
|
|
|
if (mdio_wait(sc))
|
|
return (1);
|
|
|
|
return (0);
|
|
}
|
|
|
|
static void
|
|
xae_phy_fixup(struct xae_softc *sc)
|
|
{
|
|
uint32_t reg;
|
|
|
|
do {
|
|
WRITE_TI_EREG(sc, DP83867_SGMIICTL1, SGMIICTL1_SGMII_6W);
|
|
PHY_WR(sc, DP83867_PHYCR, PHYCR_SGMII_EN);
|
|
|
|
reg = PHY_RD(sc, DP83867_CFG2);
|
|
reg &= ~CFG2_SPEED_OPT_ATTEMPT_CNT_M;
|
|
reg |= (CFG2_SPEED_OPT_ATTEMPT_CNT_4);
|
|
reg |= CFG2_INTERRUPT_POLARITY;
|
|
reg |= CFG2_SPEED_OPT_ENHANCED_EN;
|
|
reg |= CFG2_SPEED_OPT_10M_EN;
|
|
PHY_WR(sc, DP83867_CFG2, reg);
|
|
|
|
WRITE_TI_EREG(sc, DP83867_CFG4, CFG4_SGMII_TMR);
|
|
PHY_WR(sc, MII_BMCR,
|
|
BMCR_AUTOEN | BMCR_FDX | BMCR_SPEED1 | BMCR_RESET);
|
|
} while (PHY1_RD(sc, MII_BMCR) == 0x0ffff);
|
|
|
|
do {
|
|
PHY1_WR(sc, MII_BMCR,
|
|
BMCR_AUTOEN | BMCR_FDX | BMCR_SPEED1 | BMCR_STARTNEG);
|
|
DELAY(40000);
|
|
} while ((PHY1_RD(sc, MII_BMSR) & BMSR_ACOMP) == 0);
|
|
}
|
|
|
|
static int
|
|
get_xdma_std(struct xae_softc *sc)
|
|
{
|
|
|
|
sc->xdma_tx = xdma_ofw_get(sc->dev, "tx");
|
|
if (sc->xdma_tx == NULL)
|
|
return (ENXIO);
|
|
|
|
sc->xdma_rx = xdma_ofw_get(sc->dev, "rx");
|
|
if (sc->xdma_rx == NULL) {
|
|
xdma_put(sc->xdma_tx);
|
|
return (ENXIO);
|
|
}
|
|
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
get_xdma_axistream(struct xae_softc *sc)
|
|
{
|
|
struct axidma_fdt_data *data;
|
|
device_t dma_dev;
|
|
phandle_t node;
|
|
pcell_t prop;
|
|
size_t len;
|
|
|
|
node = ofw_bus_get_node(sc->dev);
|
|
len = OF_getencprop(node, "axistream-connected", &prop, sizeof(prop));
|
|
if (len != sizeof(prop)) {
|
|
device_printf(sc->dev,
|
|
"%s: Couldn't get axistream-connected prop.\n", __func__);
|
|
return (ENXIO);
|
|
}
|
|
dma_dev = OF_device_from_xref(prop);
|
|
if (dma_dev == NULL) {
|
|
device_printf(sc->dev, "Could not get DMA device by xref.\n");
|
|
return (ENXIO);
|
|
}
|
|
|
|
sc->xdma_tx = xdma_get(sc->dev, dma_dev);
|
|
if (sc->xdma_tx == NULL) {
|
|
device_printf(sc->dev, "Could not find DMA controller.\n");
|
|
return (ENXIO);
|
|
}
|
|
data = malloc(sizeof(struct axidma_fdt_data),
|
|
M_DEVBUF, (M_WAITOK | M_ZERO));
|
|
data->id = AXIDMA_TX_CHAN;
|
|
sc->xdma_tx->data = data;
|
|
|
|
sc->xdma_rx = xdma_get(sc->dev, dma_dev);
|
|
if (sc->xdma_rx == NULL) {
|
|
device_printf(sc->dev, "Could not find DMA controller.\n");
|
|
return (ENXIO);
|
|
}
|
|
data = malloc(sizeof(struct axidma_fdt_data),
|
|
M_DEVBUF, (M_WAITOK | M_ZERO));
|
|
data->id = AXIDMA_RX_CHAN;
|
|
sc->xdma_rx->data = data;
|
|
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
setup_xdma(struct xae_softc *sc)
|
|
{
|
|
device_t dev;
|
|
vmem_t *vmem;
|
|
int error;
|
|
|
|
dev = sc->dev;
|
|
|
|
/* Get xDMA controller */
|
|
error = get_xdma_std(sc);
|
|
|
|
if (error) {
|
|
device_printf(sc->dev,
|
|
"Fallback to axistream-connected property\n");
|
|
error = get_xdma_axistream(sc);
|
|
}
|
|
|
|
if (error) {
|
|
device_printf(dev, "Could not find xDMA controllers.\n");
|
|
return (ENXIO);
|
|
}
|
|
|
|
/* Alloc xDMA TX virtual channel. */
|
|
sc->xchan_tx = xdma_channel_alloc(sc->xdma_tx, 0);
|
|
if (sc->xchan_tx == NULL) {
|
|
device_printf(dev, "Can't alloc virtual DMA TX channel.\n");
|
|
return (ENXIO);
|
|
}
|
|
|
|
/* Setup interrupt handler. */
|
|
error = xdma_setup_intr(sc->xchan_tx, 0,
|
|
xae_xdma_tx_intr, sc, &sc->ih_tx);
|
|
if (error) {
|
|
device_printf(sc->dev,
|
|
"Can't setup xDMA TX interrupt handler.\n");
|
|
return (ENXIO);
|
|
}
|
|
|
|
/* Alloc xDMA RX virtual channel. */
|
|
sc->xchan_rx = xdma_channel_alloc(sc->xdma_rx, 0);
|
|
if (sc->xchan_rx == NULL) {
|
|
device_printf(dev, "Can't alloc virtual DMA RX channel.\n");
|
|
return (ENXIO);
|
|
}
|
|
|
|
/* Setup interrupt handler. */
|
|
error = xdma_setup_intr(sc->xchan_rx, XDMA_INTR_NET,
|
|
xae_xdma_rx_intr, sc, &sc->ih_rx);
|
|
if (error) {
|
|
device_printf(sc->dev,
|
|
"Can't setup xDMA RX interrupt handler.\n");
|
|
return (ENXIO);
|
|
}
|
|
|
|
/* Setup bounce buffer */
|
|
vmem = xdma_get_memory(dev);
|
|
if (vmem) {
|
|
xchan_set_memory(sc->xchan_tx, vmem);
|
|
xchan_set_memory(sc->xchan_rx, vmem);
|
|
}
|
|
|
|
xdma_prep_sg(sc->xchan_tx,
|
|
TX_QUEUE_SIZE, /* xchan requests queue size */
|
|
MCLBYTES, /* maxsegsize */
|
|
8, /* maxnsegs */
|
|
16, /* alignment */
|
|
0, /* boundary */
|
|
BUS_SPACE_MAXADDR_32BIT,
|
|
BUS_SPACE_MAXADDR);
|
|
|
|
xdma_prep_sg(sc->xchan_rx,
|
|
RX_QUEUE_SIZE, /* xchan requests queue size */
|
|
MCLBYTES, /* maxsegsize */
|
|
1, /* maxnsegs */
|
|
16, /* alignment */
|
|
0, /* boundary */
|
|
BUS_SPACE_MAXADDR_32BIT,
|
|
BUS_SPACE_MAXADDR);
|
|
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
xae_probe(device_t dev)
|
|
{
|
|
|
|
if (!ofw_bus_status_okay(dev))
|
|
return (ENXIO);
|
|
|
|
if (!ofw_bus_is_compatible(dev, "xlnx,axi-ethernet-1.00.a"))
|
|
return (ENXIO);
|
|
|
|
device_set_desc(dev, "Xilinx AXI Ethernet");
|
|
|
|
return (BUS_PROBE_DEFAULT);
|
|
}
|
|
|
|
static int
|
|
xae_attach(device_t dev)
|
|
{
|
|
struct xae_softc *sc;
|
|
if_t ifp;
|
|
phandle_t node;
|
|
uint32_t reg;
|
|
int error;
|
|
|
|
sc = device_get_softc(dev);
|
|
sc->dev = dev;
|
|
node = ofw_bus_get_node(dev);
|
|
|
|
if (setup_xdma(sc) != 0) {
|
|
device_printf(dev, "Could not setup xDMA.\n");
|
|
return (ENXIO);
|
|
}
|
|
|
|
mtx_init(&sc->mtx, device_get_nameunit(sc->dev),
|
|
MTX_NETWORK_LOCK, MTX_DEF);
|
|
|
|
sc->br = buf_ring_alloc(BUFRING_SIZE, M_DEVBUF,
|
|
M_NOWAIT, &sc->mtx);
|
|
if (sc->br == NULL)
|
|
return (ENOMEM);
|
|
|
|
if (bus_alloc_resources(dev, xae_spec, sc->res)) {
|
|
device_printf(dev, "could not allocate resources\n");
|
|
return (ENXIO);
|
|
}
|
|
|
|
/* Memory interface */
|
|
sc->bst = rman_get_bustag(sc->res[0]);
|
|
sc->bsh = rman_get_bushandle(sc->res[0]);
|
|
|
|
device_printf(sc->dev, "Identification: %x\n",
|
|
READ4(sc, XAE_IDENT));
|
|
|
|
/* Get MAC addr */
|
|
if (xae_get_hwaddr(sc, sc->macaddr)) {
|
|
device_printf(sc->dev, "can't get mac\n");
|
|
return (ENXIO);
|
|
}
|
|
|
|
/* Enable MII clock */
|
|
reg = (MDIO_CLK_DIV_DEFAULT << MDIO_SETUP_CLK_DIV_S);
|
|
reg |= MDIO_SETUP_ENABLE;
|
|
WRITE4(sc, XAE_MDIO_SETUP, reg);
|
|
if (mdio_wait(sc))
|
|
return (ENXIO);
|
|
|
|
callout_init_mtx(&sc->xae_callout, &sc->mtx, 0);
|
|
|
|
/* Setup interrupt handler. */
|
|
error = bus_setup_intr(dev, sc->res[1], INTR_TYPE_NET | INTR_MPSAFE,
|
|
NULL, xae_intr, sc, &sc->intr_cookie);
|
|
if (error != 0) {
|
|
device_printf(dev, "could not setup interrupt handler.\n");
|
|
return (ENXIO);
|
|
}
|
|
|
|
/* Set up the ethernet interface. */
|
|
sc->ifp = ifp = if_alloc(IFT_ETHER);
|
|
if (ifp == NULL) {
|
|
device_printf(dev, "could not allocate ifp.\n");
|
|
return (ENXIO);
|
|
}
|
|
|
|
if_setsoftc(ifp, sc);
|
|
if_initname(ifp, device_get_name(dev), device_get_unit(dev));
|
|
if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST);
|
|
if_setcapabilities(ifp, IFCAP_VLAN_MTU);
|
|
if_setcapenable(ifp, if_getcapabilities(ifp));
|
|
if_settransmitfn(ifp, xae_transmit);
|
|
if_setqflushfn(ifp, xae_qflush);
|
|
if_setioctlfn(ifp, xae_ioctl);
|
|
if_setinitfn(ifp, xae_init);
|
|
if_setsendqlen(ifp, TX_DESC_COUNT - 1);
|
|
if_setsendqready(ifp);
|
|
|
|
if (xae_get_phyaddr(node, &sc->phy_addr) != 0)
|
|
return (ENXIO);
|
|
|
|
/* Attach the mii driver. */
|
|
error = mii_attach(dev, &sc->miibus, ifp, xae_media_change,
|
|
xae_media_status, BMSR_DEFCAPMASK, sc->phy_addr,
|
|
MII_OFFSET_ANY, 0);
|
|
|
|
if (error != 0) {
|
|
device_printf(dev, "PHY attach failed\n");
|
|
return (ENXIO);
|
|
}
|
|
sc->mii_softc = device_get_softc(sc->miibus);
|
|
|
|
/* Apply vcu118 workaround. */
|
|
if (OF_getproplen(node, "xlnx,vcu118") >= 0)
|
|
xae_phy_fixup(sc);
|
|
|
|
/* All ready to run, attach the ethernet interface. */
|
|
ether_ifattach(ifp, sc->macaddr);
|
|
sc->is_attached = true;
|
|
|
|
xae_rx_enqueue(sc, NUM_RX_MBUF);
|
|
xdma_queue_submit(sc->xchan_rx);
|
|
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
xae_detach(device_t dev)
|
|
{
|
|
struct xae_softc *sc;
|
|
if_t ifp;
|
|
|
|
sc = device_get_softc(dev);
|
|
|
|
KASSERT(mtx_initialized(&sc->mtx), ("%s: mutex not initialized",
|
|
device_get_nameunit(dev)));
|
|
|
|
ifp = sc->ifp;
|
|
|
|
/* Only cleanup if attach succeeded. */
|
|
if (device_is_attached(dev)) {
|
|
XAE_LOCK(sc);
|
|
xae_stop_locked(sc);
|
|
XAE_UNLOCK(sc);
|
|
callout_drain(&sc->xae_callout);
|
|
ether_ifdetach(ifp);
|
|
}
|
|
|
|
if (sc->miibus != NULL)
|
|
device_delete_child(dev, sc->miibus);
|
|
|
|
if (ifp != NULL)
|
|
if_free(ifp);
|
|
|
|
mtx_destroy(&sc->mtx);
|
|
|
|
bus_teardown_intr(dev, sc->res[1], sc->intr_cookie);
|
|
|
|
bus_release_resources(dev, xae_spec, sc->res);
|
|
|
|
xdma_channel_free(sc->xchan_tx);
|
|
xdma_channel_free(sc->xchan_rx);
|
|
xdma_put(sc->xdma_tx);
|
|
xdma_put(sc->xdma_rx);
|
|
|
|
return (0);
|
|
}
|
|
|
|
static void
|
|
xae_miibus_statchg(device_t dev)
|
|
{
|
|
struct xae_softc *sc;
|
|
struct mii_data *mii;
|
|
uint32_t reg;
|
|
|
|
/*
|
|
* Called by the MII bus driver when the PHY establishes
|
|
* link to set the MAC interface registers.
|
|
*/
|
|
|
|
sc = device_get_softc(dev);
|
|
|
|
XAE_ASSERT_LOCKED(sc);
|
|
|
|
mii = sc->mii_softc;
|
|
|
|
if (mii->mii_media_status & IFM_ACTIVE)
|
|
sc->link_is_up = true;
|
|
else
|
|
sc->link_is_up = false;
|
|
|
|
switch (IFM_SUBTYPE(mii->mii_media_active)) {
|
|
case IFM_1000_T:
|
|
case IFM_1000_SX:
|
|
reg = SPEED_1000;
|
|
break;
|
|
case IFM_100_TX:
|
|
reg = SPEED_100;
|
|
break;
|
|
case IFM_10_T:
|
|
reg = SPEED_10;
|
|
break;
|
|
case IFM_NONE:
|
|
sc->link_is_up = false;
|
|
return;
|
|
default:
|
|
sc->link_is_up = false;
|
|
device_printf(dev, "Unsupported media %u\n",
|
|
IFM_SUBTYPE(mii->mii_media_active));
|
|
return;
|
|
}
|
|
|
|
WRITE4(sc, XAE_SPEED, reg);
|
|
}
|
|
|
|
static device_method_t xae_methods[] = {
|
|
DEVMETHOD(device_probe, xae_probe),
|
|
DEVMETHOD(device_attach, xae_attach),
|
|
DEVMETHOD(device_detach, xae_detach),
|
|
|
|
/* MII Interface */
|
|
DEVMETHOD(miibus_readreg, xae_miibus_read_reg),
|
|
DEVMETHOD(miibus_writereg, xae_miibus_write_reg),
|
|
DEVMETHOD(miibus_statchg, xae_miibus_statchg),
|
|
{ 0, 0 }
|
|
};
|
|
|
|
driver_t xae_driver = {
|
|
"xae",
|
|
xae_methods,
|
|
sizeof(struct xae_softc),
|
|
};
|
|
|
|
DRIVER_MODULE(xae, simplebus, xae_driver, 0, 0);
|
|
DRIVER_MODULE(miibus, xae, miibus_driver, 0, 0);
|
|
|
|
MODULE_DEPEND(xae, ether, 1, 1, 1);
|
|
MODULE_DEPEND(xae, miibus, 1, 1, 1);
|