fa081a357e
go into the PLX 9052's interrupt control register and turn on the magic interrupt enable bit. Partial thanks are due to OpenBSD for pointing out that the chip is a PLX 9052 and pointing me to the datasheet PDF.
678 lines
18 KiB
C
678 lines
18 KiB
C
/*
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* Copyright (c) 1997, 1998, 1999
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* Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Bill Paul.
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* 4. Neither the name of the author nor the names of any co-contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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* THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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struct wi_counters {
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u_int32_t wi_tx_unicast_frames;
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u_int32_t wi_tx_multicast_frames;
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u_int32_t wi_tx_fragments;
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u_int32_t wi_tx_unicast_octets;
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u_int32_t wi_tx_multicast_octets;
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u_int32_t wi_tx_deferred_xmits;
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u_int32_t wi_tx_single_retries;
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u_int32_t wi_tx_multi_retries;
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u_int32_t wi_tx_retry_limit;
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u_int32_t wi_tx_discards;
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u_int32_t wi_rx_unicast_frames;
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u_int32_t wi_rx_multicast_frames;
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u_int32_t wi_rx_fragments;
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u_int32_t wi_rx_unicast_octets;
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u_int32_t wi_rx_multicast_octets;
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u_int32_t wi_rx_fcs_errors;
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u_int32_t wi_rx_discards_nobuf;
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u_int32_t wi_tx_discards_wrong_sa;
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u_int32_t wi_rx_WEP_cant_decrypt;
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u_int32_t wi_rx_msg_in_msg_frags;
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u_int32_t wi_rx_msg_in_bad_msg_frags;
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};
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/*
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* Encryption controls. We can enable or disable encryption as
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* well as specify up to 4 encryption keys. We can also specify
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* which of the four keys will be used for transmit encryption.
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*/
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#define WI_RID_ENCRYPTION 0xFC20
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#define WI_RID_AUTHTYPE 0xFC21
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#define WI_RID_DEFLT_CRYPT_KEYS 0xFCB0
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#define WI_RID_TX_CRYPT_KEY 0xFCB1
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#define WI_RID_WEP_AVAIL 0xFD4F
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#define WI_RID_P2_TX_CRYPT_KEY 0xFC23
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#define WI_RID_P2_CRYPT_KEY0 0xFC24
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#define WI_RID_P2_CRYPT_KEY1 0xFC25
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#define WI_RID_P2_CRYPT_KEY2 0xFC26
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#define WI_RID_P2_CRYPT_KEY3 0xFC27
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#define WI_RID_P2_ENCRYPTION 0xFC28
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#define WI_RID_CUR_TX_RATE 0xFD44 /* current TX rate */
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struct wi_key {
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u_int16_t wi_keylen;
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u_int8_t wi_keydat[14];
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};
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struct wi_ltv_keys {
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u_int16_t wi_len;
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u_int16_t wi_type;
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struct wi_key wi_keys[4];
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};
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struct wi_softc {
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struct arpcom arpcom;
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struct ifmedia ifmedia;
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device_t dev;
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int wi_unit;
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struct resource * local;
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int local_rid;
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struct resource * iobase;
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int iobase_rid;
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struct resource * irq;
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int irq_rid;
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struct resource * mem;
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int mem_rid;
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bus_space_handle_t wi_localhandle;
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bus_space_tag_t wi_localtag;
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bus_space_handle_t wi_bhandle;
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bus_space_tag_t wi_btag;
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bus_space_handle_t wi_bmemhandle;
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bus_space_tag_t wi_bmemtag;
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void * wi_intrhand;
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int wi_io_addr;
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int wi_tx_data_id;
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int wi_tx_mgmt_id;
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int wi_gone;
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int wi_if_flags;
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u_int16_t wi_ptype;
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u_int16_t wi_portnum;
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u_int16_t wi_max_data_len;
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u_int16_t wi_rts_thresh;
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u_int16_t wi_ap_density;
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u_int16_t wi_tx_rate;
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u_int16_t wi_create_ibss;
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u_int16_t wi_channel;
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u_int16_t wi_pm_enabled;
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u_int16_t wi_max_sleep;
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char wi_node_name[32];
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char wi_net_name[32];
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char wi_ibss_name[32];
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u_int8_t wi_txbuf[1596];
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struct wi_counters wi_stats;
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int wi_has_wep;
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int wi_use_wep;
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int wi_tx_key;
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struct wi_ltv_keys wi_keys;
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#ifdef WICACHE
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int wi_sigitems;
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struct wi_sigcache wi_sigcache[MAXWICACHE];
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int wi_nextitem;
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#endif
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struct callout_handle wi_stat_ch;
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struct mtx wi_mtx;
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int wi_prism2; /* set to 1 if it uses a Prism II chip */
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};
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#define WI_LOCK(_sc)
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#define WI_UNLOCK(_sc)
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#define WI_TIMEOUT 65536
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#define WI_PORT0 0
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#define WI_PORT1 1
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#define WI_PORT2 2
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#define WI_PORT3 3
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#define WI_PORT4 4
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#define WI_PORT5 5
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#define WI_PCI_LOCALRES 0x14 /* The PLX chip's local registers */
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#define WI_PCI_MEMRES 0x18 /* The PCCard's attribute memory */
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#define WI_PCI_IORES 0x1C /* The PCCard's I/O space */
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#define WI_LOCAL_INTCSR 0x4c
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#define WI_LOCAL_INTEN 0x40
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#define WI_HFA384X_SWSUPPORT0_OFF 0x28
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#define WI_PRISM2STA_MAGIC 0x4A2D
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/* Default port: 0 (only 0 exists on stations) */
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#define WI_DEFAULT_PORT (WI_PORT0 << 8)
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/* Default TX rate: 2Mbps, auto fallback */
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#define WI_DEFAULT_TX_RATE 3
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/* Default network name: empty string implies any */
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#define WI_DEFAULT_NETNAME ""
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#define WI_DEFAULT_AP_DENSITY 1
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#define WI_DEFAULT_RTS_THRESH 2347
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#define WI_DEFAULT_DATALEN 2304
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#define WI_DEFAULT_CREATE_IBSS 0
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#define WI_DEFAULT_PM_ENABLED 0
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#define WI_DEFAULT_MAX_SLEEP 100
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#define WI_DEFAULT_NODENAME "FreeBSD WaveLAN/IEEE node"
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#define WI_DEFAULT_IBSS "FreeBSD IBSS"
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#define WI_DEFAULT_CHAN 3
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/*
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* register space access macros
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*/
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#define CSR_WRITE_4(sc, reg, val) \
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bus_space_write_4(sc->wi_btag, sc->wi_bhandle, reg, val)
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#define CSR_WRITE_2(sc, reg, val) \
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bus_space_write_2(sc->wi_btag, sc->wi_bhandle, reg, val)
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#define CSR_WRITE_1(sc, reg, val) \
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bus_space_write_1(sc->wi_btag, sc->wi_bhandle, reg, val)
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#define CSR_READ_4(sc, reg) \
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bus_space_read_4(sc->wi_btag, sc->wi_bhandle, reg)
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#define CSR_READ_2(sc, reg) \
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bus_space_read_2(sc->wi_btag, sc->wi_bhandle, reg)
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#define CSR_READ_1(sc, reg) \
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bus_space_read_1(sc->wi_btag, sc->wi_bhandle, reg)
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#define CSM_WRITE_1(sc, off, val) \
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bus_space_write_1(sc->wi_bmemtag, sc->wi_bmemhandle, off, val)
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#define CSM_READ_1(sc, off) \
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bus_space_read_1(sc->wi_bmemtag, sc->wi_bmemhandle, off)
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/*
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* The WaveLAN/IEEE cards contain an 802.11 MAC controller which Lucent
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* calls 'Hermes.' In typical fashion, getting documentation about this
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* controller is about as easy as squeezing blood from a stone. Here
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* is more or less what I know:
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*
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* - The Hermes controller is firmware driven, and the host interacts
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* with the Hermes via a firmware interface, which can change.
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*
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* - The Hermes is described in a document called: "Hermes Firmware
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* WaveLAN/IEEE Station Functions," document #010245, which of course
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* Lucent will not release without an NDA.
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*
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* - Lucent has created a library called HCF (Hardware Control Functions)
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* though which it wants developers to interact with the card. The HCF
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* is needlessly complex, ill conceived and badly documented. Actually,
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* the comments in the HCP code itself aren't bad, but the publically
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* available manual that comes with it is awful, probably due largely to
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* the fact that it has been emasculated in order to hide information
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* that Lucent wants to keep proprietary. The purpose of the HCF seems
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* to be to insulate the driver programmer from the Hermes itself so that
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* Lucent has an excuse not to release programming in for it.
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*
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* - Lucent only makes available documentation and code for 'HCF Light'
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* which is a stripped down version of HCF with certain features not
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* implemented, most notably support for 802.11 frames.
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*
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* - The HCF code which I have seen blows goats. Whoever decided to
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* use a 132 column format should be shot.
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*
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* Rather than actually use the Lucent HCF library, I have stripped all
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* the useful information from it and used it to create a driver in the
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* usual BSD form. Note: I don't want to hear anybody whining about the
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* fact that the Lucent code is GPLed and mine isn't. I did not actually
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* put any of Lucent's code in this driver: I only used it as a reference
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* to obtain information about the underlying hardware. The Hermes
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* programming interface is not GPLed, so bite me.
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*/
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/*
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* Size of Hermes I/O space.
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*/
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#define WI_IOSIZ 0x40
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/*
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* Hermes register definitions and what little I know about them.
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*/
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/* Hermes command/status registers. */
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#define WI_COMMAND 0x00
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#define WI_PARAM0 0x02
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#define WI_PARAM1 0x04
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#define WI_PARAM2 0x06
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#define WI_STATUS 0x08
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#define WI_RESP0 0x0A
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#define WI_RESP1 0x0C
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#define WI_RESP2 0x0E
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/* Command register values. */
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#define WI_CMD_BUSY 0x8000 /* busy bit */
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#define WI_CMD_INI 0x0000 /* initialize */
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#define WI_CMD_ENABLE 0x0001 /* enable */
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#define WI_CMD_DISABLE 0x0002 /* disable */
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#define WI_CMD_DIAG 0x0003
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#define WI_CMD_ALLOC_MEM 0x000A /* allocate NIC memory */
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#define WI_CMD_TX 0x000B /* transmit */
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#define WI_CMD_NOTIFY 0x0010
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#define WI_CMD_INQUIRE 0x0011
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#define WI_CMD_ACCESS 0x0021
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#define WI_CMD_PROGRAM 0x0022
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#define WI_CMD_CODE_MASK 0x003F
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/*
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* Reclaim qualifier bit, applicable to the
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* TX and INQUIRE commands.
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*/
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#define WI_RECLAIM 0x0100 /* reclaim NIC memory */
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/*
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* ACCESS command qualifier bits.
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*/
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#define WI_ACCESS_READ 0x0000
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#define WI_ACCESS_WRITE 0x0100
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/*
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* PROGRAM command qualifier bits.
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*/
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#define WI_PROGRAM_DISABLE 0x0000
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#define WI_PROGRAM_ENABLE_RAM 0x0100
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#define WI_PROGRAM_ENABLE_NVRAM 0x0200
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#define WI_PROGRAM_NVRAM 0x0300
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/* Status register values */
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#define WI_STAT_CMD_CODE 0x003F
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#define WI_STAT_DIAG_ERR 0x0100
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#define WI_STAT_INQ_ERR 0x0500
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#define WI_STAT_CMD_RESULT 0x7F00
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/* memory handle management registers */
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#define WI_INFO_FID 0x10
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#define WI_RX_FID 0x20
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#define WI_ALLOC_FID 0x22
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#define WI_TX_CMP_FID 0x24
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/*
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* Buffer Access Path (BAP) registers.
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* These are I/O channels. I believe you can use each one for
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* any desired purpose independently of the other. In general
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* though, we use BAP1 for reading and writing LTV records and
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* reading received data frames, and BAP0 for writing transmit
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* frames. This is a convention though, not a rule.
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*/
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#define WI_SEL0 0x18
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#define WI_SEL1 0x1A
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#define WI_OFF0 0x1C
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#define WI_OFF1 0x1E
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#define WI_DATA0 0x36
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#define WI_DATA1 0x38
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#define WI_BAP0 WI_DATA0
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#define WI_BAP1 WI_DATA1
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#define WI_OFF_BUSY 0x8000
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#define WI_OFF_ERR 0x4000
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#define WI_OFF_DATAOFF 0x0FFF
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/* Event registers */
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#define WI_EVENT_STAT 0x30 /* Event status */
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#define WI_INT_EN 0x32 /* Interrupt enable/disable */
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#define WI_EVENT_ACK 0x34 /* Ack event */
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/* Events */
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#define WI_EV_TICK 0x8000 /* aux timer tick */
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#define WI_EV_RES 0x4000 /* controller h/w error (time out) */
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#define WI_EV_INFO_DROP 0x2000 /* no RAM to build unsolicited frame */
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#define WI_EV_NO_CARD 0x0800 /* card removed (hunh?) */
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#define WI_EV_DUIF_RX 0x0400 /* wavelan management packet received */
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#define WI_EV_INFO 0x0080 /* async info frame */
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#define WI_EV_CMD 0x0010 /* command completed */
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#define WI_EV_ALLOC 0x0008 /* async alloc/reclaim completed */
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#define WI_EV_TX_EXC 0x0004 /* async xmit completed with failure */
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#define WI_EV_TX 0x0002 /* async xmit completed succesfully */
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#define WI_EV_RX 0x0001 /* async rx completed */
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#define WI_INTRS \
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(WI_EV_RX|WI_EV_TX|WI_EV_TX_EXC|WI_EV_ALLOC|WI_EV_INFO|WI_EV_INFO_DROP)
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/* Host software registers */
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#define WI_SW0 0x28
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#define WI_SW1 0x2A
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#define WI_SW2 0x2C
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#define WI_SW3 0x2E
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#define WI_CNTL 0x14
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#define WI_CNTL_AUX_ENA 0xC000
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#define WI_CNTL_AUX_ENA_STAT 0xC000
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#define WI_CNTL_AUX_DIS_STAT 0x0000
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#define WI_CNTL_AUX_ENA_CNTL 0x8000
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#define WI_CNTL_AUX_DIS_CNTL 0x4000
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#define WI_AUX_PAGE 0x3A
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#define WI_AUX_OFFSET 0x3C
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#define WI_AUX_DATA 0x3E
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#define WI_COR_OFFSET 0x3e0
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#define WI_COR_VALUE 0x41
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/*
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* One form of communication with the Hermes is with what Lucent calls
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* LTV records, where LTV stands for Length, Type and Value. The length
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* and type are 16 bits and are in native byte order. The value is in
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* multiples of 16 bits and is in little endian byte order.
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*/
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struct wi_ltv_gen {
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u_int16_t wi_len;
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u_int16_t wi_type;
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u_int16_t wi_val;
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};
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struct wi_ltv_str {
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u_int16_t wi_len;
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u_int16_t wi_type;
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u_int16_t wi_str[17];
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};
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#define WI_SETVAL(recno, val) \
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do { \
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struct wi_ltv_gen g; \
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\
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g.wi_len = 2; \
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g.wi_type = recno; \
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g.wi_val = val; \
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wi_write_record(sc, &g); \
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} while (0)
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#define WI_SETSTR(recno, str) \
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do { \
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struct wi_ltv_str s; \
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int l; \
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\
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l = (strlen(str) + 1) & ~0x1; \
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bzero((char *)&s, sizeof(s)); \
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s.wi_len = (l / 2) + 2; \
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s.wi_type = recno; \
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s.wi_str[0] = strlen(str); \
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bcopy(str, (char *)&s.wi_str[1], strlen(str)); \
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wi_write_record(sc, (struct wi_ltv_gen *)&s); \
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} while (0)
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/*
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* Download buffer location and length (0xFD01).
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*/
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#define WI_RID_DNLD_BUF 0xFD01
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struct wi_ltv_dnld_buf {
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u_int16_t wi_len;
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u_int16_t wi_type;
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u_int16_t wi_buf_pg; /* page addr of intermediate dl buf*/
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u_int16_t wi_buf_off; /* offset of idb */
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u_int16_t wi_buf_len; /* len of idb */
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};
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/*
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* Mem sizes (0xFD02).
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*/
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#define WI_RID_MEMSZ 0xFD02
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struct wi_ltv_memsz {
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u_int16_t wi_len;
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u_int16_t wi_type;
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u_int16_t wi_mem_ram;
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u_int16_t wi_mem_nvram;
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};
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/*
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* List of intended regulatory domains (0xFD11).
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*/
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#define WI_RID_DOMAINS 0xFD11
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struct wi_ltv_domains {
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u_int16_t wi_len;
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u_int16_t wi_type;
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u_int16_t wi_domains[6];
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};
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/*
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* CIS struct (0xFD13).
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*/
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#define WI_RID_CIS 0xFD13
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struct wi_ltv_cis {
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u_int16_t wi_len;
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u_int16_t wi_type;
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u_int16_t wi_cis[240];
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};
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/*
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* Communications quality (0xFD43).
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*/
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#define WI_RID_COMMQUAL 0xFD43
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struct wi_ltv_commqual {
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u_int16_t wi_len;
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u_int16_t wi_type;
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u_int16_t wi_coms_qual;
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u_int16_t wi_sig_lvl;
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u_int16_t wi_noise_lvl;
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};
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/*
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* Actual system scale thresholds (0xFD46).
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*/
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#define WI_RID_SYSTEM_SCALE 0xFC06
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#define WI_RID_SCALETHRESH 0xFD46
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struct wi_ltv_scalethresh {
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u_int16_t wi_len;
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u_int16_t wi_type;
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u_int16_t wi_energy_detect;
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u_int16_t wi_carrier_detect;
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u_int16_t wi_defer;
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u_int16_t wi_cell_search;
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u_int16_t wi_out_of_range;
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u_int16_t wi_delta_snr;
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};
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/*
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* PCF info struct (0xFD87).
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*/
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#define WI_RID_PCF 0xFD87
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struct wi_ltv_pcf {
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u_int16_t wi_len;
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u_int16_t wi_type;
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u_int16_t wi_energy_detect;
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u_int16_t wi_carrier_detect;
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u_int16_t wi_defer;
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u_int16_t wi_cell_search;
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u_int16_t wi_range;
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};
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/*
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* Connection control characteristics.
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* 1 == Basic Service Set (BSS)
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* 2 == Wireless Distribudion System (WDS)
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* 3 == Pseudo IBSS
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*/
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#define WI_RID_PORTTYPE 0xFC00
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#define WI_PORTTYPE_BSS 0x1
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#define WI_PORTTYPE_WDS 0x2
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#define WI_PORTTYPE_ADHOC 0x3
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/*
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* Mac addresses.
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*/
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#define WI_RID_MAC_NODE 0xFC01
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#define WI_RID_MAC_WDS 0xFC08
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struct wi_ltv_macaddr {
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u_int16_t wi_len;
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u_int16_t wi_type;
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u_int16_t wi_mac_addr[3];
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};
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/*
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* Station set identification (SSID).
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*/
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#define WI_RID_DESIRED_SSID 0xFC02
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#define WI_RID_OWN_SSID 0xFC04
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struct wi_ltv_ssid {
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u_int16_t wi_len;
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u_int16_t wi_type;
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u_int16_t wi_id[17];
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};
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/*
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* Set communications channel (radio frequency).
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*/
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#define WI_RID_OWN_CHNL 0xFC03
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/*
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* Frame data size.
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*/
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#define WI_RID_MAX_DATALEN 0xFC07
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/*
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* ESS power management enable
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*/
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#define WI_RID_PM_ENABLED 0xFC09
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/*
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* ESS max PM sleep internal
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*/
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#define WI_RID_MAX_SLEEP 0xFC0C
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/*
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* Set our station name.
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*/
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#define WI_RID_NODENAME 0xFC0E
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struct wi_ltv_nodename {
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u_int16_t wi_len;
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u_int16_t wi_type;
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u_int16_t wi_nodename[17];
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};
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/*
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* Multicast addresses to be put in filter. We're
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* allowed up to 16 addresses in the filter.
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*/
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#define WI_RID_MCAST 0xFC80
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struct wi_ltv_mcast {
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u_int16_t wi_len;
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u_int16_t wi_type;
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struct ether_addr wi_mcast[16];
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};
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/*
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* Create IBSS.
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*/
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#define WI_RID_CREATE_IBSS 0xFC81
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#define WI_RID_FRAG_THRESH 0xFC82
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#define WI_RID_RTS_THRESH 0xFC83
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/*
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* TX rate control
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* 0 == Fixed 1mbps
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* 1 == Fixed 2mbps
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* 2 == auto fallback
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*/
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#define WI_RID_TX_RATE 0xFC84
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/*
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* promiscuous mode.
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*/
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#define WI_RID_PROMISC 0xFC85
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/*
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* Auxiliary Timer tick interval
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*/
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#define WI_RID_TICK_TIME 0xFCE0
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/*
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* Information frame types.
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*/
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#define WI_INFO_NOTIFY 0xF000 /* Handover address */
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#define WI_INFO_COUNTERS 0xF100 /* Statistics counters */
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#define WI_INFO_SCAN_RESULTS 0xF101 /* Scan results */
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#define WI_INFO_LINK_STAT 0xF200 /* Link status */
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#define WI_INFO_ASSOC_STAT 0xF201 /* Association status */
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/*
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* Hermes transmit/receive frame structure
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*/
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struct wi_frame {
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u_int16_t wi_status; /* 0x00 */
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u_int16_t wi_rsvd0; /* 0x02 */
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u_int16_t wi_rsvd1; /* 0x04 */
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u_int16_t wi_q_info; /* 0x06 */
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u_int16_t wi_rsvd2; /* 0x08 */
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u_int16_t wi_rsvd3; /* 0x0A */
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u_int16_t wi_tx_ctl; /* 0x0C */
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u_int16_t wi_frame_ctl; /* 0x0E */
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u_int16_t wi_id; /* 0x10 */
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u_int8_t wi_addr1[6]; /* 0x12 */
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u_int8_t wi_addr2[6]; /* 0x18 */
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u_int8_t wi_addr3[6]; /* 0x1E */
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u_int16_t wi_seq_ctl; /* 0x24 */
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u_int8_t wi_addr4[6]; /* 0x26 */
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u_int16_t wi_dat_len; /* 0x2C */
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u_int8_t wi_dst_addr[6]; /* 0x2E */
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u_int8_t wi_src_addr[6]; /* 0x34 */
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u_int16_t wi_len; /* 0x3A */
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u_int16_t wi_dat[3]; /* 0x3C */ /* SNAP header */
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u_int16_t wi_type; /* 0x42 */
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};
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#define WI_802_3_OFFSET 0x2E
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#define WI_802_11_OFFSET 0x44
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#define WI_802_11_OFFSET_RAW 0x3C
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#define WI_STAT_BADCRC 0x0001
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#define WI_STAT_UNDECRYPTABLE 0x0002
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#define WI_STAT_ERRSTAT 0x0003
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#define WI_STAT_MAC_PORT 0x0700
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#define WI_STAT_1042 0x2000 /* RFC1042 encoded */
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#define WI_STAT_TUNNEL 0x4000 /* Bridge-tunnel encoded */
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#define WI_STAT_WMP_MSG 0x6000 /* WaveLAN-II management protocol */
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#define WI_RXSTAT_MSG_TYPE 0xE000
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#define WI_ENC_TX_802_3 0x00
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#define WI_ENC_TX_802_11 0x11
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#define WI_ENC_TX_E_II 0x0E
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#define WI_ENC_TX_1042 0x00
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#define WI_ENC_TX_TUNNEL 0xF8
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#define WI_TXCNTL_MACPORT 0x00FF
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#define WI_TXCNTL_STRUCTTYPE 0xFF00
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/*
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* SNAP (sub-network access protocol) constants for transmission
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* of IP datagrams over IEEE 802 networks, taken from RFC1042.
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* We need these for the LLC/SNAP header fields in the TX/RX frame
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* structure.
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*/
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#define WI_SNAP_K1 0xaa /* assigned global SAP for SNAP */
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#define WI_SNAP_K2 0x00
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#define WI_SNAP_CONTROL 0x03 /* unnumbered information format */
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#define WI_SNAP_WORD0 (WI_SNAP_K1 | (WI_SNAP_K1 << 8))
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#define WI_SNAP_WORD1 (WI_SNAP_K2 | (WI_SNAP_CONTROL << 8))
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#define WI_SNAPHDR_LEN 0x6
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