7b185ef809
Several new fine-grained locks. New FAST_INTR() methods: - separate simplelock for FAST_INTR, no more giant lock. - FAST_INTR()s no longer checks ipending on way out of ISR. sio made MP-safe (I hope).
360 lines
9.5 KiB
ArmAsm
360 lines
9.5 KiB
ArmAsm
/*-
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* Copyright (c) 1989, 1990 William F. Jolitz.
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* Copyright (c) 1990 The Regents of the University of California.
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* All rights reserved.
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*
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* This code is derived from software contributed to Berkeley by
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* William Jolitz.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* @(#)ipl.s
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*
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* $Id: ipl.s,v 1.8 1997/08/10 21:17:55 fsmp Exp $
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*/
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/*
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* AT/386
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* Vector interrupt control section
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*/
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.data
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ALIGN_DATA
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/* current priority (all off) */
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.globl _cpl
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_cpl: .long HWI_MASK | SWI_MASK
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#ifndef APIC_IO
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/* interrupt mask enable (all h/w off) */
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.globl _imen
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_imen: .long HWI_MASK
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#endif /* APIC_IO */
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.globl _tty_imask
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_tty_imask: .long 0
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.globl _bio_imask
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_bio_imask: .long 0
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.globl _net_imask
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_net_imask: .long 0
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.globl _soft_imask
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_soft_imask: .long SWI_MASK
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.globl _softnet_imask
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_softnet_imask: .long SWI_NET_MASK
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.globl _softtty_imask
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_softtty_imask: .long SWI_TTY_MASK
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.globl _ipending
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/* pending interrupts blocked by splxxx() */
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_ipending: .long 0
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/* set with bits for which queue to service */
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.globl _netisr
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_netisr: .long 0
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.globl _netisrs
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_netisrs:
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.long dummynetisr, dummynetisr, dummynetisr, dummynetisr
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.long dummynetisr, dummynetisr, dummynetisr, dummynetisr
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.long dummynetisr, dummynetisr, dummynetisr, dummynetisr
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.long dummynetisr, dummynetisr, dummynetisr, dummynetisr
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.long dummynetisr, dummynetisr, dummynetisr, dummynetisr
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.long dummynetisr, dummynetisr, dummynetisr, dummynetisr
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.long dummynetisr, dummynetisr, dummynetisr, dummynetisr
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.long dummynetisr, dummynetisr, dummynetisr, dummynetisr
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.text
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/*
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* Handle return from interrupts, traps and syscalls.
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*/
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SUPERALIGN_TEXT
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_doreti:
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FAKE_MCOUNT(_bintr) /* init "from" _bintr -> _doreti */
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addl $4,%esp /* discard unit number */
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popl %eax /* cpl to restore */
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doreti_next:
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/*
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* Check for pending HWIs and SWIs atomically with restoring cpl
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* and exiting. The check has to be atomic with exiting to stop
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* (ipending & ~cpl) changing from zero to nonzero while we're
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* looking at it (this wouldn't be fatal but it would increase
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* interrupt latency). Restoring cpl has to be atomic with exiting
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* so that the stack cannot pile up (the nesting level of interrupt
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* handlers is limited by the number of bits in cpl).
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*/
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movl %eax,%ecx
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notl %ecx
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cli
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andl _ipending,%ecx
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jne doreti_unpend
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doreti_exit:
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movl %eax,_cpl
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decb _intr_nesting_level
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MEXITCOUNT
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#ifdef VM86
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/*
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* XXX
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* Sometimes when attempting to return to vm86 mode, cpl is not
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* being reset to 0, so here we force it to 0 before returning to
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* vm86 mode. doreti_stop is a convenient place to set a breakpoint.
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* When the cpl problem is solved, this code can disappear.
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*/
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cmpl $0,_cpl
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je 1f
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testl $PSL_VM,TF_EFLAGS(%esp)
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je 1f
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doreti_stop:
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movl $0,_cpl
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nop
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1:
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#endif /* VM86 */
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#ifdef SMP
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/* release the kernel lock */
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pushl $_mp_lock /* GIANT_LOCK */
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call _MPrellock
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add $4, %esp
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#endif /* SMP */
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.globl doreti_popl_es
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doreti_popl_es:
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popl %es
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.globl doreti_popl_ds
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doreti_popl_ds:
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popl %ds
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popal
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addl $8,%esp
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.globl doreti_iret
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doreti_iret:
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iret
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ALIGN_TEXT
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.globl doreti_iret_fault
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doreti_iret_fault:
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subl $8,%esp
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pushal
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pushl %ds
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.globl doreti_popl_ds_fault
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doreti_popl_ds_fault:
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pushl %es
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.globl doreti_popl_es_fault
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doreti_popl_es_fault:
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movl $0,4+4+32+4(%esp) /* XXX should be the error code */
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movl $T_PROTFLT,4+4+32+0(%esp)
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jmp alltraps_with_regs_pushed
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ALIGN_TEXT
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doreti_unpend:
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/*
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* Enabling interrupts is safe because we haven't restored cpl yet.
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* The locking from the "btrl" test is probably no longer necessary.
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* We won't miss any new pending interrupts because we will check
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* for them again.
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*/
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sti
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bsfl %ecx,%ecx /* slow, but not worth optimizing */
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MPLOCKED btrl %ecx, _ipending
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jnc doreti_next /* some intr cleared memory copy */
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movl ihandlers(,%ecx,4),%edx
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testl %edx,%edx
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je doreti_next /* "can't happen" */
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cmpl $NHWI,%ecx
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jae doreti_swi
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cli
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movl %eax,_cpl
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MEXITCOUNT
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jmp %edx
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ALIGN_TEXT
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doreti_swi:
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pushl %eax
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/*
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* The SWI_AST handler has to run at cpl = SWI_AST_MASK and the
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* SWI_CLOCK handler at cpl = SWI_CLOCK_MASK, so we have to restore
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* all the h/w bits in cpl now and have to worry about stack growth.
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* The worst case is currently (30 Jan 1994) 2 SWI handlers nested
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* in dying interrupt frames and about 12 HWIs nested in active
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* interrupt frames. There are only 4 different SWIs and the HWI
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* and SWI masks limit the nesting further.
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*/
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orl imasks(,%ecx,4),%eax
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movl %eax,_cpl
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call %edx
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popl %eax
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jmp doreti_next
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ALIGN_TEXT
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swi_ast:
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addl $8,%esp /* discard raddr & cpl to get trap frame */
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testb $SEL_RPL_MASK,TRAPF_CS_OFF(%esp)
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je swi_ast_phantom
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swi_ast_user:
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movl $T_ASTFLT,(2+8+0)*4(%esp)
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movb $0,_intr_nesting_level /* finish becoming a trap handler */
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call _trap
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subl %eax,%eax /* recover cpl */
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movb $1,_intr_nesting_level /* for doreti_next to decrement */
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jmp doreti_next
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ALIGN_TEXT
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swi_ast_phantom:
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#ifdef VM86
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/*
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* check for ast from vm86 mode. Placed down here so the jumps do
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* not get taken for mainline code.
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*/
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testl $PSL_VM,TF_EFLAGS(%esp)
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jne swi_ast_user
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#endif /* VM86 */
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/*
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* These happen when there is an interrupt in a trap handler before
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* ASTs can be masked or in an lcall handler before they can be
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* masked or after they are unmasked. They could be avoided for
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* trap entries by using interrupt gates, and for lcall exits by
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* using by using cli, but they are unavoidable for lcall entries.
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*/
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cli
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MPLOCKED orl $SWI_AST_PENDING, _ipending
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subl %eax,%eax
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jmp doreti_exit /* SWI_AST is highest so we must be done */
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/*
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* Interrupt priority mechanism
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* -- soft splXX masks with group mechanism (cpl)
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* -- h/w masks for currently active or unused interrupts (imen)
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* -- ipending = active interrupts currently masked by cpl
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*/
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ENTRY(splz)
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/*
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* The caller has restored cpl and checked that (ipending & ~cpl)
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* is nonzero. We have to repeat the check since if there is an
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* interrupt while we're looking, _doreti processing for the
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* interrupt will handle all the unmasked pending interrupts
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* because we restored early. We're repeating the calculation
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* of (ipending & ~cpl) anyway so that the caller doesn't have
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* to pass it, so this only costs one "jne". "bsfl %ecx,%ecx"
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* is undefined when %ecx is 0 so we can't rely on the secondary
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* btrl tests.
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*/
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movl _cpl,%eax
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splz_next:
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/*
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* We don't need any locking here. (ipending & ~cpl) cannot grow
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* while we're looking at it - any interrupt will shrink it to 0.
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*/
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movl %eax,%ecx
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notl %ecx
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andl _ipending,%ecx
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jne splz_unpend
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ret
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ALIGN_TEXT
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splz_unpend:
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bsfl %ecx,%ecx
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MPLOCKED btrl %ecx, _ipending
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jnc splz_next
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movl ihandlers(,%ecx,4),%edx
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testl %edx,%edx
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je splz_next /* "can't happen" */
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cmpl $NHWI,%ecx
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jae splz_swi
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/*
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* We would prefer to call the intr handler directly here but that
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* doesn't work for badly behaved handlers that want the interrupt
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* frame. Also, there's a problem determining the unit number.
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* We should change the interface so that the unit number is not
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* determined at config time.
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*/
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jmp *_vec(,%ecx,4)
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ALIGN_TEXT
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splz_swi:
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cmpl $SWI_AST,%ecx
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je splz_next /* "can't happen" */
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pushl %eax
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orl imasks(,%ecx,4),%eax
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movl %eax,_cpl
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call %edx
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popl %eax
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movl %eax,_cpl
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jmp splz_next
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ALIGN_TEXT
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swi_net:
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MCOUNT
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bsfl _netisr,%eax
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je swi_net_done
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swi_net_more:
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btrl %eax,_netisr
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jnc swi_net_next
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call *_netisrs(,%eax,4)
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swi_net_next:
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bsfl _netisr,%eax
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jne swi_net_more
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swi_net_done:
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ret
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ALIGN_TEXT
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dummynetisr:
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MCOUNT
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ret
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/*
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* XXX there should be a registration function to put the handler for the
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* attached driver directly in ihandlers. Then this function will go away.
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*/
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ALIGN_TEXT
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swi_tty:
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MCOUNT
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#include "cy.h"
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#if NCY > 0
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call _cypoll
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#endif
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#include "rc.h"
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#if NRC > 0
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call _rcpoll
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#endif
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#include "sio.h"
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#if NSIO > 0
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jmp _siopoll
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#else
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ret
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#endif
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#ifdef APIC_IO
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#include "i386/isa/apic_ipl.s"
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#else
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#include "i386/isa/icu_ipl.s"
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#endif /* APIC_IO */
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