693 lines
15 KiB
ArmAsm
693 lines
15 KiB
ArmAsm
/*
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* from: vector.s, 386BSD 0.1 unknown origin
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* $FreeBSD$
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*/
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#include <machine/apic.h>
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#include <machine/smp.h>
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#include "i386/isa/intr_machdep.h"
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/* convert an absolute IRQ# into a bitmask */
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#define IRQ_BIT(irq_num) (1 << (irq_num))
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/* make an index into the IO APIC from the IRQ# */
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#define REDTBL_IDX(irq_num) (0x10 + ((irq_num) * 2))
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/*
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*
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*/
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#define PUSH_FRAME \
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pushl $0 ; /* dummy error code */ \
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pushl $0 ; /* dummy trap type */ \
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pushal ; \
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pushl %ds ; /* save data and extra segments ... */ \
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pushl %es ; \
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pushl %fs
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#define POP_FRAME \
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popl %fs ; \
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popl %es ; \
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popl %ds ; \
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popal ; \
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addl $4+4,%esp
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/*
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* Macros for interrupt entry, call to handler, and exit.
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*/
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#define FAST_INTR(irq_num, vec_name) \
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.text ; \
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SUPERALIGN_TEXT ; \
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IDTVEC(vec_name) ; \
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PUSH_FRAME ; \
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movl $KDSEL,%eax ; \
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mov %ax,%ds ; \
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mov %ax,%es ; \
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movl $KPSEL,%eax ; \
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mov %ax,%fs ; \
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FAKE_MCOUNT(13*4(%esp)) ; \
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incb PCPU(INTR_NESTING_LEVEL) ; \
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pushl _intr_unit + (irq_num) * 4 ; \
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call *_intr_handler + (irq_num) * 4 ; /* do the work ASAP */ \
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addl $4, %esp ; \
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movl $0, _lapic+LA_EOI ; \
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lock ; \
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incl _cnt+V_INTR ; /* book-keeping can wait */ \
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movl _intr_countp + (irq_num) * 4, %eax ; \
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lock ; \
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incl (%eax) ; \
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MEXITCOUNT ; \
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jmp _doreti
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#define IOAPICADDR(irq_num) CNAME(int_to_apicintpin) + 16 * (irq_num) + 8
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#define REDIRIDX(irq_num) CNAME(int_to_apicintpin) + 16 * (irq_num) + 12
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#define MASK_IRQ(irq_num) \
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IMASK_LOCK ; /* into critical reg */ \
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testl $IRQ_BIT(irq_num), _apic_imen ; \
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jne 7f ; /* masked, don't mask */ \
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orl $IRQ_BIT(irq_num), _apic_imen ; /* set the mask bit */ \
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movl IOAPICADDR(irq_num), %ecx ; /* ioapic addr */ \
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movl REDIRIDX(irq_num), %eax ; /* get the index */ \
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movl %eax, (%ecx) ; /* write the index */ \
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movl IOAPIC_WINDOW(%ecx), %eax ; /* current value */ \
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orl $IOART_INTMASK, %eax ; /* set the mask */ \
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movl %eax, IOAPIC_WINDOW(%ecx) ; /* new value */ \
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7: ; /* already masked */ \
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IMASK_UNLOCK
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/*
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* Test to see whether we are handling an edge or level triggered INT.
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* Level-triggered INTs must still be masked as we don't clear the source,
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* and the EOI cycle would cause redundant INTs to occur.
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*/
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#define MASK_LEVEL_IRQ(irq_num) \
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testl $IRQ_BIT(irq_num), _apic_pin_trigger ; \
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jz 9f ; /* edge, don't mask */ \
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MASK_IRQ(irq_num) ; \
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9:
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#ifdef APIC_INTR_REORDER
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#define EOI_IRQ(irq_num) \
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movl _apic_isrbit_location + 8 * (irq_num), %eax ; \
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movl (%eax), %eax ; \
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testl _apic_isrbit_location + 4 + 8 * (irq_num), %eax ; \
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jz 9f ; /* not active */ \
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movl $0, _lapic+LA_EOI ; \
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APIC_ITRACE(apic_itrace_eoi, irq_num, APIC_ITRACE_EOI) ; \
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9:
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#else
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#define EOI_IRQ(irq_num) \
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testl $IRQ_BIT(irq_num), _lapic+LA_ISR1; \
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jz 9f ; /* not active */ \
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movl $0, _lapic+LA_EOI; \
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APIC_ITRACE(apic_itrace_eoi, irq_num, APIC_ITRACE_EOI) ; \
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9:
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#endif
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/*
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* Test to see if the source is currently masked, clear if so.
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*/
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#define UNMASK_IRQ(irq_num) \
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IMASK_LOCK ; /* into critical reg */ \
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testl $IRQ_BIT(irq_num), _apic_imen ; \
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je 7f ; /* bit clear, not masked */ \
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andl $~IRQ_BIT(irq_num), _apic_imen ;/* clear mask bit */ \
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movl IOAPICADDR(irq_num), %ecx ; /* ioapic addr */ \
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movl REDIRIDX(irq_num), %eax ; /* get the index */ \
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movl %eax, (%ecx) ; /* write the index */ \
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movl IOAPIC_WINDOW(%ecx), %eax ; /* current value */ \
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andl $~IOART_INTMASK, %eax ; /* clear the mask */ \
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movl %eax, IOAPIC_WINDOW(%ecx) ; /* new value */ \
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7: ; /* already unmasked */ \
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IMASK_UNLOCK
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#ifdef APIC_INTR_DIAGNOSTIC
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#ifdef APIC_INTR_DIAGNOSTIC_IRQ
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log_intr_event:
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pushf
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cli
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pushl $CNAME(apic_itrace_debuglock)
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call CNAME(s_lock_np)
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addl $4, %esp
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movl CNAME(apic_itrace_debugbuffer_idx), %ecx
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andl $32767, %ecx
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movl PCPU(CPUID), %eax
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shll $8, %eax
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orl 8(%esp), %eax
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movw %ax, CNAME(apic_itrace_debugbuffer)(,%ecx,2)
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incl %ecx
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andl $32767, %ecx
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movl %ecx, CNAME(apic_itrace_debugbuffer_idx)
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pushl $CNAME(apic_itrace_debuglock)
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call CNAME(s_unlock_np)
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addl $4, %esp
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popf
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ret
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#define APIC_ITRACE(name, irq_num, id) \
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lock ; /* MP-safe */ \
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incl CNAME(name) + (irq_num) * 4 ; \
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pushl %eax ; \
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pushl %ecx ; \
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pushl %edx ; \
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movl $(irq_num), %eax ; \
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cmpl $APIC_INTR_DIAGNOSTIC_IRQ, %eax ; \
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jne 7f ; \
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pushl $id ; \
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call log_intr_event ; \
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addl $4, %esp ; \
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7: ; \
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popl %edx ; \
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popl %ecx ; \
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popl %eax
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#else
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#define APIC_ITRACE(name, irq_num, id) \
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lock ; /* MP-safe */ \
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incl CNAME(name) + (irq_num) * 4
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#endif
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#define APIC_ITRACE_ENTER 1
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#define APIC_ITRACE_EOI 2
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#define APIC_ITRACE_TRYISRLOCK 3
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#define APIC_ITRACE_GOTISRLOCK 4
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#define APIC_ITRACE_ENTER2 5
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#define APIC_ITRACE_LEAVE 6
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#define APIC_ITRACE_UNMASK 7
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#define APIC_ITRACE_ACTIVE 8
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#define APIC_ITRACE_MASKED 9
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#define APIC_ITRACE_NOISRLOCK 10
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#define APIC_ITRACE_MASKED2 11
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#define APIC_ITRACE_SPLZ 12
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#define APIC_ITRACE_DORETI 13
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#else
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#define APIC_ITRACE(name, irq_num, id)
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#endif
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/*
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* Slow, threaded interrupts.
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*
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* XXX Most of the parameters here are obsolete. Fix this when we're
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* done.
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* XXX we really shouldn't return via doreti if we just schedule the
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* interrupt handler and don't run anything. We could just do an
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* iret. FIXME.
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*/
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#define INTR(irq_num, vec_name, maybe_extra_ipending) \
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.text ; \
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SUPERALIGN_TEXT ; \
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/* _XintrNN: entry point used by IDT/HWIs & splz_unpend via _vec[]. */ \
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IDTVEC(vec_name) ; \
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PUSH_FRAME ; \
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movl $KDSEL, %eax ; /* reload with kernel's data segment */ \
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mov %ax, %ds ; \
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mov %ax, %es ; \
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movl $KPSEL, %eax ; \
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mov %ax, %fs ; \
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; \
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maybe_extra_ipending ; \
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; \
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APIC_ITRACE(apic_itrace_enter, irq_num, APIC_ITRACE_ENTER) ; \
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; \
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MASK_LEVEL_IRQ(irq_num) ; \
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EOI_IRQ(irq_num) ; \
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0: ; \
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incb PCPU(INTR_NESTING_LEVEL) ; \
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; \
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/* entry point used by doreti_unpend for HWIs. */ \
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__CONCAT(Xresume,irq_num): ; \
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FAKE_MCOUNT(13*4(%esp)) ; /* XXX avoid dbl cnt */ \
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pushl $irq_num; /* pass the IRQ */ \
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APIC_ITRACE(apic_itrace_enter2, irq_num, APIC_ITRACE_ENTER2) ; \
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sti ; \
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call _sched_ithd ; \
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addl $4, %esp ; /* discard the parameter */ \
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APIC_ITRACE(apic_itrace_leave, irq_num, APIC_ITRACE_LEAVE) ; \
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; \
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MEXITCOUNT ; \
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jmp _doreti
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/*
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* Handle "spurious INTerrupts".
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* Notes:
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* This is different than the "spurious INTerrupt" generated by an
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* 8259 PIC for missing INTs. See the APIC documentation for details.
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* This routine should NOT do an 'EOI' cycle.
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*/
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.text
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SUPERALIGN_TEXT
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.globl _Xspuriousint
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_Xspuriousint:
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/* No EOI cycle used here */
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iret
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/*
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* Handle TLB shootdowns.
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*/
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.text
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SUPERALIGN_TEXT
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.globl _Xinvltlb
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_Xinvltlb:
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pushl %eax
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#ifdef COUNT_XINVLTLB_HITS
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pushl %fs
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movl $KPSEL, %eax
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mov %ax, %fs
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movl PCPU(CPUID), %eax
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popl %fs
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ss
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incl _xhits(,%eax,4)
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#endif /* COUNT_XINVLTLB_HITS */
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movl %cr3, %eax /* invalidate the TLB */
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movl %eax, %cr3
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ss /* stack segment, avoid %ds load */
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movl $0, _lapic+LA_EOI /* End Of Interrupt to APIC */
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popl %eax
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iret
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#ifdef BETTER_CLOCK
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/*
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* Executed by a CPU when it receives an Xcpucheckstate IPI from another CPU,
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*
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* - Stores current cpu state in checkstate_cpustate[cpuid]
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* 0 == user, 1 == sys, 2 == intr
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* - Stores current process in checkstate_curproc[cpuid]
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*
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* - Signals its receipt by setting bit cpuid in checkstate_probed_cpus.
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*
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* stack: 0->ds, 4->fs, 8->ebx, 12->eax, 16->eip, 20->cs, 24->eflags
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*/
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.text
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SUPERALIGN_TEXT
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.globl _Xcpucheckstate
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.globl _checkstate_cpustate
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.globl _checkstate_curproc
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.globl _checkstate_pc
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_Xcpucheckstate:
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pushl %eax
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pushl %ebx
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pushl %ds /* save current data segment */
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pushl %fs
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movl $KDSEL, %eax
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mov %ax, %ds /* use KERNEL data segment */
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movl $KPSEL, %eax
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mov %ax, %fs
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movl $0, _lapic+LA_EOI /* End Of Interrupt to APIC */
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movl $0, %ebx
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movl 20(%esp), %eax
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andl $3, %eax
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cmpl $3, %eax
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je 1f
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testl $PSL_VM, 24(%esp)
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jne 1f
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incl %ebx /* system or interrupt */
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1:
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movl PCPU(CPUID), %eax
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movl %ebx, _checkstate_cpustate(,%eax,4)
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movl PCPU(CURPROC), %ebx
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movl %ebx, _checkstate_curproc(,%eax,4)
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movl 16(%esp), %ebx
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movl %ebx, _checkstate_pc(,%eax,4)
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lock /* checkstate_probed_cpus |= (1<<id) */
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btsl %eax, _checkstate_probed_cpus
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popl %fs
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popl %ds /* restore previous data segment */
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popl %ebx
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popl %eax
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iret
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#endif /* BETTER_CLOCK */
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/*
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* Executed by a CPU when it receives an Xcpuast IPI from another CPU,
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*
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* - Signals its receipt by clearing bit cpuid in checkstate_need_ast.
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*
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* - We need a better method of triggering asts on other cpus.
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*/
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.text
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SUPERALIGN_TEXT
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.globl _Xcpuast
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_Xcpuast:
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PUSH_FRAME
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movl $KDSEL, %eax
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mov %ax, %ds /* use KERNEL data segment */
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mov %ax, %es
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movl $KPSEL, %eax
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mov %ax, %fs
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movl PCPU(CPUID), %eax
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lock /* checkstate_need_ast &= ~(1<<id) */
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btrl %eax, _checkstate_need_ast
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movl $0, _lapic+LA_EOI /* End Of Interrupt to APIC */
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lock
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btsl %eax, _checkstate_pending_ast
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jc 1f
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FAKE_MCOUNT(13*4(%esp))
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orl $AST_PENDING, PCPU(ASTPENDING) /* XXX */
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incb PCPU(INTR_NESTING_LEVEL)
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sti
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movl PCPU(CPUID), %eax
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lock
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btrl %eax, _checkstate_pending_ast
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lock
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btrl %eax, CNAME(resched_cpus)
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jnc 2f
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orl $AST_PENDING+AST_RESCHED, PCPU(ASTPENDING)
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lock
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incl CNAME(want_resched_cnt)
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2:
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lock
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incl CNAME(cpuast_cnt)
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MEXITCOUNT
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jmp _doreti
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1:
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/* We are already in the process of delivering an ast for this CPU */
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POP_FRAME
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iret
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/*
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* Executed by a CPU when it receives an XFORWARD_IRQ IPI.
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*/
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.text
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SUPERALIGN_TEXT
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.globl _Xforward_irq
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_Xforward_irq:
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PUSH_FRAME
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movl $KDSEL, %eax
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mov %ax, %ds /* use KERNEL data segment */
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mov %ax, %es
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movl $KPSEL, %eax
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mov %ax, %fs
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movl $0, _lapic+LA_EOI /* End Of Interrupt to APIC */
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FAKE_MCOUNT(13*4(%esp))
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lock
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incl CNAME(forward_irq_hitcnt)
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cmpb $4, PCPU(INTR_NESTING_LEVEL)
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jae 1f
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incb PCPU(INTR_NESTING_LEVEL)
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sti
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MEXITCOUNT
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jmp doreti_next /* Handle forwarded interrupt */
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1:
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lock
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incl CNAME(forward_irq_toodeepcnt)
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MEXITCOUNT
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POP_FRAME
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iret
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#if 0
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/*
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*
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*/
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forward_irq:
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MCOUNT
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cmpl $0,_invltlb_ok
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jz 4f
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cmpl $0, CNAME(forward_irq_enabled)
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jz 4f
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/* XXX - this is broken now, because mp_lock doesn't exist
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movl _mp_lock,%eax
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cmpl $FREE_LOCK,%eax
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jne 1f
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*/
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movl $0, %eax /* Pick CPU #0 if noone has lock */
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1:
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shrl $24,%eax
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movl _cpu_num_to_apic_id(,%eax,4),%ecx
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shll $24,%ecx
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movl _lapic+LA_ICR_HI, %eax
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andl $~APIC_ID_MASK, %eax
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orl %ecx, %eax
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movl %eax, _lapic+LA_ICR_HI
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2:
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movl _lapic+LA_ICR_LO, %eax
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andl $APIC_DELSTAT_MASK,%eax
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jnz 2b
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movl _lapic+LA_ICR_LO, %eax
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andl $APIC_RESV2_MASK, %eax
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orl $(APIC_DEST_DESTFLD|APIC_DELMODE_FIXED|XFORWARD_IRQ_OFFSET), %eax
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movl %eax, _lapic+LA_ICR_LO
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3:
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movl _lapic+LA_ICR_LO, %eax
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andl $APIC_DELSTAT_MASK,%eax
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jnz 3b
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4:
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ret
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#endif
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/*
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* Executed by a CPU when it receives an Xcpustop IPI from another CPU,
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*
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* - Signals its receipt.
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* - Waits for permission to restart.
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* - Signals its restart.
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*/
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.text
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SUPERALIGN_TEXT
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.globl _Xcpustop
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_Xcpustop:
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pushl %ebp
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movl %esp, %ebp
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pushl %eax
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pushl %ecx
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pushl %edx
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pushl %ds /* save current data segment */
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pushl %fs
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movl $KDSEL, %eax
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mov %ax, %ds /* use KERNEL data segment */
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movl $KPSEL, %eax
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mov %ax, %fs
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movl $0, _lapic+LA_EOI /* End Of Interrupt to APIC */
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movl PCPU(CPUID), %eax
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imull $PCB_SIZE, %eax
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leal CNAME(stoppcbs)(%eax), %eax
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pushl %eax
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call CNAME(savectx) /* Save process context */
|
|
addl $4, %esp
|
|
|
|
|
|
movl PCPU(CPUID), %eax
|
|
|
|
lock
|
|
btsl %eax, _stopped_cpus /* stopped_cpus |= (1<<id) */
|
|
1:
|
|
btl %eax, _started_cpus /* while (!(started_cpus & (1<<id))) */
|
|
jnc 1b
|
|
|
|
lock
|
|
btrl %eax, _started_cpus /* started_cpus &= ~(1<<id) */
|
|
lock
|
|
btrl %eax, _stopped_cpus /* stopped_cpus &= ~(1<<id) */
|
|
|
|
test %eax, %eax
|
|
jnz 2f
|
|
|
|
movl CNAME(cpustop_restartfunc), %eax
|
|
test %eax, %eax
|
|
jz 2f
|
|
movl $0, CNAME(cpustop_restartfunc) /* One-shot */
|
|
|
|
call *%eax
|
|
2:
|
|
popl %fs
|
|
popl %ds /* restore previous data segment */
|
|
popl %edx
|
|
popl %ecx
|
|
popl %eax
|
|
movl %ebp, %esp
|
|
popl %ebp
|
|
iret
|
|
|
|
|
|
MCOUNT_LABEL(bintr)
|
|
FAST_INTR(0,fastintr0)
|
|
FAST_INTR(1,fastintr1)
|
|
FAST_INTR(2,fastintr2)
|
|
FAST_INTR(3,fastintr3)
|
|
FAST_INTR(4,fastintr4)
|
|
FAST_INTR(5,fastintr5)
|
|
FAST_INTR(6,fastintr6)
|
|
FAST_INTR(7,fastintr7)
|
|
FAST_INTR(8,fastintr8)
|
|
FAST_INTR(9,fastintr9)
|
|
FAST_INTR(10,fastintr10)
|
|
FAST_INTR(11,fastintr11)
|
|
FAST_INTR(12,fastintr12)
|
|
FAST_INTR(13,fastintr13)
|
|
FAST_INTR(14,fastintr14)
|
|
FAST_INTR(15,fastintr15)
|
|
FAST_INTR(16,fastintr16)
|
|
FAST_INTR(17,fastintr17)
|
|
FAST_INTR(18,fastintr18)
|
|
FAST_INTR(19,fastintr19)
|
|
FAST_INTR(20,fastintr20)
|
|
FAST_INTR(21,fastintr21)
|
|
FAST_INTR(22,fastintr22)
|
|
FAST_INTR(23,fastintr23)
|
|
FAST_INTR(24,fastintr24)
|
|
FAST_INTR(25,fastintr25)
|
|
FAST_INTR(26,fastintr26)
|
|
FAST_INTR(27,fastintr27)
|
|
FAST_INTR(28,fastintr28)
|
|
FAST_INTR(29,fastintr29)
|
|
FAST_INTR(30,fastintr30)
|
|
FAST_INTR(31,fastintr31)
|
|
#define CLKINTR_PENDING movl $1,CNAME(clkintr_pending)
|
|
/* Threaded interrupts */
|
|
INTR(0,intr0, CLKINTR_PENDING)
|
|
INTR(1,intr1,)
|
|
INTR(2,intr2,)
|
|
INTR(3,intr3,)
|
|
INTR(4,intr4,)
|
|
INTR(5,intr5,)
|
|
INTR(6,intr6,)
|
|
INTR(7,intr7,)
|
|
INTR(8,intr8,)
|
|
INTR(9,intr9,)
|
|
INTR(10,intr10,)
|
|
INTR(11,intr11,)
|
|
INTR(12,intr12,)
|
|
INTR(13,intr13,)
|
|
INTR(14,intr14,)
|
|
INTR(15,intr15,)
|
|
INTR(16,intr16,)
|
|
INTR(17,intr17,)
|
|
INTR(18,intr18,)
|
|
INTR(19,intr19,)
|
|
INTR(20,intr20,)
|
|
INTR(21,intr21,)
|
|
INTR(22,intr22,)
|
|
INTR(23,intr23,)
|
|
INTR(24,intr24,)
|
|
INTR(25,intr25,)
|
|
INTR(26,intr26,)
|
|
INTR(27,intr27,)
|
|
INTR(28,intr28,)
|
|
INTR(29,intr29,)
|
|
INTR(30,intr30,)
|
|
INTR(31,intr31,)
|
|
MCOUNT_LABEL(eintr)
|
|
|
|
/*
|
|
* Executed by a CPU when it receives a RENDEZVOUS IPI from another CPU.
|
|
*
|
|
* - Calls the generic rendezvous action function.
|
|
*/
|
|
.text
|
|
SUPERALIGN_TEXT
|
|
.globl _Xrendezvous
|
|
_Xrendezvous:
|
|
PUSH_FRAME
|
|
movl $KDSEL, %eax
|
|
mov %ax, %ds /* use KERNEL data segment */
|
|
mov %ax, %es
|
|
movl $KPSEL, %eax
|
|
mov %ax, %fs
|
|
|
|
call _smp_rendezvous_action
|
|
|
|
movl $0, _lapic+LA_EOI /* End Of Interrupt to APIC */
|
|
POP_FRAME
|
|
iret
|
|
|
|
|
|
.data
|
|
#if 0
|
|
/* active flag for lazy masking */
|
|
iactive:
|
|
.long 0
|
|
#endif
|
|
|
|
#ifdef COUNT_XINVLTLB_HITS
|
|
.globl _xhits
|
|
_xhits:
|
|
.space (NCPU * 4), 0
|
|
#endif /* COUNT_XINVLTLB_HITS */
|
|
|
|
/* variables used by stop_cpus()/restart_cpus()/Xcpustop */
|
|
.globl _stopped_cpus, _started_cpus
|
|
_stopped_cpus:
|
|
.long 0
|
|
_started_cpus:
|
|
.long 0
|
|
|
|
#ifdef BETTER_CLOCK
|
|
.globl _checkstate_probed_cpus
|
|
_checkstate_probed_cpus:
|
|
.long 0
|
|
#endif /* BETTER_CLOCK */
|
|
.globl _checkstate_need_ast
|
|
_checkstate_need_ast:
|
|
.long 0
|
|
_checkstate_pending_ast:
|
|
.long 0
|
|
.globl CNAME(forward_irq_misscnt)
|
|
.globl CNAME(forward_irq_toodeepcnt)
|
|
.globl CNAME(forward_irq_hitcnt)
|
|
.globl CNAME(resched_cpus)
|
|
.globl CNAME(want_resched_cnt)
|
|
.globl CNAME(cpuast_cnt)
|
|
.globl CNAME(cpustop_restartfunc)
|
|
CNAME(forward_irq_misscnt):
|
|
.long 0
|
|
CNAME(forward_irq_hitcnt):
|
|
.long 0
|
|
CNAME(forward_irq_toodeepcnt):
|
|
.long 0
|
|
CNAME(resched_cpus):
|
|
.long 0
|
|
CNAME(want_resched_cnt):
|
|
.long 0
|
|
CNAME(cpuast_cnt):
|
|
.long 0
|
|
CNAME(cpustop_restartfunc):
|
|
.long 0
|
|
|
|
.globl _apic_pin_trigger
|
|
_apic_pin_trigger:
|
|
.long 0
|
|
|
|
.text
|