673c4fe419
- Allow for setting per platform MPP/GPIO configuration in the kernel, so that we can override all settings firmware might set. - Set decode windows for the remaining on-chip peripherals: CESA, SATA and XOR. - Improve handling of USB controllers so that all port are available on the given SOC/platform (e.g. up to three on DB-78xxx), this includes rework of USB decode windows set-up. - Other minor fixes and cosmetics. Obtained from: Semihalf
175 lines
5.0 KiB
C
175 lines
5.0 KiB
C
/*-
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* Copyright (C) 2008 MARVELL INTERNATIONAL LTD.
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* All rights reserved.
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*
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* Developed by Semihalf.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of MARVELL nor the names of contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <vm/vm.h>
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#include <vm/pmap.h>
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#include <machine/bus.h>
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#include <machine/pte.h>
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#include <machine/pmap.h>
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#include <machine/vmparam.h>
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#include <arm/mv/mvreg.h>
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#include <arm/mv/mvvar.h>
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/*
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* Virtual address space layout:
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* -----------------------------
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* 0x0000_0000 - 0xbfff_ffff : user process
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*
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* 0xc040_0000 - virtual_avail : kernel reserved (text, data, page tables
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* : structures, ARM stacks etc.)
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* virtual_avail - 0xefff_ffff : KVA (virtual_avail is typically < 0xc0a0_0000)
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* 0xf000_0000 - 0xf0ff_ffff : no-cache allocation area (16MB)
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* 0xf100_0000 - 0xf10f_ffff : SoC integrated devices registers range (1MB)
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* 0xf110_0000 - 0xf11f_ffff : PCI-Express I/O space (1MB)
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* 0xf120_0000 - 0xf12f_ffff : unused (1MB)
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* 0xf130_0000 - 0xf52f_ffff : PCI-Express memory space (64MB)
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* 0xf930_0000 - 0xfffe_ffff : unused (~172MB)
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* 0xffff_0000 - 0xffff_0fff : 'high' vectors page (4KB)
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* 0xffff_1000 - 0xffff_1fff : ARM_TP_ADDRESS/RAS page (4KB)
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* 0xffff_2000 - 0xffff_ffff : unused (~55KB)
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*/
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const struct pmap_devmap *pmap_devmap_bootstrap_table;
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vm_offset_t pmap_bootstrap_lastaddr;
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/* Static device mappings. */
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static const struct pmap_devmap pmap_devmap[] = {
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/*
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* Map the on-board devices VA == PA so that we can access them
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* with the MMU on or off.
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*/
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{ /* SoC integrated peripherals registers range */
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MV_BASE,
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MV_PHYS_BASE,
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MV_SIZE,
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VM_PROT_READ | VM_PROT_WRITE,
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PTE_NOCACHE,
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},
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{ /* PCIE I/O */
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MV_PCIE_IO_BASE,
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MV_PCIE_IO_PHYS_BASE,
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MV_PCIE_IO_SIZE,
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VM_PROT_READ | VM_PROT_WRITE,
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PTE_NOCACHE,
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},
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{ /* PCIE Memory */
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MV_PCIE_MEM_BASE,
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MV_PCIE_MEM_PHYS_BASE,
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MV_PCIE_MEM_SIZE,
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VM_PROT_READ | VM_PROT_WRITE,
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PTE_NOCACHE,
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},
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{ 0, 0, 0, 0, 0, }
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};
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const struct gpio_config mv_gpio_config[] = {
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{ -1, -1, -1 }
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};
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int
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platform_pmap_init(void)
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{
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pmap_bootstrap_lastaddr = MV_BASE - ARM_NOCACHE_KVA_SIZE;
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pmap_devmap_bootstrap_table = &pmap_devmap[0];
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return (0);
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}
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void
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platform_mpp_init(void)
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{
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/*
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* MPP Configuration for DB-78100-BP
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*
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* MPP[0]: GE1_TXCLK
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* MPP[1]: GE1_TXCTL
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* MPP[2]: GE1_RXCTL
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* MPP[3]: GE1_RXCLK
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* MPP[4]: GE1_TXD[0]
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* MPP[5]: GE1_TXD[1]
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* MPP[6]: GE1_TXD[2]
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* MPP[7]: GE1_TXD[3]
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* MPP[8]: GE1_RXD[0]
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* MPP[9]: GE1_RXD[1]
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* MPP[10]: GE1_RXD[2]
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* MPP[11]: GE1_RXD[3]
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* MPP[13]: SYSRST_OUTn
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* MPP[14]: SATA1_ACT
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* MPP[15]: SATA0_ACT
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* MPP[16]: UA2_TXD
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* MPP[17]: UA2_RXD
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* MPP[18]: <UNKNOWN>
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* MPP[19]: <UNKNOWN>
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* MPP[20]: <UNKNOWN>
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* MPP[21]: <UNKNOWN>
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* MPP[22]: UA3_TXD
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* MPP[23]: UA3_RXD
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* MPP[48]: <UNKNOWN>
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* MPP[49]: <UNKNOWN>
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*
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* Others: GPIO
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*
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* <UNKNOWN> entries are not documented, not on the schematics etc.
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*/
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bus_space_write_4(obio_tag, MV_MPP_BASE, MPP_CONTROL0, 0x22222222);
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bus_space_write_4(obio_tag, MV_MPP_BASE, MPP_CONTROL1, 0x33302222);
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bus_space_write_4(obio_tag, MV_MPP_BASE, MPP_CONTROL2, 0x44333344);
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bus_space_write_4(obio_tag, MV_MPP_BASE, MPP_CONTROL3, 0x00000000);
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bus_space_write_4(obio_tag, MV_MPP_BASE, MPP_CONTROL4, 0x00000000);
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bus_space_write_4(obio_tag, MV_MPP_BASE, MPP_CONTROL5, 0x00000000);
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bus_space_write_4(obio_tag, MV_MPP_BASE, MPP_CONTROL6, 0x0000FFFF);
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}
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static void
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platform_identify(void *dummy)
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{
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soc_identify();
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/*
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* XXX Board identification e.g. read out from FPGA or similar should
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* go here
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*/
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}
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SYSINIT(platform_identify, SI_SUB_CPU, SI_ORDER_SECOND, platform_identify, NULL);
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