156 lines
4.3 KiB
ArmAsm
156 lines
4.3 KiB
ArmAsm
/*-
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* Copyright (c) 2009 Neelkanth Natu
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <machine/asm.h>
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/*
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* We compile a 32-bit kernel to run on the SB-1 processor which is a 64-bit
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* processor. It has some registers that must be accessed using 64-bit load
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* and store instructions.
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*
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* So we have to resort to assembly because the compiler does not emit the
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* 'ld' and 'sd' instructions since it thinks that it is compiling for a
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* 32-bit mips processor.
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*/
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.set mips64
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.set noat
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.set noreorder
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/*
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* return (MIPS_PHYS_TO_KSEG1(0x10020008))
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* Parameters: none
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*/
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LEAF(sb_read_syscfg)
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lui v0, 0xb002
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ori v0, v0, 0x8
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ld v1, 0(v0) /* syscfg = MIPS_PHYS_TO_KSEG1(0x10020008) */
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move v0, v1
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dsll32 v0, v0, 0
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dsrl32 v0, v0, 0 /* v0 = lower_uint32(mask) */
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jr ra
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dsrl32 v1, v1, 0 /* v1 = upper_uint32(mask) */
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END(sb_read_syscfg)
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/*
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* MIPS_PHYS_TO_KSEG1(0x10020008) = (uint64_t)val
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* Parameters:
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* - lower_uint32(val): a0
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* - upper_uint32(val): a1
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*/
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LEAF(sb_write_syscfg)
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lui v0, 0xb002
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ori v0, v0, 0x8
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dsll32 a1, a1, 0 /* clear lower 32 bits of a1 */
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dsll32 a0, a0, 0
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dsrl32 a0, a0, 0 /* clear upper 32 bits of a0 */
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or a1, a1, a0
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sd a1, 0(v0) /* MIPS_PHYS_TO_KSEG1(0x10020008) = val */
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jr ra
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nop
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nop
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END(sb_write_syscfg)
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/*
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* MIPS_PHYS_TO_KSEG1(0x10020028) |= (1 << intsrc)
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*
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* Parameters:
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* - intsrc (a0)
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*/
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LEAF(sb_disable_intsrc)
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lui v0, 0xb002
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ori v0, v0, 0x28
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ld v1, 0(v0) /* mask = MIPS_PHYS_TO_KSEG1(0x10020028) */
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li a1, 1
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dsllv a1, a1, a0
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or a1, a1, v1 /* mask |= (1 << intsrc) */
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jr ra
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sd a1, 0(v0) /* MIPS_PHYS_TO_KSEG1(0x10020028) = mask */
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END(sb_disable_intsrc)
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/*
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* MIPS_PHYS_TO_KSEG1(0x10020028) &= ~(1 << intsrc)
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*
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* Parameters:
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* - intsrc (a0)
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*/
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LEAF(sb_enable_intsrc)
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lui v0, 0xb002
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ori v0, v0, 0x28
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ld v1, 0(v0) /* mask = MIPS_PHYS_TO_KSEG1(0x10020028) */
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li a2, 1
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dsllv a2, a2, a0
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nor a2, zero, a2
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and a2, a2, v1 /* mask &= ~(1 << intsrc) */
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sd a2, 0(v0) /* MIPS_PHYS_TO_KSEG1(0x10020028) = mask */
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jr ra
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nop
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END(sb_enable_intsrc)
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/*
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* return ((uint64_t)MIPS_PHYS_TO_KSEG1(0x10020028))
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* Parameters: none
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*/
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LEAF(sb_read_intsrc_mask)
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lui v0, 0xb002
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ori v0, v0, 0x28
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ld v1, 0(v0) /* mask = MIPS_PHYS_TO_KSEG1(0x10020028) */
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move v0, v1
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dsll32 v0, v0, 0
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dsrl32 v0, v0, 0 /* v0 = lower_uint32(mask) */
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jr ra
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dsrl32 v1, v1, 0 /* v1 = upper_uint32(mask) */
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END(sb_read_intsrc_mask)
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/*
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* return ((uint64_t *)MIPS_PHYS_TO_KSEG1(0x10020200) + intsrc)
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* Parameters:
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* - intsrc (a0)
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*/
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LEAF(sb_read_intmap)
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sll a0, a0, 3 /* compute the offset of the intmap register */
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lui v0, 0xb002
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addu a0, a0, v0
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ld v0, 512(a0) /* v0 = MIPS_PHYS_TO_KSEG1(0x10020200) + off */
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jr ra
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nop
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END(sb_read_intmap)
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/*
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* (uint64_t *)MIPS_PHYS_TO_KSEG1(0x10020200) + intsrc = irq
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* Parameters:
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* - intsrc (a0)
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* - irq (a1)
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*/
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LEAF(sb_write_intmap)
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sll a0, a0, 0x3 /* compute the offset of the intmap register */
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lui v0, 0xb002
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addu a0, a0, v0
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sd a1, 512(a0) /* MIPS_PHYS_TO_KSEG1(0x10020200) + off = irq */
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jr ra
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nop
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END(sb_write_intmap)
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