455fa6518a
This update brings few features:
o Support for the setmaster/dropmaster ioctls. For instance, they
are used to run multiple X servers simultaneously.
o Support for minor devices. The only user-visible change is a new
entry in /dev/dri but it is useless at the moment. This is a
first step to support render nodes [1].
The main benefit is to greatly reduce the diff with Linux (at the
expense of an unreadable commit diff). Hopefully, next upgrades will be
easier.
No updates were made to the drivers, beside adapting them to API
changes.
[1] https://en.wikipedia.org/wiki/Direct_Rendering_Manager#Render_nodes
Tested by: Many people
MFC after: 1 month
Relnotes: yes
258 lines
7.5 KiB
C
258 lines
7.5 KiB
C
/*
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* Copyright © 2007-2008 Intel Corporation
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* Jesse Barnes <jesse.barnes@intel.com>
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* $FreeBSD$
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*/
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#ifndef __DRM_EDID_H__
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#define __DRM_EDID_H__
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#define EDID_LENGTH 128
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#define DDC_ADDR 0x50
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#define CEA_EXT 0x02
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#define VTB_EXT 0x10
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#define DI_EXT 0x40
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#define LS_EXT 0x50
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#define MI_EXT 0x60
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struct est_timings {
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u8 t1;
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u8 t2;
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u8 mfg_rsvd;
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} __attribute__((packed));
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/* 00=16:10, 01=4:3, 10=5:4, 11=16:9 */
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#define EDID_TIMING_ASPECT_SHIFT 6
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#define EDID_TIMING_ASPECT_MASK (0x3 << EDID_TIMING_ASPECT_SHIFT)
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/* need to add 60 */
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#define EDID_TIMING_VFREQ_SHIFT 0
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#define EDID_TIMING_VFREQ_MASK (0x3f << EDID_TIMING_VFREQ_SHIFT)
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struct std_timing {
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u8 hsize; /* need to multiply by 8 then add 248 */
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u8 vfreq_aspect;
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} __attribute__((packed));
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#define DRM_EDID_PT_HSYNC_POSITIVE (1 << 1)
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#define DRM_EDID_PT_VSYNC_POSITIVE (1 << 2)
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#define DRM_EDID_PT_SEPARATE_SYNC (3 << 3)
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#define DRM_EDID_PT_STEREO (1 << 5)
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#define DRM_EDID_PT_INTERLACED (1 << 7)
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/* If detailed data is pixel timing */
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struct detailed_pixel_timing {
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u8 hactive_lo;
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u8 hblank_lo;
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u8 hactive_hblank_hi;
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u8 vactive_lo;
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u8 vblank_lo;
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u8 vactive_vblank_hi;
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u8 hsync_offset_lo;
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u8 hsync_pulse_width_lo;
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u8 vsync_offset_pulse_width_lo;
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u8 hsync_vsync_offset_pulse_width_hi;
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u8 width_mm_lo;
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u8 height_mm_lo;
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u8 width_height_mm_hi;
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u8 hborder;
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u8 vborder;
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u8 misc;
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} __attribute__((packed));
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/* If it's not pixel timing, it'll be one of the below */
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struct detailed_data_string {
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u8 str[13];
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} __attribute__((packed));
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struct detailed_data_monitor_range {
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u8 min_vfreq;
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u8 max_vfreq;
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u8 min_hfreq_khz;
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u8 max_hfreq_khz;
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u8 pixel_clock_mhz; /* need to multiply by 10 */
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u8 flags;
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union {
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struct {
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u8 reserved;
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u8 hfreq_start_khz; /* need to multiply by 2 */
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u8 c; /* need to divide by 2 */
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__le16 m;
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u8 k;
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u8 j; /* need to divide by 2 */
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} __attribute__((packed)) gtf2;
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struct {
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u8 version;
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u8 data1; /* high 6 bits: extra clock resolution */
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u8 data2; /* plus low 2 of above: max hactive */
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u8 supported_aspects;
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u8 flags; /* preferred aspect and blanking support */
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u8 supported_scalings;
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u8 preferred_refresh;
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} __attribute__((packed)) cvt;
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} formula;
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} __attribute__((packed));
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struct detailed_data_wpindex {
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u8 white_yx_lo; /* Lower 2 bits each */
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u8 white_x_hi;
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u8 white_y_hi;
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u8 gamma; /* need to divide by 100 then add 1 */
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} __attribute__((packed));
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struct detailed_data_color_point {
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u8 windex1;
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u8 wpindex1[3];
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u8 windex2;
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u8 wpindex2[3];
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} __attribute__((packed));
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struct cvt_timing {
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u8 code[3];
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} __attribute__((packed));
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struct detailed_non_pixel {
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u8 pad1;
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u8 type; /* ff=serial, fe=string, fd=monitor range, fc=monitor name
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fb=color point data, fa=standard timing data,
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f9=undefined, f8=mfg. reserved */
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u8 pad2;
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union {
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struct detailed_data_string str;
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struct detailed_data_monitor_range range;
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struct detailed_data_wpindex color;
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struct std_timing timings[6];
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struct cvt_timing cvt[4];
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} data;
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} __attribute__((packed));
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#define EDID_DETAIL_EST_TIMINGS 0xf7
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#define EDID_DETAIL_CVT_3BYTE 0xf8
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#define EDID_DETAIL_COLOR_MGMT_DATA 0xf9
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#define EDID_DETAIL_STD_MODES 0xfa
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#define EDID_DETAIL_MONITOR_CPDATA 0xfb
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#define EDID_DETAIL_MONITOR_NAME 0xfc
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#define EDID_DETAIL_MONITOR_RANGE 0xfd
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#define EDID_DETAIL_MONITOR_STRING 0xfe
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#define EDID_DETAIL_MONITOR_SERIAL 0xff
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struct detailed_timing {
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__le16 pixel_clock; /* need to multiply by 10 KHz */
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union {
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struct detailed_pixel_timing pixel_data;
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struct detailed_non_pixel other_data;
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} data;
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} __attribute__((packed));
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#define DRM_EDID_INPUT_SERRATION_VSYNC (1 << 0)
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#define DRM_EDID_INPUT_SYNC_ON_GREEN (1 << 1)
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#define DRM_EDID_INPUT_COMPOSITE_SYNC (1 << 2)
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#define DRM_EDID_INPUT_SEPARATE_SYNCS (1 << 3)
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#define DRM_EDID_INPUT_BLANK_TO_BLACK (1 << 4)
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#define DRM_EDID_INPUT_VIDEO_LEVEL (3 << 5)
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#define DRM_EDID_INPUT_DIGITAL (1 << 7)
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#define DRM_EDID_DIGITAL_DEPTH_MASK (7 << 4)
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#define DRM_EDID_DIGITAL_DEPTH_UNDEF (0 << 4)
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#define DRM_EDID_DIGITAL_DEPTH_6 (1 << 4)
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#define DRM_EDID_DIGITAL_DEPTH_8 (2 << 4)
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#define DRM_EDID_DIGITAL_DEPTH_10 (3 << 4)
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#define DRM_EDID_DIGITAL_DEPTH_12 (4 << 4)
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#define DRM_EDID_DIGITAL_DEPTH_14 (5 << 4)
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#define DRM_EDID_DIGITAL_DEPTH_16 (6 << 4)
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#define DRM_EDID_DIGITAL_DEPTH_RSVD (7 << 4)
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#define DRM_EDID_DIGITAL_TYPE_UNDEF (0)
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#define DRM_EDID_DIGITAL_TYPE_DVI (1)
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#define DRM_EDID_DIGITAL_TYPE_HDMI_A (2)
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#define DRM_EDID_DIGITAL_TYPE_HDMI_B (3)
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#define DRM_EDID_DIGITAL_TYPE_MDDI (4)
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#define DRM_EDID_DIGITAL_TYPE_DP (5)
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#define DRM_EDID_FEATURE_DEFAULT_GTF (1 << 0)
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#define DRM_EDID_FEATURE_PREFERRED_TIMING (1 << 1)
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#define DRM_EDID_FEATURE_STANDARD_COLOR (1 << 2)
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/* If analog */
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#define DRM_EDID_FEATURE_DISPLAY_TYPE (3 << 3) /* 00=mono, 01=rgb, 10=non-rgb, 11=unknown */
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/* If digital */
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#define DRM_EDID_FEATURE_COLOR_MASK (3 << 3)
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#define DRM_EDID_FEATURE_RGB (0 << 3)
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#define DRM_EDID_FEATURE_RGB_YCRCB444 (1 << 3)
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#define DRM_EDID_FEATURE_RGB_YCRCB422 (2 << 3)
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#define DRM_EDID_FEATURE_RGB_YCRCB (3 << 3) /* both 4:4:4 and 4:2:2 */
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#define DRM_EDID_FEATURE_PM_ACTIVE_OFF (1 << 5)
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#define DRM_EDID_FEATURE_PM_SUSPEND (1 << 6)
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#define DRM_EDID_FEATURE_PM_STANDBY (1 << 7)
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struct edid {
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u8 header[8];
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/* Vendor & product info */
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u8 mfg_id[2];
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u8 prod_code[2];
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u32 serial; /* FIXME: byte order */
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u8 mfg_week;
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u8 mfg_year;
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/* EDID version */
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u8 version;
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u8 revision;
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/* Display info: */
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u8 input;
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u8 width_cm;
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u8 height_cm;
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u8 gamma;
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u8 features;
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/* Color characteristics */
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u8 red_green_lo;
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u8 black_white_lo;
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u8 red_x;
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u8 red_y;
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u8 green_x;
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u8 green_y;
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u8 blue_x;
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u8 blue_y;
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u8 white_x;
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u8 white_y;
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/* Est. timings and mfg rsvd timings*/
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struct est_timings established_timings;
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/* Standard timings 1-8*/
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struct std_timing standard_timings[8];
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/* Detailing timings 1-4 */
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struct detailed_timing detailed_timings[4];
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/* Number of 128 byte ext. blocks */
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u8 extensions;
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/* Checksum */
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u8 checksum;
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} __attribute__((packed));
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#define EDID_PRODUCT_ID(e) ((e)->prod_code[0] | ((e)->prod_code[1] << 8))
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struct drm_encoder;
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struct drm_connector;
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struct drm_display_mode;
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void drm_edid_to_eld(struct drm_connector *connector, struct edid *edid);
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int drm_av_sync_delay(struct drm_connector *connector,
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struct drm_display_mode *mode);
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struct drm_connector *drm_select_eld(struct drm_encoder *encoder,
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struct drm_display_mode *mode);
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int drm_load_edid_firmware(struct drm_connector *connector);
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#endif /* __DRM_EDID_H__ */
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