7ec8c789c3
The Allwinner SoC has an AHCI device on its internal main bus rather than the PCI bus. This SoC is somewhat underdocumented, and its SATA controller is no exception. The methods to support this chip were harvested from the Linux Allwinner SDK, and then constants invented to describe what's going on based on low-level constants contained in the SATA standard and guess work. This SoC requires a specific AHCI channel setup in order to start the operations on the channel properly. Clock setup and AHCI channel setup idea came from NetBSD. Tested on Cubieboard 2 and Banana pi (and attachment on Cubieboard by Pratik Singhal). Differential Revision: https://reviews.freebsd.org/D737 Submitted by: imp Reviewed by: imp, ganbold, mav, andrew
327 lines
8.2 KiB
C
327 lines
8.2 KiB
C
/*-
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* Copyright (c) 2013 Ganbold Tsagaankhuu <ganbold@freebsd.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/* Simple clock driver for Allwinner A10 */
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/malloc.h>
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#include <sys/rman.h>
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#include <sys/timeet.h>
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#include <sys/timetc.h>
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#include <sys/watchdog.h>
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#include <machine/bus.h>
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#include <machine/cpu.h>
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#include <machine/intr.h>
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#include <dev/fdt/fdt_common.h>
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#include <dev/ofw/openfirm.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include <machine/bus.h>
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#include "a10_clk.h"
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struct a10_ccm_softc {
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struct resource *res;
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bus_space_tag_t bst;
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bus_space_handle_t bsh;
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int pll6_enabled;
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};
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static struct a10_ccm_softc *a10_ccm_sc = NULL;
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#define ccm_read_4(sc, reg) \
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bus_space_read_4((sc)->bst, (sc)->bsh, (reg))
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#define ccm_write_4(sc, reg, val) \
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bus_space_write_4((sc)->bst, (sc)->bsh, (reg), (val))
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static int
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a10_ccm_probe(device_t dev)
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{
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if (!ofw_bus_status_okay(dev))
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return (ENXIO);
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if (ofw_bus_is_compatible(dev, "allwinner,sun4i-ccm")) {
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device_set_desc(dev, "Allwinner Clock Control Module");
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return(BUS_PROBE_DEFAULT);
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}
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return (ENXIO);
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}
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static int
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a10_ccm_attach(device_t dev)
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{
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struct a10_ccm_softc *sc = device_get_softc(dev);
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int rid = 0;
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if (a10_ccm_sc)
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return (ENXIO);
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sc->res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE);
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if (!sc->res) {
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device_printf(dev, "could not allocate resource\n");
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return (ENXIO);
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}
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sc->bst = rman_get_bustag(sc->res);
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sc->bsh = rman_get_bushandle(sc->res);
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a10_ccm_sc = sc;
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return (0);
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}
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static device_method_t a10_ccm_methods[] = {
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DEVMETHOD(device_probe, a10_ccm_probe),
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DEVMETHOD(device_attach, a10_ccm_attach),
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{ 0, 0 }
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};
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static driver_t a10_ccm_driver = {
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"a10_ccm",
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a10_ccm_methods,
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sizeof(struct a10_ccm_softc),
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};
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static devclass_t a10_ccm_devclass;
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DRIVER_MODULE(a10_ccm, simplebus, a10_ccm_driver, a10_ccm_devclass, 0, 0);
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int
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a10_clk_usb_activate(void)
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{
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struct a10_ccm_softc *sc = a10_ccm_sc;
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uint32_t reg_value;
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if (sc == NULL)
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return (ENXIO);
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/* Gating AHB clock for USB */
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reg_value = ccm_read_4(sc, CCM_AHB_GATING0);
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reg_value |= CCM_AHB_GATING_USB0; /* AHB clock gate usb0 */
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reg_value |= CCM_AHB_GATING_EHCI0; /* AHB clock gate ehci0 */
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reg_value |= CCM_AHB_GATING_EHCI1; /* AHB clock gate ehci1 */
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ccm_write_4(sc, CCM_AHB_GATING0, reg_value);
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/* Enable clock for USB */
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reg_value = ccm_read_4(sc, CCM_USB_CLK);
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reg_value |= CCM_USB_PHY; /* USBPHY */
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reg_value |= CCM_USB0_RESET; /* disable reset for USB0 */
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reg_value |= CCM_USB1_RESET; /* disable reset for USB1 */
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reg_value |= CCM_USB2_RESET; /* disable reset for USB2 */
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ccm_write_4(sc, CCM_USB_CLK, reg_value);
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return (0);
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}
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int
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a10_clk_usb_deactivate(void)
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{
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struct a10_ccm_softc *sc = a10_ccm_sc;
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uint32_t reg_value;
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if (sc == NULL)
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return (ENXIO);
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/* Disable clock for USB */
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reg_value = ccm_read_4(sc, CCM_USB_CLK);
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reg_value &= ~CCM_USB_PHY; /* USBPHY */
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reg_value &= ~CCM_USB0_RESET; /* reset for USB0 */
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reg_value &= ~CCM_USB1_RESET; /* reset for USB1 */
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reg_value &= ~CCM_USB2_RESET; /* reset for USB2 */
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ccm_write_4(sc, CCM_USB_CLK, reg_value);
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/* Disable gating AHB clock for USB */
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reg_value = ccm_read_4(sc, CCM_AHB_GATING0);
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reg_value &= ~CCM_AHB_GATING_USB0; /* disable AHB clock gate usb0 */
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reg_value &= ~CCM_AHB_GATING_EHCI0; /* disable AHB clock gate ehci0 */
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reg_value &= ~CCM_AHB_GATING_EHCI1; /* disable AHB clock gate ehci1 */
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ccm_write_4(sc, CCM_AHB_GATING0, reg_value);
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return (0);
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}
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int
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a10_clk_emac_activate(void)
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{
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struct a10_ccm_softc *sc = a10_ccm_sc;
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uint32_t reg_value;
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if (sc == NULL)
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return (ENXIO);
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/* Gating AHB clock for EMAC */
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reg_value = ccm_read_4(sc, CCM_AHB_GATING0);
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reg_value |= CCM_AHB_GATING_EMAC;
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ccm_write_4(sc, CCM_AHB_GATING0, reg_value);
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return (0);
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}
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static void
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a10_clk_pll6_enable(void)
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{
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struct a10_ccm_softc *sc;
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uint32_t reg_value;
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/*
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* SATA needs PLL6 to be a 100MHz clock.
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* The SATA output frequency is 24MHz * n * k / m / 6.
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* To get to 100MHz, k & m must be equal and n must be 25.
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* For other uses the output frequency is 24MHz * n * k / 2.
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*/
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sc = a10_ccm_sc;
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if (sc->pll6_enabled)
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return;
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reg_value = ccm_read_4(sc, CCM_PLL6_CFG);
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reg_value &= ~CCM_PLL_CFG_BYPASS;
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reg_value &= ~(CCM_PLL_CFG_FACTOR_K | CCM_PLL_CFG_FACTOR_M |
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CCM_PLL_CFG_FACTOR_N);
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reg_value |= (25 << CCM_PLL_CFG_FACTOR_N_SHIFT);
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reg_value |= CCM_PLL6_CFG_SATA_CLKEN;
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reg_value |= CCM_PLL_CFG_ENABLE;
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ccm_write_4(sc, CCM_PLL6_CFG, reg_value);
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sc->pll6_enabled = 1;
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}
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static unsigned int
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a10_clk_pll6_get_rate(void)
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{
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struct a10_ccm_softc *sc;
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uint32_t k, n, reg_value;
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sc = a10_ccm_sc;
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reg_value = ccm_read_4(sc, CCM_PLL6_CFG);
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n = ((reg_value & CCM_PLL_CFG_FACTOR_N) >> CCM_PLL_CFG_FACTOR_N_SHIFT);
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k = ((reg_value & CCM_PLL_CFG_FACTOR_K) >> CCM_PLL_CFG_FACTOR_K_SHIFT) +
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1;
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return ((CCM_CLK_REF_FREQ * n * k) / 2);
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}
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int
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a10_clk_ahci_activate(void)
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{
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struct a10_ccm_softc *sc;
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uint32_t reg_value;
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sc = a10_ccm_sc;
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if (sc == NULL)
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return (ENXIO);
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a10_clk_pll6_enable();
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/* Gating AHB clock for SATA */
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reg_value = ccm_read_4(sc, CCM_AHB_GATING0);
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reg_value |= CCM_AHB_GATING_SATA;
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ccm_write_4(sc, CCM_AHB_GATING0, reg_value);
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DELAY(1000);
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ccm_write_4(sc, CCM_SATA_CLK, CCM_PLL_CFG_ENABLE);
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return (0);
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}
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int
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a10_clk_mmc_activate(int devid)
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{
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struct a10_ccm_softc *sc;
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uint32_t reg_value;
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sc = a10_ccm_sc;
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if (sc == NULL)
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return (ENXIO);
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a10_clk_pll6_enable();
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/* Gating AHB clock for SD/MMC */
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reg_value = ccm_read_4(sc, CCM_AHB_GATING0);
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reg_value |= CCM_AHB_GATING_SDMMC0 << devid;
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ccm_write_4(sc, CCM_AHB_GATING0, reg_value);
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return (0);
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}
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int
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a10_clk_mmc_cfg(int devid, int freq)
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{
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struct a10_ccm_softc *sc;
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uint32_t clksrc, m, n, ophase, phase, reg_value;
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unsigned int pll_freq;
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sc = a10_ccm_sc;
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if (sc == NULL)
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return (ENXIO);
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freq /= 1000;
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if (freq <= 400) {
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pll_freq = CCM_CLK_REF_FREQ / 1000;
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clksrc = CCM_SD_CLK_SRC_SEL_OSC24M;
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ophase = 0;
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phase = 0;
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n = 2;
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} else if (freq <= 25000) {
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pll_freq = a10_clk_pll6_get_rate() / 1000;
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clksrc = CCM_SD_CLK_SRC_SEL_PLL6;
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ophase = 0;
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phase = 5;
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n = 2;
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} else if (freq <= 50000) {
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pll_freq = a10_clk_pll6_get_rate() / 1000;
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clksrc = CCM_SD_CLK_SRC_SEL_PLL6;
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ophase = 3;
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phase = 5;
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n = 0;
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} else
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return (EINVAL);
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m = ((pll_freq / (1 << n)) / (freq)) - 1;
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reg_value = ccm_read_4(sc, CCM_MMC0_SCLK_CFG + (devid * 4));
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reg_value &= ~CCM_SD_CLK_SRC_SEL;
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reg_value |= (clksrc << CCM_SD_CLK_SRC_SEL_SHIFT);
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reg_value &= ~CCM_SD_CLK_PHASE_CTR;
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reg_value |= (phase << CCM_SD_CLK_PHASE_CTR_SHIFT);
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reg_value &= ~CCM_SD_CLK_DIV_RATIO_N;
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reg_value |= (n << CCM_SD_CLK_DIV_RATIO_N_SHIFT);
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reg_value &= ~CCM_SD_CLK_OPHASE_CTR;
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reg_value |= (ophase << CCM_SD_CLK_OPHASE_CTR_SHIFT);
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reg_value &= ~CCM_SD_CLK_DIV_RATIO_M;
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reg_value |= m;
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reg_value |= CCM_PLL_CFG_ENABLE;
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ccm_write_4(sc, CCM_MMC0_SCLK_CFG + (devid * 4), reg_value);
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return (0);
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}
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