654d58ca24
older PCI BIOSes hate this and this leads to panics when it is done. Also, assume that a uniquely routed interrupt is already routed. This also seems to help some older laptops with feable BIOSes cope.
745 lines
18 KiB
C
745 lines
18 KiB
C
/*
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* Copyright (c) 1997, Stefan Esser <se@freebsd.org>
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* Copyright (c) 2000, Michael Smith <msmith@freebsd.org>
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* Copyright (c) 2000, BSDi
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice unmodified, this list of conditions, and the following
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* disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $FreeBSD$
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*
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*/
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#include <sys/param.h> /* XXX trim includes */
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/malloc.h>
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#include <vm/vm.h>
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#include <vm/pmap.h>
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#include <machine/md_var.h>
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#include <pci/pcivar.h>
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#include <pci/pcireg.h>
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#include <isa/isavar.h>
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#include <machine/nexusvar.h>
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#include <machine/pci_cfgreg.h>
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#include <machine/segments.h>
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#include <machine/pc/bios.h>
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#ifdef APIC_IO
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#include <machine/smp.h>
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#endif /* APIC_IO */
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#include "pcib_if.h"
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#define PRVERB(a) printf a
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static int cfgmech;
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static int devmax;
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static int usebios;
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static int enable_pcibios = 0;
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TUNABLE_INT("hw.pci.enable_pcibios", &enable_pcibios);
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static int pci_cfgintr_unique(struct PIR_entry *pe, int pin);
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static int pci_cfgintr_linked(struct PIR_entry *pe, int pin);
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static int pci_cfgintr_search(struct PIR_entry *pe, int bus, int device, int matchpin, int pin);
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static int pci_cfgintr_virgin(struct PIR_entry *pe, int pin);
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static int pcibios_cfgread(int bus, int slot, int func, int reg, int bytes);
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static void pcibios_cfgwrite(int bus, int slot, int func, int reg, int data, int bytes);
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static int pcibios_cfgopen(void);
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static int pcireg_cfgread(int bus, int slot, int func, int reg, int bytes);
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static void pcireg_cfgwrite(int bus, int slot, int func, int reg, int data, int bytes);
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static int pcireg_cfgopen(void);
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static struct PIR_table *pci_route_table;
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static int pci_route_count;
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int
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pci_pcibios_active(void)
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{
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return usebios;
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}
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int
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pci_kill_pcibios(void)
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{
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usebios = 0;
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return pcireg_cfgopen() != 0;
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}
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static u_int16_t
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pcibios_get_version(void)
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{
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struct bios_regs args;
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if (PCIbios.entry == 0) {
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PRVERB(("pcibios: No call entry point\n"));
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return (0);
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}
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args.eax = PCIBIOS_BIOS_PRESENT;
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if (bios32(&args, PCIbios.ventry, GSEL(GCODE_SEL, SEL_KPL))) {
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PRVERB(("pcibios: BIOS_PRESENT call failed\n"));
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return (0);
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}
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if (args.edx != 0x20494350) {
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PRVERB(("pcibios: BIOS_PRESENT didn't return 'PCI ' in edx\n"));
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return (0);
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}
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return (args.ebx & 0xffff);
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}
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/*
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* Initialise access to PCI configuration space
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*/
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int
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pci_cfgregopen(void)
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{
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static int opened = 0;
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u_long sigaddr;
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static struct PIR_table *pt;
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u_int8_t ck, *cv;
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int i;
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if (opened)
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return(1);
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if (pcibios_cfgopen() != 0) {
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usebios = 1;
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} else if (pcireg_cfgopen() != 0) {
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usebios = 0;
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} else {
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return(0);
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}
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/*
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* Look for the interrupt routing table.
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*
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* We use PCI BIOS's PIR table if it's available $PIR is the
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* standard way to do this. Sadly, some machines are not
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* standards conforming and have _PIR instead. We shrug and cope
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* by looking for both.
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*/
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if (pcibios_get_version() >= 0x0210 && pt == NULL) {
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sigaddr = bios_sigsearch(0, "$PIR", 4, 16, 0);
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if (sigaddr == 0)
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sigaddr = bios_sigsearch(0, "_PIR", 4, 16, 0);
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if (sigaddr != 0) {
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pt = (struct PIR_table *)(uintptr_t)BIOS_PADDRTOVADDR(sigaddr);
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for (cv = (u_int8_t *)pt, ck = 0, i = 0;
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i < (pt->pt_header.ph_length); i++) {
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ck += cv[i];
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}
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if (ck == 0) {
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pci_route_table = pt;
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pci_route_count = (pt->pt_header.ph_length -
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sizeof(struct PIR_header)) / sizeof(struct PIR_entry);
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printf("Using $PIR table, %d entries at %p\n",
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pci_route_count, pci_route_table);
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}
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}
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}
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opened = 1;
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return(1);
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}
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/*
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* Read configuration space register
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*/
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static u_int32_t
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pci_do_cfgregread(int bus, int slot, int func, int reg, int bytes)
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{
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return(usebios ?
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pcibios_cfgread(bus, slot, func, reg, bytes) :
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pcireg_cfgread(bus, slot, func, reg, bytes));
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}
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u_int32_t
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pci_cfgregread(int bus, int slot, int func, int reg, int bytes)
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{
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#ifdef APIC_IO
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/*
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* If we are using the APIC, the contents of the intline register will probably
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* be wrong (since they are set up for use with the PIC.
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* Rather than rewrite these registers (maybe that would be smarter) we trap
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* attempts to read them and translate to our private vector numbers.
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*/
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if ((reg == PCIR_INTLINE) && (bytes == 1)) {
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int pin, line;
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pin = pci_do_cfgregread(bus, slot, func, PCIR_INTPIN, 1);
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line = pci_do_cfgregread(bus, slot, func, PCIR_INTLINE, 1);
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if (pin != 0) {
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int airq;
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airq = pci_apic_irq(bus, slot, pin);
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if (airq >= 0) {
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/* PCI specific entry found in MP table */
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if (airq != line)
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undirect_pci_irq(line);
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return(airq);
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} else {
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/*
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* PCI interrupts might be redirected to the
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* ISA bus according to some MP tables. Use the
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* same methods as used by the ISA devices
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* devices to find the proper IOAPIC int pin.
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*/
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airq = isa_apic_irq(line);
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if ((airq >= 0) && (airq != line)) {
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/* XXX: undirect_pci_irq() ? */
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undirect_isa_irq(line);
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return(airq);
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}
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}
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}
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return(line);
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}
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#endif /* APIC_IO */
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return(pci_do_cfgregread(bus, slot, func, reg, bytes));
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}
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/*
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* Write configuration space register
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*/
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void
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pci_cfgregwrite(int bus, int slot, int func, int reg, u_int32_t data, int bytes)
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{
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return(usebios ?
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pcibios_cfgwrite(bus, slot, func, reg, data, bytes) :
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pcireg_cfgwrite(bus, slot, func, reg, data, bytes));
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}
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/*
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* Route a PCI interrupt
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*
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* XXX we don't do anything "right" with the function number in the PIR table
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* (because the consumer isn't currently passing it in). We don't care
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* anyway, due to the way PCI interrupts are assigned.
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*/
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int
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pci_cfgintr(int bus, int device, int pin)
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{
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struct PIR_entry *pe;
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int i, irq;
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struct bios_regs args;
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u_int16_t v;
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int already = 0;
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v = pcibios_get_version();
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if (v < 0x0210) {
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PRVERB((
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"pci_cfgintr: BIOS %x.%02x doesn't support interrupt routing\n",
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(v & 0xff00) >> 8, v & 0xff));
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return (255);
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}
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if ((bus < 0) || (bus > 255) || (device < 0) || (device > 255) ||
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(pin < 1) || (pin > 4))
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return(255);
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/*
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* Scan the entry table for a contender
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*/
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for (i = 0, pe = &pci_route_table->pt_entry[0]; i < pci_route_count; i++, pe++) {
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if ((bus != pe->pe_bus) || (device != pe->pe_device))
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continue;
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irq = pci_cfgintr_linked(pe, pin);
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if (irq == 255)
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irq = pci_cfgintr_unique(pe, pin);
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if (irq != 255)
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already = 1;
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if (irq == 255)
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irq = pci_cfgintr_virgin(pe, pin);
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if (irq == 255)
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break;
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/*
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* Ask the BIOS to route the interrupt
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*/
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args.eax = PCIBIOS_ROUTE_INTERRUPT;
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args.ebx = (bus << 8) | (device << 3);
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args.ecx = (irq << 8) | (0xa + pin - 1); /* pin value is 0xa - 0xd */
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if (!already && bios32(&args, PCIbios.ventry, GSEL(GCODE_SEL, SEL_KPL))) {
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/*
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* XXX if it fails, we should try to smack the router
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* hardware directly.
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* XXX Also, there may be other choices that we can try that
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* will work.
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*/
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PRVERB(("pci_cfgintr: ROUTE_INTERRUPT failed.\n"));
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return(255);
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}
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printf("pci_cfgintr: %d:%d INT%c routed to irq %d\n", bus, device, 'A' + pin - 1, irq);
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return(irq);
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}
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PRVERB(("pci_cfgintr: can't route an interrupt to %d:%d INT%c\n", bus, device, 'A' + pin - 1));
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return(255);
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}
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/*
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* Look to see if the routing table claims this pin is uniquely routed.
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*/
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static int
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pci_cfgintr_unique(struct PIR_entry *pe, int pin)
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{
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int irq;
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if (powerof2(pe->pe_intpin[pin - 1].irqs)) {
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irq = ffs(pe->pe_intpin[pin - 1].irqs) - 1;
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PRVERB(("pci_cfgintr_unique: hard-routed to irq %d\n", irq));
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return(irq);
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}
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return(255);
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}
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/*
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* Look for another device which shares the same link byte and
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* already has a unique IRQ, or which has had one routed already.
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*/
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static int
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pci_cfgintr_linked(struct PIR_entry *pe, int pin)
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{
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struct PIR_entry *oe;
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struct PIR_intpin *pi;
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int i, j, irq;
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/*
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* Scan table slots.
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*/
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for (i = 0, oe = &pci_route_table->pt_entry[0]; i < pci_route_count; i++, oe++) {
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/* scan interrupt pins */
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for (j = 0, pi = &oe->pe_intpin[0]; j < 4; j++, pi++) {
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/* don't look at the entry we're trying to match with */
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if ((pe == oe) && (i == (pin - 1)))
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continue;
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/* compare link bytes */
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if (pi->link != pe->pe_intpin[pin - 1].link)
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continue;
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/* link destination mapped to a unique interrupt? */
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if (powerof2(pi->irqs)) {
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irq = ffs(pi->irqs) - 1;
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PRVERB(("pci_cfgintr_linked: linked (%x) to hard-routed irq %d\n",
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pi->link, irq));
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return(irq);
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}
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/* look for the real PCI device that matches this table entry */
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if ((irq = pci_cfgintr_search(pe, oe->pe_bus, oe->pe_device, j, pin)) != 255)
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return(irq);
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}
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}
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return(255);
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}
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/*
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* Scan for the real PCI device at (bus)/(device) using intpin (matchpin) and
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* see if it has already been assigned an interrupt.
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*/
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static int
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pci_cfgintr_search(struct PIR_entry *pe, int bus, int device, int matchpin, int pin)
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{
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devclass_t pci_devclass;
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device_t *pci_devices;
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int pci_count;
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device_t *pci_children;
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int pci_childcount;
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device_t *busp, *childp;
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int i, j, irq;
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/*
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* Find all the PCI busses.
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*/
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pci_count = 0;
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if ((pci_devclass = devclass_find("pci")) != NULL)
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devclass_get_devices(pci_devclass, &pci_devices, &pci_count);
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/*
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* Scan all the PCI busses/devices looking for this one.
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*/
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irq = 255;
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for (i = 0, busp = pci_devices; (i < pci_count) && (irq == 255); i++, busp++) {
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pci_childcount = 0;
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device_get_children(*busp, &pci_children, &pci_childcount);
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for (j = 0, childp = pci_children; j < pci_childcount; j++, childp++) {
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if ((pci_get_bus(*childp) == bus) &&
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(pci_get_slot(*childp) == device) &&
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(pci_get_intpin(*childp) == matchpin)) {
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irq = pci_get_irq(*childp);
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/*
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* Some BIOS writers seem to want to ignore the spec and put
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* 0 in the intline rather than 255 to indicate none. Once
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* we've found one that matches, we break because there can
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* be no others (which is why test looks a little odd).
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*/
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if (irq == 0)
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irq = 255;
|
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if (irq != 255)
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PRVERB(("pci_cfgintr_search: linked (%x) to configured irq %d at %d:%d:%d\n",
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pe->pe_intpin[pin - 1].link, irq,
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pci_get_bus(*childp), pci_get_slot(*childp), pci_get_function(*childp)));
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break;
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}
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}
|
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if (pci_children != NULL)
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free(pci_children, M_TEMP);
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}
|
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if (pci_devices != NULL)
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free(pci_devices, M_TEMP);
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return(irq);
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}
|
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|
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/*
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* Pick a suitable IRQ from those listed as routable to this device.
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*/
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static int
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pci_cfgintr_virgin(struct PIR_entry *pe, int pin)
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{
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int irq, ibit;
|
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|
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/* first scan the set of PCI-only interrupts and see if any of these are routable */
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for (irq = 0; irq < 16; irq++) {
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ibit = (1 << irq);
|
|
|
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/* can we use this interrupt? */
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if ((pci_route_table->pt_header.ph_pci_irqs & ibit) &&
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(pe->pe_intpin[pin - 1].irqs & ibit)) {
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PRVERB(("pci_cfgintr_virgin: using routable PCI-only interrupt %d\n", irq));
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return(irq);
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}
|
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}
|
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|
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/* life is tough, so just pick an interrupt */
|
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for (irq = 0; irq < 16; irq++) {
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ibit = (1 << irq);
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|
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if (pe->pe_intpin[pin - 1].irqs & ibit) {
|
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PRVERB(("pci_cfgintr_virgin: using routable interrupt %d\n", irq));
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return(irq);
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}
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}
|
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return(255);
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}
|
|
|
|
|
|
/*
|
|
* Config space access using BIOS functions
|
|
*/
|
|
static int
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pcibios_cfgread(int bus, int slot, int func, int reg, int bytes)
|
|
{
|
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struct bios_regs args;
|
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u_int mask;
|
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|
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switch(bytes) {
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case 1:
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args.eax = PCIBIOS_READ_CONFIG_BYTE;
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mask = 0xff;
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break;
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case 2:
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args.eax = PCIBIOS_READ_CONFIG_WORD;
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mask = 0xffff;
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break;
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case 4:
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args.eax = PCIBIOS_READ_CONFIG_DWORD;
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mask = 0xffffffff;
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break;
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default:
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return(-1);
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}
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args.ebx = (bus << 8) | (slot << 3) | func;
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args.edi = reg;
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bios32(&args, PCIbios.ventry, GSEL(GCODE_SEL, SEL_KPL));
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/* check call results? */
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return(args.ecx & mask);
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}
|
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|
|
static void
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pcibios_cfgwrite(int bus, int slot, int func, int reg, int data, int bytes)
|
|
{
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struct bios_regs args;
|
|
|
|
switch(bytes) {
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case 1:
|
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args.eax = PCIBIOS_WRITE_CONFIG_BYTE;
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break;
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case 2:
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args.eax = PCIBIOS_WRITE_CONFIG_WORD;
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break;
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case 4:
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args.eax = PCIBIOS_WRITE_CONFIG_DWORD;
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break;
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default:
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return;
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}
|
|
args.ebx = (bus << 8) | (slot << 3) | func;
|
|
args.ecx = data;
|
|
args.edi = reg;
|
|
bios32(&args, PCIbios.ventry, GSEL(GCODE_SEL, SEL_KPL));
|
|
}
|
|
|
|
/*
|
|
* Determine whether there is a PCI BIOS present
|
|
*/
|
|
static int
|
|
pcibios_cfgopen(void)
|
|
{
|
|
u_int16_t v = 0;
|
|
|
|
if (PCIbios.entry != 0 && enable_pcibios) {
|
|
v = pcibios_get_version();
|
|
if (v > 0)
|
|
printf("pcibios: BIOS version %x.%02x\n", (v & 0xff00) >> 8,
|
|
v & 0xff);
|
|
}
|
|
return (v > 0);
|
|
}
|
|
|
|
/*
|
|
* Configuration space access using direct register operations
|
|
*/
|
|
|
|
/* enable configuration space accesses and return data port address */
|
|
static int
|
|
pci_cfgenable(unsigned bus, unsigned slot, unsigned func, int reg, int bytes)
|
|
{
|
|
int dataport = 0;
|
|
|
|
if (bus <= PCI_BUSMAX
|
|
&& slot < devmax
|
|
&& func <= PCI_FUNCMAX
|
|
&& reg <= PCI_REGMAX
|
|
&& bytes != 3
|
|
&& (unsigned) bytes <= 4
|
|
&& (reg & (bytes -1)) == 0) {
|
|
switch (cfgmech) {
|
|
case 1:
|
|
outl(CONF1_ADDR_PORT, (1 << 31)
|
|
| (bus << 16) | (slot << 11)
|
|
| (func << 8) | (reg & ~0x03));
|
|
dataport = CONF1_DATA_PORT + (reg & 0x03);
|
|
break;
|
|
case 2:
|
|
outb(CONF2_ENABLE_PORT, 0xf0 | (func << 1));
|
|
outb(CONF2_FORWARD_PORT, bus);
|
|
dataport = 0xc000 | (slot << 8) | reg;
|
|
break;
|
|
}
|
|
}
|
|
return (dataport);
|
|
}
|
|
|
|
/* disable configuration space accesses */
|
|
static void
|
|
pci_cfgdisable(void)
|
|
{
|
|
switch (cfgmech) {
|
|
case 1:
|
|
outl(CONF1_ADDR_PORT, 0);
|
|
break;
|
|
case 2:
|
|
outb(CONF2_ENABLE_PORT, 0);
|
|
outb(CONF2_FORWARD_PORT, 0);
|
|
break;
|
|
}
|
|
}
|
|
|
|
static int
|
|
pcireg_cfgread(int bus, int slot, int func, int reg, int bytes)
|
|
{
|
|
int data = -1;
|
|
int port;
|
|
|
|
port = pci_cfgenable(bus, slot, func, reg, bytes);
|
|
|
|
if (port != 0) {
|
|
switch (bytes) {
|
|
case 1:
|
|
data = inb(port);
|
|
break;
|
|
case 2:
|
|
data = inw(port);
|
|
break;
|
|
case 4:
|
|
data = inl(port);
|
|
break;
|
|
}
|
|
pci_cfgdisable();
|
|
}
|
|
return (data);
|
|
}
|
|
|
|
static void
|
|
pcireg_cfgwrite(int bus, int slot, int func, int reg, int data, int bytes)
|
|
{
|
|
int port;
|
|
|
|
port = pci_cfgenable(bus, slot, func, reg, bytes);
|
|
if (port != 0) {
|
|
switch (bytes) {
|
|
case 1:
|
|
outb(port, data);
|
|
break;
|
|
case 2:
|
|
outw(port, data);
|
|
break;
|
|
case 4:
|
|
outl(port, data);
|
|
break;
|
|
}
|
|
pci_cfgdisable();
|
|
}
|
|
}
|
|
|
|
/* check whether the configuration mechanism has been correctly identified */
|
|
static int
|
|
pci_cfgcheck(int maxdev)
|
|
{
|
|
u_char device;
|
|
|
|
if (bootverbose)
|
|
printf("pci_cfgcheck:\tdevice ");
|
|
|
|
for (device = 0; device < maxdev; device++) {
|
|
unsigned id, class, header;
|
|
if (bootverbose)
|
|
printf("%d ", device);
|
|
|
|
id = inl(pci_cfgenable(0, device, 0, 0, 4));
|
|
if (id == 0 || id == -1)
|
|
continue;
|
|
|
|
class = inl(pci_cfgenable(0, device, 0, 8, 4)) >> 8;
|
|
if (bootverbose)
|
|
printf("[class=%06x] ", class);
|
|
if (class == 0 || (class & 0xf870ff) != 0)
|
|
continue;
|
|
|
|
header = inb(pci_cfgenable(0, device, 0, 14, 1));
|
|
if (bootverbose)
|
|
printf("[hdr=%02x] ", header);
|
|
if ((header & 0x7e) != 0)
|
|
continue;
|
|
|
|
if (bootverbose)
|
|
printf("is there (id=%08x)\n", id);
|
|
|
|
pci_cfgdisable();
|
|
return (1);
|
|
}
|
|
if (bootverbose)
|
|
printf("-- nothing found\n");
|
|
|
|
pci_cfgdisable();
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
pcireg_cfgopen(void)
|
|
{
|
|
unsigned long mode1res,oldval1;
|
|
unsigned char mode2res,oldval2;
|
|
|
|
oldval1 = inl(CONF1_ADDR_PORT);
|
|
|
|
if (bootverbose) {
|
|
printf("pci_open(1):\tmode 1 addr port (0x0cf8) is 0x%08lx\n",
|
|
oldval1);
|
|
}
|
|
|
|
if ((oldval1 & CONF1_ENABLE_MSK) == 0) {
|
|
|
|
cfgmech = 1;
|
|
devmax = 32;
|
|
|
|
outl(CONF1_ADDR_PORT, CONF1_ENABLE_CHK);
|
|
outb(CONF1_ADDR_PORT +3, 0);
|
|
mode1res = inl(CONF1_ADDR_PORT);
|
|
outl(CONF1_ADDR_PORT, oldval1);
|
|
|
|
if (bootverbose)
|
|
printf("pci_open(1a):\tmode1res=0x%08lx (0x%08lx)\n",
|
|
mode1res, CONF1_ENABLE_CHK);
|
|
|
|
if (mode1res) {
|
|
if (pci_cfgcheck(32))
|
|
return (cfgmech);
|
|
}
|
|
|
|
outl(CONF1_ADDR_PORT, CONF1_ENABLE_CHK1);
|
|
mode1res = inl(CONF1_ADDR_PORT);
|
|
outl(CONF1_ADDR_PORT, oldval1);
|
|
|
|
if (bootverbose)
|
|
printf("pci_open(1b):\tmode1res=0x%08lx (0x%08lx)\n",
|
|
mode1res, CONF1_ENABLE_CHK1);
|
|
|
|
if ((mode1res & CONF1_ENABLE_MSK1) == CONF1_ENABLE_RES1) {
|
|
if (pci_cfgcheck(32))
|
|
return (cfgmech);
|
|
}
|
|
}
|
|
|
|
oldval2 = inb(CONF2_ENABLE_PORT);
|
|
|
|
if (bootverbose) {
|
|
printf("pci_open(2):\tmode 2 enable port (0x0cf8) is 0x%02x\n",
|
|
oldval2);
|
|
}
|
|
|
|
if ((oldval2 & 0xf0) == 0) {
|
|
|
|
cfgmech = 2;
|
|
devmax = 16;
|
|
|
|
outb(CONF2_ENABLE_PORT, CONF2_ENABLE_CHK);
|
|
mode2res = inb(CONF2_ENABLE_PORT);
|
|
outb(CONF2_ENABLE_PORT, oldval2);
|
|
|
|
if (bootverbose)
|
|
printf("pci_open(2a):\tmode2res=0x%02x (0x%02x)\n",
|
|
mode2res, CONF2_ENABLE_CHK);
|
|
|
|
if (mode2res == CONF2_ENABLE_RES) {
|
|
if (bootverbose)
|
|
printf("pci_open(2a):\tnow trying mechanism 2\n");
|
|
|
|
if (pci_cfgcheck(16))
|
|
return (cfgmech);
|
|
}
|
|
}
|
|
|
|
cfgmech = 0;
|
|
devmax = 0;
|
|
return (cfgmech);
|
|
}
|
|
|