257 lines
7.4 KiB
C
257 lines
7.4 KiB
C
/*-
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* Copyright (c) 2005 Olivier Houchard. All rights reserved.
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* Copyright (c) 2010 Greg Ansley. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/malloc.h>
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#include <sys/module.h>
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#define _ARM32_BUS_DMA_PRIVATE
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#include <machine/bus.h>
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#include <arm/at91/at91var.h>
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#include <arm/at91/at91reg.h>
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#include <arm/at91/at91soc.h>
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#include <arm/at91/at91_aicreg.h>
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#include <arm/at91/at91sam9g20reg.h>
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#include <arm/at91/at91_pitreg.h>
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#include <arm/at91/at91_pmcreg.h>
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#include <arm/at91/at91_pmcvar.h>
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#include <arm/at91/at91_rstreg.h>
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struct at91sam9_softc {
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bus_space_tag_t sc_st;
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bus_space_handle_t sc_sh;
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bus_space_handle_t sc_matrix_sh;
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};
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/*
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* Standard priority levels for the system. 0 is lowest and 7 is highest.
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* These values are the ones Atmel uses for its Linux port
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*/
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static const int at91_irq_prio[32] =
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{
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7, /* Advanced Interrupt Controller */
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7, /* System Peripherals */
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1, /* Parallel IO Controller A */
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1, /* Parallel IO Controller B */
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1, /* Parallel IO Controller C */
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0, /* Analog-to-Digital Converter */
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5, /* USART 0 */
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5, /* USART 1 */
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5, /* USART 2 */
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0, /* Multimedia Card Interface */
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2, /* USB Device Port */
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6, /* Two-Wire Interface */
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5, /* Serial Peripheral Interface 0 */
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5, /* Serial Peripheral Interface 1 */
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5, /* Serial Synchronous Controller */
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0, /* (reserved) */
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0, /* (reserved) */
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0, /* Timer Counter 0 */
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0, /* Timer Counter 1 */
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0, /* Timer Counter 2 */
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2, /* USB Host port */
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3, /* Ethernet */
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0, /* Image Sensor Interface */
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5, /* USART 3 */
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5, /* USART 4 */
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5, /* USART 5 */
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0, /* Timer Counter 3 */
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0, /* Timer Counter 4 */
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0, /* Timer Counter 5 */
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0, /* Advanced Interrupt Controller IRQ0 */
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0, /* Advanced Interrupt Controller IRQ1 */
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0, /* Advanced Interrupt Controller IRQ2 */
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};
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#define DEVICE(_name, _id, _unit) \
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{ \
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_name, _unit, \
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AT91SAM9G20_ ## _id ##_BASE, \
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AT91SAM9G20_ ## _id ## _SIZE, \
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AT91SAM9G20_IRQ_ ## _id \
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}
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static const struct cpu_devs at91_devs[] =
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{
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DEVICE("at91_pmc", PMC, 0),
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DEVICE("at91_wdt", WDT, 0),
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DEVICE("at91_rst", RSTC, 0),
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DEVICE("at91_pit", PIT, 0),
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DEVICE("at91_pio", PIOA, 0),
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DEVICE("at91_pio", PIOB, 1),
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DEVICE("at91_pio", PIOC, 2),
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DEVICE("at91_twi", TWI, 0),
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DEVICE("at91_mci", MCI, 0),
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DEVICE("uart", DBGU, 0),
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DEVICE("uart", USART0, 1),
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DEVICE("uart", USART1, 2),
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DEVICE("uart", USART2, 3),
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DEVICE("uart", USART3, 4),
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DEVICE("uart", USART4, 5),
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DEVICE("uart", USART5, 6),
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DEVICE("spi", SPI0, 0),
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DEVICE("spi", SPI1, 1),
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DEVICE("ate", EMAC, 0),
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DEVICE("macb", EMAC, 0),
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DEVICE("nand", NAND, 0),
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DEVICE("ohci", OHCI, 0),
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{ 0, 0, 0, 0, 0 }
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};
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static uint32_t
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at91_pll_outa(int freq)
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{
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switch (freq / 10000000) {
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case 747 ... 801: return ((1 << 29) | (0 << 14));
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case 697 ... 746: return ((1 << 29) | (1 << 14));
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case 647 ... 696: return ((1 << 29) | (2 << 14));
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case 597 ... 646: return ((1 << 29) | (3 << 14));
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case 547 ... 596: return ((1 << 29) | (1 << 14));
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case 497 ... 546: return ((1 << 29) | (2 << 14));
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case 447 ... 496: return ((1 << 29) | (3 << 14));
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case 397 ... 446: return ((1 << 29) | (4 << 14));
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default: return (1 << 29);
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}
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}
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static uint32_t
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at91_pll_outb(int freq)
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{
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return (0);
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}
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static void
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at91_identify(driver_t *drv, device_t parent)
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{
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if (at91_cpu_is(AT91_T_SAM9G20))
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at91_add_child(parent, 0, "at91sam", 9, 0, 0, -1, 0, 0);
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}
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static int
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at91_probe(device_t dev)
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{
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device_set_desc(dev, soc_info.name);
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return (0);
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}
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static int
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at91_attach(device_t dev)
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{
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struct at91_pmc_clock *clk;
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struct at91sam9_softc *sc = device_get_softc(dev);
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struct at91_softc *at91sc = device_get_softc(device_get_parent(dev));
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uint32_t i;
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sc->sc_st = at91sc->sc_st;
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sc->sc_sh = at91sc->sc_sh;
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if (bus_space_subregion(sc->sc_st, sc->sc_sh,
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AT91SAM9G20_MATRIX_BASE, AT91SAM9G20_MATRIX_SIZE,
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&sc->sc_matrix_sh) != 0)
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panic("Enable to map matrix registers");
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/* activate NAND*/
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i = bus_space_read_4(sc->sc_st, sc->sc_matrix_sh,
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AT91SAM9G20_EBICSA);
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bus_space_write_4(sc->sc_st, sc->sc_matrix_sh,
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AT91SAM9G20_EBICSA,
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i | AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA);
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/* Update USB device port clock info */
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clk = at91_pmc_clock_ref("udpck");
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clk->pmc_mask = PMC_SCER_UDP_SAM9;
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at91_pmc_clock_deref(clk);
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/* Update USB host port clock info */
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clk = at91_pmc_clock_ref("uhpck");
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clk->pmc_mask = PMC_SCER_UHP_SAM9;
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at91_pmc_clock_deref(clk);
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/* Each SOC has different PLL contraints */
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clk = at91_pmc_clock_ref("plla");
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clk->pll_min_in = SAM9G20_PLL_A_MIN_IN_FREQ; /* 2 MHz */
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clk->pll_max_in = SAM9G20_PLL_A_MAX_IN_FREQ; /* 32 MHz */
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clk->pll_min_out = SAM9G20_PLL_A_MIN_OUT_FREQ; /* 400 MHz */
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clk->pll_max_out = SAM9G20_PLL_A_MAX_OUT_FREQ; /* 800 MHz */
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clk->pll_mul_shift = SAM9G20_PLL_A_MUL_SHIFT;
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clk->pll_mul_mask = SAM9G20_PLL_A_MUL_MASK;
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clk->pll_div_shift = SAM9G20_PLL_A_DIV_SHIFT;
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clk->pll_div_mask = SAM9G20_PLL_A_DIV_MASK;
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clk->set_outb = at91_pll_outa;
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at91_pmc_clock_deref(clk);
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clk = at91_pmc_clock_ref("pllb");
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clk->pll_min_in = SAM9G20_PLL_B_MIN_IN_FREQ; /* 2 MHz */
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clk->pll_max_in = SAM9G20_PLL_B_MAX_IN_FREQ; /* 32 MHz */
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clk->pll_min_out = SAM9G20_PLL_B_MIN_OUT_FREQ; /* 30 MHz */
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clk->pll_max_out = SAM9G20_PLL_B_MAX_OUT_FREQ; /* 100 MHz */
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clk->pll_mul_shift = SAM9G20_PLL_B_MUL_SHIFT;
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clk->pll_mul_mask = SAM9G20_PLL_B_MUL_MASK;
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clk->pll_div_shift = SAM9G20_PLL_B_DIV_SHIFT;
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clk->pll_div_mask = SAM9G20_PLL_B_DIV_MASK;
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clk->set_outb = at91_pll_outb;
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at91_pmc_clock_deref(clk);
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return (0);
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}
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static device_method_t at91_methods[] = {
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DEVMETHOD(device_probe, at91_probe),
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DEVMETHOD(device_attach, at91_attach),
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DEVMETHOD(device_identify, at91_identify),
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{0, 0},
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};
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static driver_t at91sam9_driver = {
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"at91sam",
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at91_methods,
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sizeof(struct at91sam9_softc),
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};
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static devclass_t at91sam9_devclass;
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DRIVER_MODULE(at91sam, atmelarm, at91sam9_driver, at91sam9_devclass, 0, 0);
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static struct at91_soc_data soc_data = {
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.soc_delay = at91_pit_delay,
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.soc_reset = at91_rst_cpu_reset,
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.soc_irq_prio = at91_irq_prio,
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.soc_childpren = at91_devs,
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};
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AT91_SOC(AT91_T_SAM9G20, &soc_data);
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