548d35fd69
Features: Jumbo frames (up to 9600), LRO (Large Receive Offload),
TSO (TCP segmentation offload), RTH (Receive Traffic Hash).
Submitted by: Sriram Rapuru at Exar
MFC after: 2 weeks
1232 lines
60 KiB
C
1232 lines
60 KiB
C
/*-
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* Copyright(c) 2002-2011 Exar Corp.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification are permitted provided the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the Exar Corporation nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*$FreeBSD$*/
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#ifndef VXGE_HAL_REGS_H
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#define VXGE_HAL_REGS_H
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__EXTERN_BEGIN_DECLS
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#pragma pack(1)
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/* Using this strcture to calculate offsets */
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typedef struct vxge_hal_pci_config_le_t {
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u16 vendor_id; /* 0x00 */
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u16 device_id; /* 0x02 */
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u16 command; /* 0x04 */
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u16 status; /* 0x06 */
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u8 revision; /* 0x08 */
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u8 pciClass[3]; /* 0x09 */
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u8 cache_line_size; /* 0x0c */
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u8 latency_timer; /* 0x0d */
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u8 header_type; /* 0x0e */
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u8 bist; /* 0x0f */
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u32 base_addr0_lo; /* 0x10 */
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u32 base_addr0_hi; /* 0x14 */
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u32 base_addr1_lo; /* 0x18 */
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u32 base_addr1_hi; /* 0x1C */
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u32 base_addr2_lo; /* 0x20 */
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u32 base_addr2_hi; /* 0x24 */
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u32 cardbus_cis_pointer; /* 0x28 */
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u16 subsystem_vendor_id; /* 0x2c */
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u16 subsystem_id; /* 0x2e */
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u32 rom_base; /* 0x30 */
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u8 capabilities_pointer; /* 0x34 */
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u8 rsvd_35[3]; /* 0x35 */
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u32 rsvd_38; /* 0x38 */
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u8 interrupt_line; /* 0x3c */
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u8 interrupt_pin; /* 0x3d */
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u8 min_grant; /* 0x3e */
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u8 max_latency; /* 0x3f */
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u8 rsvd_b1[VXGE_HAL_PCI_CONFIG_SPACE_SIZE - 0x40];
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} vxge_hal_pci_config_le_t; /* 0x100 */
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typedef struct vxge_hal_pci_config_t {
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#if defined(VXGE_OS_HOST_BIG_ENDIAN)
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u16 device_id; /* 0x02 */
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u16 vendor_id; /* 0x00 */
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u16 status; /* 0x06 */
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u16 command; /* 0x04 */
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u8 pciClass[3]; /* 0x09 */
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u8 revision; /* 0x08 */
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u8 bist; /* 0x0f */
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u8 header_type; /* 0x0e */
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u8 latency_timer; /* 0x0d */
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u8 cache_line_size; /* 0x0c */
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u32 base_addr0_lo; /* 0x10 */
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u32 base_addr0_hi; /* 0x14 */
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u32 base_addr1_lo; /* 0x18 */
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u32 base_addr1_hi; /* 0x1C */
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u32 not_Implemented1; /* 0x20 */
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u32 not_Implemented2; /* 0x24 */
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u32 cardbus_cis_pointer; /* 0x28 */
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u16 subsystem_id; /* 0x2e */
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u16 subsystem_vendor_id; /* 0x2c */
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u32 rom_base; /* 0x30 */
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u8 rsvd_35[3]; /* 0x35 */
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u8 capabilities_pointer; /* 0x34 */
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u32 rsvd_38; /* 0x38 */
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u8 max_latency; /* 0x3f */
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u8 min_grant; /* 0x3e */
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u8 interrupt_pin; /* 0x3d */
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u8 interrupt_line; /* 0x3c */
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#else
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u16 vendor_id; /* 0x00 */
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u16 device_id; /* 0x02 */
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u16 command; /* 0x04 */
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u16 status; /* 0x06 */
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u8 revision; /* 0x08 */
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u8 pciClass[3]; /* 0x09 */
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u8 cache_line_size; /* 0x0c */
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u8 latency_timer; /* 0x0d */
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u8 header_type; /* 0x0e */
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u8 bist; /* 0x0f */
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u32 base_addr0_lo; /* 0x10 */
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u32 base_addr0_hi; /* 0x14 */
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u32 base_addr1_lo; /* 0x18 */
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u32 base_addr1_hi; /* 0x1C */
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u32 not_Implemented1; /* 0x20 */
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u32 not_Implemented2; /* 0x24 */
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u32 cardbus_cis_pointer; /* 0x28 */
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u16 subsystem_vendor_id; /* 0x2c */
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u16 subsystem_id; /* 0x2e */
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u32 rom_base; /* 0x30 */
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u8 capabilities_pointer; /* 0x34 */
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u8 rsvd_35[3]; /* 0x35 */
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u32 rsvd_38; /* 0x38 */
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u8 interrupt_line; /* 0x3c */
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u8 interrupt_pin; /* 0x3d */
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u8 min_grant; /* 0x3e */
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u8 max_latency; /* 0x3f */
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#endif
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u8 rsvd_b1[VXGE_HAL_PCI_CONFIG_SPACE_SIZE - 0x40];
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} vxge_hal_pci_config_t; /* 0x100 */
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#define VXGE_HAL_EEPROM_SIZE (0x01 << 11)
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#if defined(VXGE_OS_HOST_BIG_ENDIAN)
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#define VXGE_HAL_PCI_CAP_ID(ptr) *((ptr) + 3)
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#define VXGE_HAL_PCI_CAP_NEXT(ptr) *((ptr) + 2)
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#else
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#define VXGE_HAL_PCI_CAP_ID(ptr) *(ptr)
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#define VXGE_HAL_PCI_CAP_NEXT(ptr) *((ptr) + 1)
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#endif
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/* Capability lists */
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#define VXGE_HAL_PCI_CAP_LIST_ID 0 /* Capability ID */
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#define VXGE_HAL_PCI_CAP_ID_PM 0x01 /* Power Management */
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#define VXGE_HAL_PCI_CAP_ID_AGP 0x02 /* Accelerated Graphics Port */
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#define VXGE_HAL_PCI_CAP_ID_VPD 0x03 /* Vital Product Data */
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#define VXGE_HAL_PCI_CAP_ID_SLOTID 0x04 /* Slot Identification */
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#define VXGE_HAL_PCI_CAP_ID_MSI 0x05 /* Message Signalled Intr */
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#define VXGE_HAL_PCI_CAP_ID_CHSWP 0x06 /* CompactPCI HotSwap */
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#define VXGE_HAL_PCI_CAP_ID_PCIX 0x07 /* PCIX */
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#define VXGE_HAL_PCI_CAP_ID_HT 0x08 /* Hypertransport */
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#define VXGE_HAL_PCI_CAP_ID_VS 0x09 /* Vendor Specific */
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#define VXGE_HAL_PCI_CAP_ID_DBGPORT 0x0A /* Debug Port */
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#define VXGE_HAL_PCI_CAP_ID_CPCICSR 0x0B /* CompPCI central res ctrl */
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#define VXGE_HAL_PCI_CAP_ID_SHPC 0x0C /* PCI Standard Hot-Plug Ctrl */
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#define VXGE_HAL_PCI_CAP_ID_PCIBSVID 0x0D /* PCI Bridge Subsys Vendr Id */
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#define VXGE_HAL_PCI_CAP_ID_AGP8X 0x0E /* AGP 8x */
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#define VXGE_HAL_PCI_CAP_ID_SECDEV 0x0F /* Secure Device */
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#define VXGE_HAL_PCI_CAP_ID_PCIE 0x10 /* PCI Express */
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#define VXGE_HAL_PCI_CAP_ID_MSIX 0x11 /* MSI-X */
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#define VXGE_HAL_PCI_CAP_LIST_NEXT 1 /* Next cap in the list */
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#define VXGE_HAL_PCI_CAP_FLAGS 2 /* Cap defined flags(16 bits) */
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typedef struct vxge_hal_pm_capability_le_t {
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u8 capability_id;
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u8 next_capability_ptr;
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u16 capabilities_reg;
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#define VXGE_HAL_PCI_PM_CAP_VER_MASK 0x0007 /* Version */
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#define VXGE_HAL_PCI_PM_CAP_PME_CLOCK 0x0008 /* PME clock required */
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#define VXGE_HAL_PCI_PM_CAP_AUX_POWER 0x0010 /* Auxilliary power support */
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#define VXGE_HAL_PCI_PM_CAP_DSI 0x0020 /* Device specific init */
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#define VXGE_HAL_PCI_PM_AUX_CURRENT 0x01C0 /* Auxiliary current reqs */
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#define VXGE_HAL_PCI_PM_CAP_D1 0x0200 /* D1 power state support */
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#define VXGE_HAL_PCI_PM_CAP_D2 0x0400 /* D2 power state support */
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#define VXGE_HAL_PCI_PM_CAP_PME_D0 0x0800 /* PME# assertable from D0 */
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#define VXGE_HAL_PCI_PM_CAP_PME_D1 0x1000 /* PME# assertable from D1 */
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#define VXGE_HAL_PCI_PM_CAP_PME_D2 0x2000 /* PME# assertable from D2 */
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#define VXGE_HAL_PCI_PM_CAP_PME_D3_HOT 0x4000 /* PME# assertable from D3hot */
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#define VXGE_HAL_PCI_PM_CAP_PME_D3_COLD 0x8000 /* PME# assertable from D3cold */
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u16 pm_ctrl;
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#define VXGE_HAL_PCI_PM_CTRL_STATE_MASK 0x0003 /* Curr power state(D0 to D3) */
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#define VXGE_HAL_PCI_PM_CTRL_NO_SOFT_RESET 0x0008 /* trans from D3hot to D0 */
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#define VXGE_HAL_PCI_PM_CTRL_PME_ENABLE 0x0100 /* PME pin enable */
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#define VXGE_HAL_PCI_PM_CTRL_DATA_SEL_MASK 0x1e00 /* Data select (??) */
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#define VXGE_HAL_PCI_PM_CTRL_DATA_SCALE_MASK 0x6000 /* Data scale (??) */
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#define VXGE_HAL_PCI_PM_CTRL_PME_STATUS 0x8000 /* PME pin status */
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u8 pm_ppb_ext;
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#define VXGE_HAL_PCI_PM_PPB_B2_B3 0x40 /* Stop clk when in D3hot(??) */
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#define VXGE_HAL_PCI_PM_BPCC_ENABLE 0x80 /* Bus pwr/clk ctrl enable(??) */
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u8 pm_data_reg;
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} vxge_hal_pm_capability_le_t;
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typedef struct vxge_hal_pm_capability_t {
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#if defined(VXGE_OS_HOST_BIG_ENDIAN)
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u16 capabilities_reg;
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#define VXGE_HAL_PCI_PM_CAP_VER_MASK 0x0007 /* Version */
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#define VXGE_HAL_PCI_PM_CAP_PME_CLOCK 0x0008 /* PME clock required */
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#define VXGE_HAL_PCI_PM_CAP_AUX_POWER 0x0010 /* Auxilliary power support */
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#define VXGE_HAL_PCI_PM_CAP_DSI 0x0020 /* Dev specific init */
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#define VXGE_HAL_PCI_PM_AUX_CURRENT 0x01C0 /* Auxiliary current reqs */
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#define VXGE_HAL_PCI_PM_CAP_D1 0x0200 /* D1 power state support */
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#define VXGE_HAL_PCI_PM_CAP_D2 0x0400 /* D2 power state support */
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#define VXGE_HAL_PCI_PM_CAP_PME_D0 0x0800 /* PME# assertable from D0 */
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#define VXGE_HAL_PCI_PM_CAP_PME_D1 0x1000 /* PME# assertable from D1 */
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#define VXGE_HAL_PCI_PM_CAP_PME_D2 0x2000 /* PME# assertable from D2 */
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#define VXGE_HAL_PCI_PM_CAP_PME_D3_HOT 0x4000 /* PME# assertable from D3hot */
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#define VXGE_HAL_PCI_PM_CAP_PME_D3_COLD 0x8000 /* PME# assertable from D3cold */
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u8 next_capability_ptr;
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u8 capability_id;
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u8 pm_data_reg;
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u8 pm_ppb_ext;
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#define VXGE_HAL_PCI_PM_PPB_B2_B3 0x40 /* Stop clk when in D3hot(??) */
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#define VXGE_HAL_PCI_PM_BPCC_ENABLE 0x80 /* Bus pwr/clk ctrl enable(??) */
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u16 pm_ctrl;
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#define VXGE_HAL_PCI_PM_CTRL_STATE_MASK 0x0003 /* Curr pwr state (D0 to D3) */
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#define VXGE_HAL_PCI_PM_CTRL_NO_SOFT_RESET 0x0008 /* dev trans D3hot to D0 */
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#define VXGE_HAL_PCI_PM_CTRL_PME_ENABLE 0x0100 /* PME pin enable */
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#define VXGE_HAL_PCI_PM_CTRL_DATA_SEL_MASK 0x1e00 /* Data select (??) */
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#define VXGE_HAL_PCI_PM_CTRL_DATA_SCALE_MASK 0x6000 /* Data scale (??) */
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#define VXGE_HAL_PCI_PM_CTRL_PME_STATUS 0x8000 /* PME pin status */
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#else
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u8 capability_id;
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u8 next_capability_ptr;
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u16 capabilities_reg;
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#define VXGE_HAL_PCI_PM_CAP_VER_MASK 0x0007 /* Version */
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#define VXGE_HAL_PCI_PM_CAP_PME_CLOCK 0x0008 /* PME clock required */
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#define VXGE_HAL_PCI_PM_CAP_AUX_POWER 0x0010 /* Auxilliary power support */
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#define VXGE_HAL_PCI_PM_CAP_DSI 0x0020 /* Dev specific init */
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#define VXGE_HAL_PCI_PM_AUX_CURRENT 0x01C0 /* Auxiliary curr reqs */
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#define VXGE_HAL_PCI_PM_CAP_D1 0x0200 /* D1 power state support */
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#define VXGE_HAL_PCI_PM_CAP_D2 0x0400 /* D2 power state support */
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#define VXGE_HAL_PCI_PM_CAP_PME_D0 0x0800 /* PME# assertable from D0 */
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#define VXGE_HAL_PCI_PM_CAP_PME_D1 0x1000 /* PME# assertable from D1 */
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#define VXGE_HAL_PCI_PM_CAP_PME_D2 0x2000 /* PME# assertable from D2 */
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#define VXGE_HAL_PCI_PM_CAP_PME_D3_HOT 0x4000 /* PME# assertable from D3hot */
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#define VXGE_HAL_PCI_PM_CAP_PME_D3_COLD 0x8000 /* PME# assertable from D3cold */
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u16 pm_ctrl;
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#define VXGE_HAL_PCI_PM_CTRL_STATE_MASK 0x0003 /* Curr pwr state (D0 to D3) */
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#define VXGE_HAL_PCI_PM_CTRL_NO_SOFT_RESET 0x0008 /* dev trans D3hot to D0 */
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#define VXGE_HAL_PCI_PM_CTRL_PME_ENABLE 0x0100 /* PME pin enable */
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#define VXGE_HAL_PCI_PM_CTRL_DATA_SEL_MASK 0x1e00 /* Data select (??) */
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#define VXGE_HAL_PCI_PM_CTRL_DATA_SCALE_MASK 0x6000 /* Data scale (??) */
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#define VXGE_HAL_PCI_PM_CTRL_PME_STATUS 0x8000 /* PME pin status */
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u8 pm_ppb_ext;
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#define VXGE_HAL_PCI_PM_PPB_B2_B3 0x40 /* Stop clk when in D3hot(??) */
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#define VXGE_HAL_PCI_PM_BPCC_ENABLE 0x80 /* Bus pwr/clk ctrl enable(??) */
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u8 pm_data_reg;
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#endif
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} vxge_hal_pm_capability_t;
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typedef struct vxge_hal_vpid_capability_le_t {
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u8 capability_id;
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u8 next_capability_ptr;
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u16 vpd_address;
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#define VXGE_HAL_PCI_VPID_COMPL_FALG 0x8000 /* Read Completion Flag */
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u32 vpd_data;
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} vxge_hal_vpid_capability_le_t;
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typedef struct vxge_hal_vpid_capability_t {
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#if defined(VXGE_OS_HOST_BIG_ENDIAN)
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u16 vpd_address;
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#define VXGE_HAL_PCI_VPID_COMPL_FALG 0x8000 /* Read Completion Flag */
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u8 next_capability_ptr;
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u8 capability_id;
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u32 vpd_data;
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#else
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u8 capability_id;
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u8 next_capability_ptr;
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u16 vpd_address;
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#define VXGE_HAL_PCI_VPID_COMPL_FALG 0x8000 /* Read Completion Flag */
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u32 vpd_data;
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#endif
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} vxge_hal_vpid_capability_t;
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typedef struct vxge_hal_sid_capability_le_t {
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u8 capability_id;
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u8 next_capability_ptr;
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u8 sid_esr;
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#define VXGE_HAL_PCI_SID_ESR_NSLOTS 0x1f /* Num of exp slots avail */
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#define VXGE_HAL_PCI_SID_ESR_FIC 0x20 /* First In Chassis Flag */
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u8 sid_chasis_nr;
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} vxge_hal_sid_capability_le_t;
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typedef struct vxge_hal_sid_capability_t {
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#if defined(VXGE_OS_HOST_BIG_ENDIAN)
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u8 sid_chasis_nr;
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u8 sid_esr;
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#define VXGE_HAL_PCI_SID_ESR_NSLOTS 0x1f /* Num of exp slots avail */
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#define VXGE_HAL_PCI_SID_ESR_FIC 0x20 /* First In Chassis Flag */
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u8 next_capability_ptr;
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u8 capability_id;
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#else
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u8 capability_id;
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u8 next_capability_ptr;
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u8 sid_esr;
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#define VXGE_HAL_PCI_SID_ESR_NSLOTS 0x1f /* Num of exp slots avail */
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#define VXGE_HAL_PCI_SID_ESR_FIC 0x20 /* First In Chassis Flag */
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u8 sid_chasis_nr;
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#endif
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} vxge_hal_sid_capability_t;
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typedef struct vxge_hal_msi_capability_le_t {
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u8 capability_id;
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u8 next_capability_ptr;
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u16 msi_control;
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#define VXGE_HAL_PCI_MSI_FLAGS_PVMASK 0x0100 /* Per Vector Masking Capable */
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#define VXGE_HAL_PCI_MSI_FLAGS_64BIT 0x0080 /* 64-bit addresses allowed */
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#define VXGE_HAL_PCI_MSI_FLAGS_QSIZE 0x0070 /* Msg queue size configured */
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#define VXGE_HAL_PCI_MSI_FLAGS_QMASK 0x000e /* Max queue size available */
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#define VXGE_HAL_PCI_MSI_FLAGS_ENABLE 0x0001 /* MSI feature enabled */
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union {
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struct {
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u32 msi_addr;
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u16 msi_data;
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u16 msi_unused;
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} ma32_no_pvm;
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struct {
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u32 msi_addr;
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u16 msi_data;
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u16 msi_unused;
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u32 msi_mask;
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u32 msi_pending;
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} ma32_pvm;
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struct {
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u32 msi_addr_lo;
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u32 msi_addr_hi;
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u16 msi_data;
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u16 msi_unused;
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} ma64_no_pvm;
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struct {
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u32 msi_addr_lo;
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u32 msi_addr_hi;
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u16 msi_data;
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u16 msi_unused;
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u32 msi_mask;
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u32 msi_pending;
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} ma64_pvm;
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} au;
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} vxge_hal_msi_capability_le_t;
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typedef struct vxge_hal_msi_capability_t {
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#if defined(VXGE_OS_HOST_BIG_ENDIAN)
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u16 msi_control;
|
|
#define VXGE_HAL_PCI_MSI_FLAGS_PVMASK 0x0100 /* Per Vector Masking Capable */
|
|
#define VXGE_HAL_PCI_MSI_FLAGS_64BIT 0x0080 /* 64-bit addresses allowed */
|
|
#define VXGE_HAL_PCI_MSI_FLAGS_QSIZE 0x0070 /* Msg queue size configured */
|
|
#define VXGE_HAL_PCI_MSI_FLAGS_QMASK 0x000e /* Max queue size available */
|
|
#define VXGE_HAL_PCI_MSI_FLAGS_ENABLE 0x0001 /* MSI feature enabled */
|
|
u8 next_capability_ptr;
|
|
u8 capability_id;
|
|
union {
|
|
struct {
|
|
u32 msi_addr;
|
|
u16 msi_unused;
|
|
u16 msi_data;
|
|
} ma32_no_pvm;
|
|
struct {
|
|
u32 msi_addr;
|
|
u16 msi_unused;
|
|
u16 msi_data;
|
|
u32 msi_mask;
|
|
u32 msi_pending;
|
|
} ma32_pvm;
|
|
struct {
|
|
u32 msi_addr_lo;
|
|
u32 msi_addr_hi;
|
|
u16 msi_unused;
|
|
u16 msi_data;
|
|
} ma64_no_pvm;
|
|
struct {
|
|
u32 msi_addr_lo;
|
|
u32 msi_addr_hi;
|
|
u16 msi_unused;
|
|
u16 msi_data;
|
|
u32 msi_mask;
|
|
u32 msi_pending;
|
|
} ma64_pvm;
|
|
} au;
|
|
#else
|
|
u8 capability_id;
|
|
u8 next_capability_ptr;
|
|
u16 msi_control;
|
|
#define VXGE_HAL_PCI_MSI_FLAGS_PVMASK 0x0100 /* Per Vector Masking Capable */
|
|
#define VXGE_HAL_PCI_MSI_FLAGS_64BIT 0x0080 /* 64-bit addresses allowed */
|
|
#define VXGE_HAL_PCI_MSI_FLAGS_QSIZE 0x0070 /* Msg queue size configured */
|
|
#define VXGE_HAL_PCI_MSI_FLAGS_QMASK 0x000e /* Max queue size available */
|
|
#define VXGE_HAL_PCI_MSI_FLAGS_ENABLE 0x0001 /* MSI feature enabled */
|
|
union {
|
|
struct {
|
|
u32 msi_addr;
|
|
u16 msi_data;
|
|
u16 msi_unused;
|
|
} ma32_no_pvm;
|
|
struct {
|
|
u32 msi_addr;
|
|
u16 msi_data;
|
|
u16 msi_unused;
|
|
u32 msi_mask;
|
|
u32 msi_pending;
|
|
} ma32_pvm;
|
|
struct {
|
|
u32 msi_addr_lo;
|
|
u32 msi_addr_hi;
|
|
u16 msi_data;
|
|
u16 msi_unused;
|
|
} ma64_no_pvm;
|
|
struct {
|
|
u32 msi_addr_lo;
|
|
u32 msi_addr_hi;
|
|
u16 msi_data;
|
|
u16 msi_unused;
|
|
u32 msi_mask;
|
|
u32 msi_pending;
|
|
} ma64_pvm;
|
|
} au;
|
|
#endif
|
|
} vxge_hal_msi_capability_t;
|
|
|
|
typedef struct vxge_hal_chswp_capability_le_t {
|
|
u8 capability_id;
|
|
u8 next_capability_ptr;
|
|
u8 chswp_csr;
|
|
#define VXGE_HAL_PCI_CHSWP_DHA 0x01 /* Device Hiding Arm */
|
|
#define VXGE_HAL_PCI_CHSWP_EIM 0x02 /* ENUM# Signal Mask */
|
|
#define VXGE_HAL_PCI_CHSWP_PIE 0x04 /* Pending Insert or Extract */
|
|
#define VXGE_HAL_PCI_CHSWP_LOO 0x08 /* LED On / Off */
|
|
#define VXGE_HAL_PCI_CHSWP_PI 0x30 /* Programming Interface */
|
|
#define VXGE_HAL_PCI_CHSWP_EXT 0x40 /* ENUM# status - extraction */
|
|
#define VXGE_HAL_PCI_CHSWP_INS 0x80 /* ENUM# status - insertion */
|
|
} vxge_hal_chswp_capability_le_t;
|
|
|
|
typedef struct vxge_hal_chswp_capability_t {
|
|
#if defined(VXGE_OS_HOST_BIG_ENDIAN)
|
|
u8 chswp_csr;
|
|
#define VXGE_HAL_PCI_CHSWP_DHA 0x01 /* Device Hiding Arm */
|
|
#define VXGE_HAL_PCI_CHSWP_EIM 0x02 /* ENUM# Signal Mask */
|
|
#define VXGE_HAL_PCI_CHSWP_PIE 0x04 /* Pending Insert or Extract */
|
|
#define VXGE_HAL_PCI_CHSWP_LOO 0x08 /* LED On / Off */
|
|
#define VXGE_HAL_PCI_CHSWP_PI 0x30 /* Programming Interface */
|
|
#define VXGE_HAL_PCI_CHSWP_EXT 0x40 /* ENUM# status - extraction */
|
|
#define VXGE_HAL_PCI_CHSWP_INS 0x80 /* ENUM# status - insertion */
|
|
u8 next_capability_ptr;
|
|
u8 capability_id;
|
|
#else
|
|
u8 capability_id;
|
|
u8 next_capability_ptr;
|
|
u8 chswp_csr;
|
|
#define VXGE_HAL_PCI_CHSWP_DHA 0x01 /* Device Hiding Arm */
|
|
#define VXGE_HAL_PCI_CHSWP_EIM 0x02 /* ENUM# Signal Mask */
|
|
#define VXGE_HAL_PCI_CHSWP_PIE 0x04 /* Pending Insert or Extract */
|
|
#define VXGE_HAL_PCI_CHSWP_LOO 0x08 /* LED On / Off */
|
|
#define VXGE_HAL_PCI_CHSWP_PI 0x30 /* Programming Interface */
|
|
#define VXGE_HAL_PCI_CHSWP_EXT 0x40 /* ENUM# status - extraction */
|
|
#define VXGE_HAL_PCI_CHSWP_INS 0x80 /* ENUM# status - insertion */
|
|
#endif
|
|
} vxge_hal_chswp_capability_t;
|
|
|
|
typedef struct vxge_hal_shpc_capability_le_t {
|
|
u8 capability_id;
|
|
u8 next_capability_ptr;
|
|
} vxge_hal_shpc_capability_le_t;
|
|
|
|
typedef struct vxge_hal_shpc_capability_t {
|
|
#if defined(VXGE_OS_HOST_BIG_ENDIAN)
|
|
u8 next_capability_ptr;
|
|
u8 capability_id;
|
|
#else
|
|
u8 capability_id;
|
|
u8 next_capability_ptr;
|
|
#endif
|
|
} vxge_hal_shpc_capability_t;
|
|
|
|
typedef struct vxge_hal_msix_capability_le_t {
|
|
u8 capability_id;
|
|
u8 next_capability_ptr;
|
|
u16 msix_control;
|
|
#define VXGE_HAL_PCI_MSIX_FLAGS_ENABLE 0x8000 /* MSIX Enable */
|
|
#define VXGE_HAL_PCI_MSIX_FLAGS_MASK 0x4000 /* Mask all vectors */
|
|
#define VXGE_HAL_PCI_MSIX_FLAGS_TSIZE 0x001f /* Table Size */
|
|
u32 table_offset;
|
|
#define VXGE_HAL_PCI_MSIX_TABLE_OFFSET 0xFFFFFFF8 /* Table offset mask */
|
|
#define VXGE_HAL_PCI_MSIX_TABLE_BIR 0x00000007 /* Table BIR mask */
|
|
u32 pba_offset;
|
|
#define VXGE_HAL_PCI_MSIX_PBA_OFFSET 0xFFFFFFF8 /* Table offset mask */
|
|
#define VXGE_HAL_PCI_MSIX_PBA_BIR 0x00000007 /* Table BIR mask */
|
|
} vxge_hal_msix_capability_le_t;
|
|
|
|
typedef struct vxge_hal_msix_capability_t {
|
|
#if defined(VXGE_OS_HOST_BIG_ENDIAN)
|
|
u16 msix_control;
|
|
#define VXGE_HAL_PCI_MSIX_FLAGS_ENABLE 0x8000 /* MSIX Enable */
|
|
#define VXGE_HAL_PCI_MSIX_FLAGS_MASK 0x4000 /* Mask all vectors */
|
|
#define VXGE_HAL_PCI_MSIX_FLAGS_TSIZE 0x001f /* Table Size */
|
|
u8 next_capability_ptr;
|
|
u8 capability_id;
|
|
u32 table_offset;
|
|
#define VXGE_HAL_PCI_MSIX_TABLE_OFFSET 0xFFFFFFF8 /* Table offset mask */
|
|
#define VXGE_HAL_PCI_MSIX_TABLE_BIR 0x00000007 /* Table BIR mask */
|
|
u32 pba_offset;
|
|
#define VXGE_HAL_PCI_MSIX_PBA_OFFSET 0xFFFFFFF8 /* Table offset mask */
|
|
#define VXGE_HAL_PCI_MSIX_PBA_BIR 0x00000007 /* Table BIR mask */
|
|
#else
|
|
u8 capability_id;
|
|
u8 next_capability_ptr;
|
|
u16 msix_control;
|
|
#define VXGE_HAL_PCI_MSIX_FLAGS_ENABLE 0x8000 /* MSIX Enable */
|
|
#define VXGE_HAL_PCI_MSIX_FLAGS_MASK 0x4000 /* Mask all vectors */
|
|
#define VXGE_HAL_PCI_MSIX_FLAGS_TSIZE 0x001f /* Table Size */
|
|
u32 table_offset;
|
|
#define VXGE_HAL_PCI_MSIX_TABLE_OFFSET 0xFFFFFFF8 /* Table offset mask */
|
|
#define VXGE_HAL_PCI_MSIX_TABLE_BIR 0x00000007 /* Table BIR mask */
|
|
u32 pba_offset;
|
|
#define VXGE_HAL_PCI_MSIX_PBA_OFFSET 0xFFFFFFF8 /* Table offset mask */
|
|
#define VXGE_HAL_PCI_MSIX_PBA_BIR 0x00000007 /* Table BIR mask */
|
|
#endif
|
|
} vxge_hal_msix_capability_t;
|
|
|
|
typedef struct vxge_hal_pci_caps_offset_t {
|
|
u32 pm_cap_offset;
|
|
u32 vpd_cap_offset;
|
|
u32 sid_cap_offset;
|
|
u32 msi_cap_offset;
|
|
u32 vs_cap_offset;
|
|
u32 shpc_cap_offset;
|
|
u32 msix_cap_offset;
|
|
} vxge_hal_pci_caps_offset_t;
|
|
|
|
typedef struct vxge_hal_pci_e_capability_le_t {
|
|
u8 capability_id;
|
|
u8 next_capability_ptr;
|
|
u16 pci_e_flags;
|
|
#define VXGE_HAL_PCI_EXP_FLAGS_VERS 0x000f /* Capability version */
|
|
#define VXGE_HAL_PCI_EXP_FLAGS_TYPE 0x00f0 /* Device/Port type */
|
|
#define VXGE_HAL_PCI_EXP_TYPE_ENDPOINT 0x0 /* Express Endpoint */
|
|
#define VXGE_HAL_PCI_EXP_TYPE_LEG_END 0x1 /* Legacy Endpoint */
|
|
#define VXGE_HAL_PCI_EXP_TYPE_ROOT_PORT 0x4 /* Root Port */
|
|
#define VXGE_HAL_PCI_EXP_TYPE_UPSTREAM 0x5 /* Upstream Port */
|
|
#define VXGE_HAL_PCI_EXP_TYPE_DOWNSTREAM 0x6 /* Downstream Port */
|
|
#define VXGE_HAL_PCI_EXP_TYPE_PCI_BRIDGE 0x7 /* PCI/PCI-X Bridge */
|
|
#define VXGE_HAL_PCI_EXP_FLAGS_SLOT 0x0100 /* Slot implemented */
|
|
#define VXGE_HAL_PCI_EXP_FLAGS_IRQ 0x3e00 /* Interrupt msg number */
|
|
u32 pci_e_devcap;
|
|
#define VXGE_HAL_PCI_EXP_DEVCAP_PAYLOAD 0x07 /* Max_Payload_Size */
|
|
#define VXGE_HAL_PCI_EXP_DEVCAP_PHANTOM 0x18 /* Phantom functions */
|
|
#define VXGE_HAL_PCI_EXP_DEVCAP_EXT_TAG 0x20 /* Extended tags */
|
|
#define VXGE_HAL_PCI_EXP_DEVCAP_L0S 0x1c0 /* L0s Acceptable Latency */
|
|
#define VXGE_HAL_PCI_EXP_DEVCAP_L1 0xe00 /* L1 Acceptable Latency */
|
|
#define VXGE_HAL_PCI_EXP_DEVCAP_ATN_BUT 0x1000 /* Attention Button Present */
|
|
#define VXGE_HAL_PCI_EXP_DEVCAP_ATN_IND 0x2000 /* Attention Ind Present */
|
|
#define VXGE_HAL_PCI_EXP_DEVCAP_PWR_IND 0x4000 /* Power Indicator Present */
|
|
#define VXGE_HAL_PCI_EXP_DEVCAP_PWR_VAL 0x3fc0000 /* Slot Power Limit Value */
|
|
#define VXGE_HAL_PCI_EXP_DEVCAP_PWR_SCL 0xc000000 /* Slot Power Limit Scale */
|
|
u16 pci_e_devctl;
|
|
#define VXGE_HAL_PCI_EXP_DEVCTL_CERE 0x0001 /* Correctable Err Report En. */
|
|
#define VXGE_HAL_PCI_EXP_DEVCTL_NFERE 0x0002 /* Non-Fatal Err Report En */
|
|
#define VXGE_HAL_PCI_EXP_DEVCTL_FERE 0x0004 /* Fatal Error Report En */
|
|
#define VXGE_HAL_PCI_EXP_DEVCTL_URRE 0x0008 /* Unsupported Req Report En. */
|
|
#define VXGE_HAL_PCI_EXP_DEVCTL_RELAX_EN 0x0010 /* Enable relaxed ordering */
|
|
#define VXGE_HAL_PCI_EXP_DEVCTL_PAYLOAD 0x00e0 /* Max_Payload_Size */
|
|
#define VXGE_HAL_PCI_EXP_DEVCTL_EXT_TAG 0x0100 /* Extended Tag Field Enable */
|
|
#define VXGE_HAL_PCI_EXP_DEVCTL_PHANTOM 0x0200 /* Phantom Functions Enable */
|
|
#define VXGE_HAL_PCI_EXP_DEVCTL_AUX_PME 0x0400 /* Auxiliary Power PM Enable */
|
|
#define VXGE_HAL_PCI_EXP_DEVCTL_NOSNOOP_EN 0x0800 /* Enable No Snoop */
|
|
#define VXGE_HAL_PCI_EXP_DEVCTL_READRQ 0x7000 /* Max_Read_Request_Size */
|
|
u16 pci_e_devsta;
|
|
#define VXGE_HAL_PCI_EXP_DEVSTA_CED 0x01 /* Correctable Error Detected */
|
|
#define VXGE_HAL_PCI_EXP_DEVSTA_NFED 0x02 /* Non-Fatal Error Detected */
|
|
#define VXGE_HAL_PCI_EXP_DEVSTA_FED 0x04 /* Fatal Error Detected */
|
|
#define VXGE_HAL_PCI_EXP_DEVSTA_URD 0x08 /* Unsupported Req Detected */
|
|
#define VXGE_HAL_PCI_EXP_DEVSTA_AUXPD 0x10 /* AUX Power Detected */
|
|
#define VXGE_HAL_PCI_EXP_DEVSTA_TRPND 0x20 /* Transactions Pending */
|
|
u32 pci_e_lnkcap;
|
|
#define VXGE_HAL_PCI_EXP_LNKCAP_LNK_SPEED 0xf /* Supported Link speeds. */
|
|
#define VXGE_HAL_PCI_EXP_LNKCAP_LS_2_5 0x1 /* 2.5 Gb/s supported. */
|
|
#define VXGE_HAL_PCI_EXP_LNKCAP_LS_5 0x2 /* 5 and 2.5 Gb/s supported. */
|
|
#define VXGE_HAL_PCI_EXP_LNKCAP_LNK_WIDTH 0x3f0 /* Supported Link speeds. */
|
|
#define VXGE_HAL_PCI_EXP_LNKCAP_LW_RES 0x0 /* Reserved. */
|
|
#define VXGE_HAL_PCI_EXP_LNKCAP_LW_X1 0x1 /* Reserved. */
|
|
#define VXGE_HAL_PCI_EXP_LNKCAP_LW_X2 0x2 /* Reserved. */
|
|
#define VXGE_HAL_PCI_EXP_LNKCAP_LW_X4 0x4 /* Reserved. */
|
|
#define VXGE_HAL_PCI_EXP_LNKCAP_LW_X8 0x8 /* Reserved. */
|
|
#define VXGE_HAL_PCI_EXP_LNKCAP_LW_X12 0xa /* Reserved. */
|
|
#define VXGE_HAL_PCI_EXP_LNKCAP_LW_X16 0x10 /* Reserved. */
|
|
#define VXGE_HAL_PCI_EXP_LNKCAP_LW_X32 0x20 /* Reserved. */
|
|
#define VXGE_HAL_PCI_EXP_LNKCAP_LNK_ASPM 0xc00 /* Supported Link speeds. */
|
|
#define VXGE_HAL_PCI_EXP_LNKCAP_LASPM_RES1 0x0 /* Reserved. */
|
|
#define VXGE_HAL_PCI_EXP_LNKCAP_LASPM_LO 0x1 /* Reserved. */
|
|
#define VXGE_HAL_PCI_EXP_LNKCAP_LASPM_RES2 0x2 /* Reserved. */
|
|
#define VXGE_HAL_PCI_EXP_LNKCAP_LASPM_L0_L1 0x3 /* Reserved. */
|
|
#define VXGE_HAL_PCI_EXP_LNKCAP_L0_LAT 0x7000 /* Supported Link speeds. */
|
|
#define VXGE_HAL_PCI_EXP_LNKCAP_L0_LT_64 0x0 /* Less than 64ns. */
|
|
#define VXGE_HAL_PCI_EXP_LNKCAP_L0_64_128 0x1 /* 64ns to less than 128ns. */
|
|
#define VXGE_HAL_PCI_EXP_LNKCAP_L0_128_256 0x2 /* 128ns to less than 256ns. */
|
|
#define VXGE_HAL_PCI_EXP_LNKCAP_L0_256_512 0x3 /* 256ns to less than 512ns. */
|
|
#define VXGE_HAL_PCI_EXP_LNKCAP_L0_512_1us 0x4 /* 512ns to less than 1s. */
|
|
#define VXGE_HAL_PCI_EXP_LNKCAP_L0_1us_2us 0x5 /* 1s to less than 2s. */
|
|
#define VXGE_HAL_PCI_EXP_LNKCAP_L0_2us_4us 0x6 /* 2s-4s. */
|
|
#define VXGE_HAL_PCI_EXP_LNKCAP_L0_GT_4us 0x7 /* More than 4s. */
|
|
#define VXGE_HAL_PCI_EXP_LNKCAP_L1_LAT 0x38000 /* Supported Link speeds. */
|
|
#define VXGE_HAL_PCI_EXP_LNKCAP_L1_LT_1us 0x0 /* Less than 1us. */
|
|
#define VXGE_HAL_PCI_EXP_LNKCAP_L1_1us_2us 0x1 /* 1us to less than 2us. */
|
|
#define VXGE_HAL_PCI_EXP_LNKCAP_L1_2us_4us 0x2 /* 2us to less than 4us. */
|
|
#define VXGE_HAL_PCI_EXP_LNKCAP_L1_4us_8us 0x3 /* 4us to less than 8us. */
|
|
#define VXGE_HAL_PCI_EXP_LNKCAP_L1_8us_16us 0x4 /* 8us to less than 16us. */
|
|
#define VXGE_HAL_PCI_EXP_LNKCAP_L1_16us_32us 0x5 /* 16us to less than 32us. */
|
|
#define VXGE_HAL_PCI_EXP_LNKCAP_L1_32us_64us 0x6 /* 32us-64us. */
|
|
#define VXGE_HAL_PCI_EXP_LNKCAP_L1_GT_64us 0x7 /* More than 64us. */
|
|
#define VXGE_HAL_PCI_EXP_LNKCAP_CLK_PWR_MGMT 0x40000 /* Clk power management. */
|
|
#define VXGE_HAL_PCI_EXP_LNKCAP_DOWN_ERR_CAP 0x80000 /* Down error capable. */
|
|
#define VXGE_HAL_PCI_EXP_LNKCAP_LNK_ACT_CAP 0x100000 /* DL active rep cap. */
|
|
#define VXGE_HAL_PCI_EXP_LNKCAP_LNK_BW_CAP 0x200000 /* DL bw reporting cap. */
|
|
#define VXGE_HAL_PCI_EXP_LNKCAP_LNK_PORT_NUM 0xff000000 /* Port number. */
|
|
u16 pci_e_lnkctl;
|
|
#define VXGE_HAL_PCI_EXP_LNKCTL_ASPM 0x3 /* ASPM Control. */
|
|
#define VXGE_HAL_PCI_EXP_LNKCTL_ASPM_DISABLED 0x0 /* Disabled. */
|
|
#define VXGE_HAL_PCI_EXP_LNKCTL_ASPM_L0_EN 0x1 /* L0 entry enabled. */
|
|
#define VXGE_HAL_PCI_EXP_LNKCTL_ASPM_L1_EN 0x2 /* L1 entry enabled. */
|
|
#define VXGE_HAL_PCI_EXP_LNKCTL_ASPM_L0_L1_EN 0x3 /* L0 & L1 entry enabled. */
|
|
#define VXGE_HAL_PCI_EXP_LNKCTL_RCB 0x8 /* Read Completion Boundary. */
|
|
#define VXGE_HAL_PCI_EXP_LNKCTL_RCB_64 0x0 /* RCB 64 bytes. */
|
|
#define VXGE_HAL_PCI_EXP_LNKCTL_RCB_128 0x1 /* RCB 128 bytes. */
|
|
#define VXGE_HAL_PCI_EXP_LNKCTL_DISABLED 0x10 /* Disables the link. */
|
|
#define VXGE_HAL_PCI_EXP_LNKCTL_RETRAIN 0x20 /* Retrain the link. */
|
|
#define VXGE_HAL_PCI_EXP_LNKCTL_CCCFG 0x40 /* Common clock config. */
|
|
#define VXGE_HAL_PCI_EXP_LNKCTL_EXT_SYNC 0x80 /* Extended Sync. */
|
|
#define VXGE_HAL_PCI_EXP_LNKCTL_CLK_PWRMGMT 0x100 /* Enable clk pwr mgmt. */
|
|
#define VXGE_HAL_PCI_EXP_LNKCTL_HW_AUTO_DIS 0x200 /* Hw autonomous with dis */
|
|
#define VXGE_HAL_PCI_EXP_LNKCTL_BWM_INTR_EN 0x400 /* Bw mgt interrupt enable */
|
|
#define VXGE_HAL_PCI_EXP_LNKCTL_ABW_INTR_EN 0x800 /* Autonomous BW intr en */
|
|
u16 pci_e_lnksta;
|
|
#define VXGE_HAL_PCI_EXP_LNKSTA_LNK_SPEED 0xf /* Supported Link speeds. */
|
|
#define VXGE_HAL_PCI_EXP_LNKSTA_LS_2_5 0x1 /* 2.5 Gb/s supported. */
|
|
#define VXGE_HAL_PCI_EXP_LNKSTA_LS_5 0x2 /* 5 2.5 Gb/s supported. */
|
|
#define VXGE_HAL_PCI_EXP_LNKSTA_LNK_WIDTH 0x3f0 /* Supported Link speeds. */
|
|
#define VXGE_HAL_PCI_EXP_LNKSTA_LW_RES 0x0 /* Reserved. */
|
|
#define VXGE_HAL_PCI_EXP_LNKSTA_LW_X1 0x1 /* Reserved. */
|
|
#define VXGE_HAL_PCI_EXP_LNKSTA_LW_X2 0x2 /* Reserved. */
|
|
#define VXGE_HAL_PCI_EXP_LNKSTA_LW_X4 0x4 /* Reserved. */
|
|
#define VXGE_HAL_PCI_EXP_LNKSTA_LW_X8 0x8 /* Reserved. */
|
|
#define VXGE_HAL_PCI_EXP_LNKSTA_LW_X12 0xa /* Reserved. */
|
|
#define VXGE_HAL_PCI_EXP_LNKSTA_LW_X16 0x10 /* Reserved. */
|
|
#define VXGE_HAL_PCI_EXP_LNKSTA_LW_X32 0x20 /* Reserved. */
|
|
#define VXGE_HAL_PCI_EXP_LNKSTA_LNK_TRAIN 0x800 /* Link training. */
|
|
#define VXGE_HAL_PCI_EXP_LNKSTA_SCLK_CFG 0x1000 /* Slot Clock Config. */
|
|
#define VXGE_HAL_PCI_EXP_LNKSTA_DLL_ACTIVE 0x2000 /* Data LL Active. */
|
|
#define VXGE_HAL_PCI_EXP_LNKSTA_BWM_STA 0x4000 /* Bw mgmt intr enable */
|
|
#define VXGE_HAL_PCI_EXP_LNKSTA_ABW_STA 0x8000 /* Autonomous BW intr en */
|
|
u32 pci_e_stlcap;
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#define VXGE_HAL_PCI_EXP_STLCAP_ATTN_BTTN 0x1 /* Attention Button Present */
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#define VXGE_HAL_PCI_EXP_STLCAP_PWR_CTRL 0x2 /* Power Control Present */
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#define VXGE_HAL_PCI_EXP_STLCAP_MRL_SENS 0x4 /* MRL Sesor Present */
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#define VXGE_HAL_PCI_EXP_STLCAP_ATTN_IND 0x8 /* Attention Ind Present */
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#define VXGE_HAL_PCI_EXP_STLCAP_PWR_IND 0x10 /* Power Indicator Present */
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#define VXGE_HAL_PCI_EXP_STLCAP_HP_SURP 0x20 /* Hot-Plug Surprise */
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#define VXGE_HAL_PCI_EXP_STLCAP_HP_CAP 0x40 /* Hot-Plug Surprise */
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#define VXGE_HAL_PCI_EXP_STLCAP_SL_PWR_VAL 0x7F80 /* Hot-Plug Surprise */
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#define VXGE_HAL_PCI_EXP_STLCAP_SL_PWR_250 0xF0 /* 250 W Slot Power Limit */
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#define VXGE_HAL_PCI_EXP_STLCAP_SL_PWR_275 0xF1 /* 275 W Slot Power Limit */
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#define VXGE_HAL_PCI_EXP_STLCAP_SL_PWR_300 0xF2 /* 300 W Slot Power Limit */
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#define VXGE_HAL_PCI_EXP_STLCAP_SL_PWR_LIM 0x18000 /* Hot-Plug Surprise */
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#define VXGE_HAL_PCI_EXP_STLCAP_SL_PWR_1X 0x0 /* 1.0x */
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#define VXGE_HAL_PCI_EXP_STLCAP_SL_PWR_XBY10 0x1 /* 0.1x */
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#define VXGE_HAL_PCI_EXP_STLCAP_SL_PWR_XBY100 0x2 /* 0.01x */
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#define VXGE_HAL_PCI_EXP_STLCAP_SL_PWR_XBY1000 0x3 /* 0.001x */
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#define VXGE_HAL_PCI_EXP_STLCAP_EM_INTR_LOCK 0x20000 /* Ele-mec Intrlock Pres */
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#define VXGE_HAL_PCI_EXP_STLCAP_NO_CMD_CMPL 0x40000 /* No Cmd Compl Support */
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#define VXGE_HAL_PCI_EXP_STLCAP_PHY_SL_NO 0xFFF80000 /* Phys Slot Number */
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u16 pci_e_stlctl;
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#define VXGE_HAL_PCI_EXP_STLCTL_ATTN_BTN_EN 0x1 /* Atten Btn pressed enable */
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#define VXGE_HAL_PCI_EXP_STLCTL_PF_DET_EN 0x2 /* Power Fault Detected En */
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#define VXGE_HAL_PCI_EXP_STLCTL_MRL_SENS_EN 0x4 /* MRL Sensor Changed Enable */
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#define VXGE_HAL_PCI_EXP_STLCTL_PDET_CH_EN 0x8 /* Presence Detect Change En */
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#define VXGE_HAL_PCI_EXP_STLCTL_CC_INTR_EN 0x10 /* Cmd Compl Intr Enable */
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#define VXGE_HAL_PCI_EXP_STLCTL_HP_INTR_EN 0x20 /* Hot-Plug Intr Enable */
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#define VXGE_HAL_PCI_EXP_STLCTL_ATN_IND_CTRL 0xC0 /* Attention Ind Control */
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#define VXGE_HAL_PCI_EXP_STLCTL_ATN_IND_RES 0x0 /* Reserved */
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#define VXGE_HAL_PCI_EXP_STLCTL_ATN_IND_ON 0x1 /* On */
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#define VXGE_HAL_PCI_EXP_STLCTL_ATN_IND_BLNK 0x2 /* Blink */
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#define VXGE_HAL_PCI_EXP_STLCTL_ATN_IND_OFF 0x3 /* Off */
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#define VXGE_HAL_PCI_EXP_STLCTL_PWR_IND_CTRL 0x300 /* POwer Indicator Control */
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#define VXGE_HAL_PCI_EXP_STLCTL_PWR_IND_RES 0x0 /* Reserved */
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#define VXGE_HAL_PCI_EXP_STLCTL_PWR_IND_ON 0x1 /* On */
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#define VXGE_HAL_PCI_EXP_STLCTL_PWR_IND_BLNK 0x2 /* Blink */
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#define VXGE_HAL_PCI_EXP_STLCTL_PWR_IND_OFF 0x3 /* Off */
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#define VXGE_HAL_PCI_EXP_STLCTL_PWRCTRL_CTRL 0x400 /* Power Controller Ctrl */
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#define VXGE_HAL_PCI_EXP_STLCTL_PWRCTRL_on 0x0 /* Power on */
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#define VXGE_HAL_PCI_EXP_STLCTL_PWRCTRL_off 0x1 /* Power off */
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#define VXGE_HAL_PCI_EXP_STLCTL_EM_IL_CTRL 0x800 /* Ele-mec Interlock Crl */
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#define VXGE_HAL_PCI_EXP_STLCTL_DLL_ST_CH_EN 0x1000 /* DL Layer State Ch En */
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u16 pci_e_stlsta;
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#define VXGE_HAL_PCI_EXP_STLSTA_ATTN_BTN 0x1 /* Attention Button Pressed */
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#define VXGE_HAL_PCI_EXP_STLSTA_PF_DET 0x2 /* Power Fault Detected */
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#define VXGE_HAL_PCI_EXP_STLSTA_MRL_SENS_CH 0x4 /* MRL Sensor Changed */
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#define VXGE_HAL_PCI_EXP_STLSTA_PDET_CH 0x8 /* Presence Detect Changed */
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#define VXGE_HAL_PCI_EXP_STLSTA_CMD_COMPL 0x10 /* Command Completed */
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#define VXGE_HAL_PCI_EXP_STLSTA_MRL_SENS_STA 0x20 /* MRL Sensor State */
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#define VXGE_HAL_PCI_EXP_STLSTA_MRL_SENS_CL 0x0 /* MRL Sensor State - closed */
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#define VXGE_HAL_PCI_EXP_STLSTA_MRL_SENS_OP 0x1 /* MRL Sensor State - open */
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#define VXGE_HAL_PCI_EXP_STLSTA_PDET_STA 0x400 /* Presence Detect State */
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#define VXGE_HAL_PCI_EXP_STLSTA_PDET_EMPTY 0x0 /* Clost Empty */
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#define VXGE_HAL_PCI_EXP_STLSTA_PDET_PRESENT 0x1 /* Card Present */
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#define VXGE_HAL_PCI_EXP_STLSTA_EM_IL_STA 0x80 /* Ele-mec Intrlock Control */
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#define VXGE_HAL_PCI_EXP_STLSTA_EM_IL_DIS 0x0 /* Disengaged */
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#define VXGE_HAL_PCI_EXP_STLSTA_EM_IL_EN 0x1 /* Engaged */
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#define VXGE_HAL_PCI_EXP_STLSTA_DLL_ST_CH 0x100 /* DL Layer State Changed */
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u16 pci_e_rtctl;
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#define VXGE_HAL_PCI_EXP_RTCTL_SECEE 0x01 /* Sys Err on Correctable Error */
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#define VXGE_HAL_PCI_EXP_RTCTL_SENFEE 0x02 /* Sys Err on Non-Fatal Error */
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#define VXGE_HAL_PCI_EXP_RTCTL_SEFEE 0x04 /* Sys Err on Fatal Error */
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#define VXGE_HAL_PCI_EXP_RTCTL_PMEIE 0x08 /* PME Interrupt Enable */
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#define VXGE_HAL_PCI_EXP_RTCTL_CRSSVE 0x10 /* CRS SW Visibility Enable */
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u16 pci_e_rtcap;
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#define VXGE_HAL_PCI_EXP_RTCAP_CRS_SW_VIS 0x01 /* CRS SW Visibility */
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u32 pci_e_rtsta;
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#define VXGE_HAL_PCI_EXP_RTSTA_PME_REQ_ID 0xFFFF /* PME Requestor ID */
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#define VXGE_HAL_PCI_EXP_RTSTA_PME_STATUS 0x10000 /* PME status */
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#define VXGE_HAL_PCI_EXP_RTSTA_PME_PENDING 0x20000 /* PME Pending */
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} vxge_hal_pci_e_capability_le_t;
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typedef struct vxge_hal_pci_e_capability_t {
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#if defined(VXGE_OS_HOST_BIG_ENDIAN)
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u16 pci_e_flags;
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#define VXGE_HAL_PCI_EXP_FLAGS_VERS 0x000f /* Capability version */
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#define VXGE_HAL_PCI_EXP_FLAGS_TYPE 0x00f0 /* Device/Port type */
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#define VXGE_HAL_PCI_EXP_TYPE_ENDPOINT 0x0 /* Express Endpoint */
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#define VXGE_HAL_PCI_EXP_TYPE_LEG_END 0x1 /* Legacy Endpoint */
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#define VXGE_HAL_PCI_EXP_TYPE_ROOT_PORT 0x4 /* Root Port */
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#define VXGE_HAL_PCI_EXP_TYPE_UPSTREAM 0x5 /* Upstream Port */
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#define VXGE_HAL_PCI_EXP_TYPE_DOWNSTREAM 0x6 /* Downstream Port */
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#define VXGE_HAL_PCI_EXP_TYPE_PCI_BRIDGE 0x7 /* PCI/PCI-X Bridge */
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#define VXGE_HAL_PCI_EXP_FLAGS_SLOT 0x0100 /* Slot implemented */
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#define VXGE_HAL_PCI_EXP_FLAGS_IRQ 0x3e00 /* Interrupt message number */
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u8 next_capability_ptr;
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u8 capability_id;
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u32 pci_e_devcap;
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#define VXGE_HAL_PCI_EXP_DEVCAP_PAYLOAD 0x07 /* Max_Payload_Size */
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#define VXGE_HAL_PCI_EXP_DEVCAP_PHANTOM 0x18 /* Phantom functions */
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#define VXGE_HAL_PCI_EXP_DEVCAP_EXT_TAG 0x20 /* Extended tags */
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#define VXGE_HAL_PCI_EXP_DEVCAP_L0S 0x1c0 /* L0s Acceptable Latency */
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#define VXGE_HAL_PCI_EXP_DEVCAP_L1 0xe00 /* L1 Acceptable Latency */
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#define VXGE_HAL_PCI_EXP_DEVCAP_ATN_BUT 0x1000 /* Attention Button Present */
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#define VXGE_HAL_PCI_EXP_DEVCAP_ATN_IND 0x2000 /* Attention Ind Present */
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#define VXGE_HAL_PCI_EXP_DEVCAP_PWR_IND 0x4000 /* Power Indicator Present */
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#define VXGE_HAL_PCI_EXP_DEVCAP_PWR_VAL 0x3fc0000 /* Slot Power Limit Value */
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#define VXGE_HAL_PCI_EXP_DEVCAP_PWR_SCL 0xc000000 /* Slot Power Limit Scale */
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u16 pci_e_devsta;
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#define VXGE_HAL_PCI_EXP_DEVSTA_CED 0x01 /* Correctable Err Detected */
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#define VXGE_HAL_PCI_EXP_DEVSTA_NFED 0x02 /* Non-Fatal Error Detected */
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#define VXGE_HAL_PCI_EXP_DEVSTA_FED 0x04 /* Fatal Error Detected */
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#define VXGE_HAL_PCI_EXP_DEVSTA_URD 0x08 /* Unsupported Req Detected */
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#define VXGE_HAL_PCI_EXP_DEVSTA_AUXPD 0x10 /* AUX Power Detected */
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#define VXGE_HAL_PCI_EXP_DEVSTA_TRPND 0x20 /* Transactions Pending */
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u16 pci_e_devctl;
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#define VXGE_HAL_PCI_EXP_DEVCTL_CERE 0x0001 /* Corr'ble Err Reporting En. */
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#define VXGE_HAL_PCI_EXP_DEVCTL_NFERE 0x0002 /* Non-Fatal Err Reporting En */
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#define VXGE_HAL_PCI_EXP_DEVCTL_FERE 0x0004 /* Fatal Error Reporting En */
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#define VXGE_HAL_PCI_EXP_DEVCTL_URRE 0x0008 /* Unsupp Req Reporting En. */
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#define VXGE_HAL_PCI_EXP_DEVCTL_RELAX_EN 0x0010 /* Enable relaxed ordering */
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#define VXGE_HAL_PCI_EXP_DEVCTL_PAYLOAD 0x00e0 /* Max_Payload_Size */
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#define VXGE_HAL_PCI_EXP_DEVCTL_EXT_TAG 0x0100 /* Extended Tag Field Enable */
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#define VXGE_HAL_PCI_EXP_DEVCTL_PHANTOM 0x0200 /* Phantom Functions Enable */
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#define VXGE_HAL_PCI_EXP_DEVCTL_AUX_PME 0x0400 /* Auxiliary Power PM Enable */
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#define VXGE_HAL_PCI_EXP_DEVCTL_NOSNOOP_EN 0x0800 /* Enable No Snoop */
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#define VXGE_HAL_PCI_EXP_DEVCTL_READRQ 0x7000 /* Max_Read_Request_Size */
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u32 pci_e_lnkcap;
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#define VXGE_HAL_PCI_EXP_LNKCAP_LNK_SPEED 0xf /* Supported Link speeds. */
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#define VXGE_HAL_PCI_EXP_LNKCAP_LS_2_5 0x1 /* 2.5 Gb/s supported. */
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#define VXGE_HAL_PCI_EXP_LNKCAP_LS_5 0x2 /* 5 2.5 Gb/s supported. */
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#define VXGE_HAL_PCI_EXP_LNKCAP_LNK_WIDTH 0x3f0 /* Supported Link speeds. */
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#define VXGE_HAL_PCI_EXP_LNKCAP_LW_RES 0x0 /* Reserved. */
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#define VXGE_HAL_PCI_EXP_LNKCAP_LW_X1 0x1 /* Reserved. */
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#define VXGE_HAL_PCI_EXP_LNKCAP_LW_X2 0x2 /* Reserved. */
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#define VXGE_HAL_PCI_EXP_LNKCAP_LW_X4 0x4 /* Reserved. */
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#define VXGE_HAL_PCI_EXP_LNKCAP_LW_X8 0x8 /* Reserved. */
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#define VXGE_HAL_PCI_EXP_LNKCAP_LW_X12 0xa /* Reserved. */
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#define VXGE_HAL_PCI_EXP_LNKCAP_LW_X16 0x10 /* Reserved. */
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#define VXGE_HAL_PCI_EXP_LNKCAP_LW_X32 0x20 /* Reserved. */
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#define VXGE_HAL_PCI_EXP_LNKCAP_LNK_ASPM 0xc00 /* Supported Link speeds. */
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#define VXGE_HAL_PCI_EXP_LNKCAP_LASPM_RES1 0x0 /* Reserved. */
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#define VXGE_HAL_PCI_EXP_LNKCAP_LASPM_LO 0x1 /* Reserved. */
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#define VXGE_HAL_PCI_EXP_LNKCAP_LASPM_RES2 0x2 /* Reserved. */
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#define VXGE_HAL_PCI_EXP_LNKCAP_LASPM_L0_L1 0x3 /* Reserved. */
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#define VXGE_HAL_PCI_EXP_LNKCAP_L0_LAT 0x7000 /* Supported Link speeds. */
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#define VXGE_HAL_PCI_EXP_LNKCAP_L0_LT_64 0x0 /* Less than 64 ns. */
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#define VXGE_HAL_PCI_EXP_LNKCAP_L0_64_128 0x1 /* 64 ns to less than 128 ns. */
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#define VXGE_HAL_PCI_EXP_LNKCAP_L0_128_256 0x2 /* 128 ns to less than 256 ns. */
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#define VXGE_HAL_PCI_EXP_LNKCAP_L0_256_512 0x3 /* 256 ns to less than 512 ns. */
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#define VXGE_HAL_PCI_EXP_LNKCAP_L0_512_1us 0x4 /* 512 ns to less than 1us. */
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#define VXGE_HAL_PCI_EXP_LNKCAP_L0_1us_2us 0x5 /* 1us to less than 2us. */
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#define VXGE_HAL_PCI_EXP_LNKCAP_L0_2us_4us 0x6 /* 2us-4us. */
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#define VXGE_HAL_PCI_EXP_LNKCAP_L0_GT_4us 0x7 /* More than 4us. */
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#define VXGE_HAL_PCI_EXP_LNKCAP_L1_LAT 0x38000 /* Supported Link speeds. */
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#define VXGE_HAL_PCI_EXP_LNKCAP_L1_LT_1us 0x0 /* Less than 1us. */
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#define VXGE_HAL_PCI_EXP_LNKCAP_L1_1us_2us 0x1 /* 1us to less than 2us. */
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#define VXGE_HAL_PCI_EXP_LNKCAP_L1_2us_4us 0x2 /* 2us to less than 4us. */
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#define VXGE_HAL_PCI_EXP_LNKCAP_L1_4us_8us 0x3 /* 4us to less than 8us. */
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#define VXGE_HAL_PCI_EXP_LNKCAP_L1_8us_16us 0x4 /* 8us to less than 16us. */
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#define VXGE_HAL_PCI_EXP_LNKCAP_L1_16us_32us 0x5 /* 16us to less than 32us. */
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#define VXGE_HAL_PCI_EXP_LNKCAP_L1_32us_64us 0x6 /* 32us-64s. */
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#define VXGE_HAL_PCI_EXP_LNKCAP_L1_GT_64us 0x7 /* More than 64us. */
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#define VXGE_HAL_PCI_EXP_LNKCAP_CLK_PWR_MGMT 0x40000 /* Clk power management. */
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#define VXGE_HAL_PCI_EXP_LNKCAP_DOWN_ERR_CAP 0x80000 /* Down error capable. */
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#define VXGE_HAL_PCI_EXP_LNKCAP_LNK_ACT_CAP 0x100000 /* DL active rep cap. */
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#define VXGE_HAL_PCI_EXP_LNKCAP_LNK_BW_CAP 0x200000 /* DL bw rep cap. */
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#define VXGE_HAL_PCI_EXP_LNKCAP_LNK_PORT_NUM 0xff000000 /* Port number. */
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u16 pci_e_lnksta;
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#define VXGE_HAL_PCI_EXP_LNKSTA_LNK_SPEED 0xf /* Supported Link speeds. */
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#define VXGE_HAL_PCI_EXP_LNKSTA_LS_2_5 0x1 /* 2.5 Gb/s supported. */
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#define VXGE_HAL_PCI_EXP_LNKSTA_LS_5 0x2 /* 5 2.5 Gb/s supported. */
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#define VXGE_HAL_PCI_EXP_LNKSTA_LNK_WIDTH 0x3f0 /* Supported Link speeds. */
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#define VXGE_HAL_PCI_EXP_LNKSTA_LW_RES 0x0 /* Reserved. */
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#define VXGE_HAL_PCI_EXP_LNKSTA_LW_X1 0x1 /* Reserved. */
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#define VXGE_HAL_PCI_EXP_LNKSTA_LW_X2 0x2 /* Reserved. */
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#define VXGE_HAL_PCI_EXP_LNKSTA_LW_X4 0x4 /* Reserved. */
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#define VXGE_HAL_PCI_EXP_LNKSTA_LW_X8 0x8 /* Reserved. */
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#define VXGE_HAL_PCI_EXP_LNKSTA_LW_X12 0xa /* Reserved. */
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#define VXGE_HAL_PCI_EXP_LNKSTA_LW_X16 0x10 /* Reserved. */
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#define VXGE_HAL_PCI_EXP_LNKSTA_LW_X32 0x20 /* Reserved. */
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#define VXGE_HAL_PCI_EXP_LNKSTA_LNK_TRAIN 0x800 /* Link training. */
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#define VXGE_HAL_PCI_EXP_LNKSTA_SCLK_CFG 0x1000 /* Slot Clock Config. */
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#define VXGE_HAL_PCI_EXP_LNKSTA_DLL_ACTIVE 0x2000 /* Data LL Active. */
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#define VXGE_HAL_PCI_EXP_LNKSTA_BWM_STA 0x4000 /* Bw mgmt interrupt enable */
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#define VXGE_HAL_PCI_EXP_LNKSTA_ABW_STA 0x8000 /* Autonomous BW intr en */
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u16 pci_e_lnkctl;
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#define VXGE_HAL_PCI_EXP_LNKCTL_ASPM 0x3 /* ASPM Control. */
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#define VXGE_HAL_PCI_EXP_LNKCTL_ASPM_DISABLED 0x0 /* Disabled. */
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#define VXGE_HAL_PCI_EXP_LNKCTL_ASPM_L0_EN 0x1 /* L0 entry enabled. */
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#define VXGE_HAL_PCI_EXP_LNKCTL_ASPM_L1_EN 0x2 /* L1 entry enabled. */
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#define VXGE_HAL_PCI_EXP_LNKCTL_ASPM_L0_L1_EN 0x3 /* L0 & L1 entry enabled. */
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#define VXGE_HAL_PCI_EXP_LNKCTL_RCB 0x8 /* Read Compl Boundary. */
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#define VXGE_HAL_PCI_EXP_LNKCTL_RCB_64 0x0 /* RCB 64 bytes. */
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#define VXGE_HAL_PCI_EXP_LNKCTL_RCB_128 0x1 /* RCB 128 bytes. */
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#define VXGE_HAL_PCI_EXP_LNKCTL_DISABLED 0x10 /* Disables the link. */
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#define VXGE_HAL_PCI_EXP_LNKCTL_RETRAIN 0x20 /* Retrain the link. */
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#define VXGE_HAL_PCI_EXP_LNKCTL_CCCFG 0x40 /* Common clock config. */
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#define VXGE_HAL_PCI_EXP_LNKCTL_EXT_SYNC 0x80 /* Extended Sync. */
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#define VXGE_HAL_PCI_EXP_LNKCTL_CLK_PWRMGMT 0x100 /* Enable clk pwr mgmt. */
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#define VXGE_HAL_PCI_EXP_LNKCTL_HW_AUTO_DIS 0x200 /* Hw autonomous w/dis */
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#define VXGE_HAL_PCI_EXP_LNKCTL_BWM_INTR_EN 0x400 /* Bw mgmt intr enable */
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#define VXGE_HAL_PCI_EXP_LNKCTL_ABW_INTR_EN 0x800 /* Autonomous BW int en */
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u32 pci_e_stlcap;
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#define VXGE_HAL_PCI_EXP_STLCAP_ATTN_BTTN 0x1 /* Attention Button Present */
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#define VXGE_HAL_PCI_EXP_STLCAP_PWR_CTRL 0x2 /* Power Control Present */
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#define VXGE_HAL_PCI_EXP_STLCAP_MRL_SENS 0x4 /* MRL Sesor Present */
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#define VXGE_HAL_PCI_EXP_STLCAP_ATTN_IND 0x8 /* Attention Ind Present */
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#define VXGE_HAL_PCI_EXP_STLCAP_PWR_IND 0x10 /* Power Indicator Present */
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#define VXGE_HAL_PCI_EXP_STLCAP_HP_SURP 0x20 /* Hot-Plug Surprise */
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#define VXGE_HAL_PCI_EXP_STLCAP_HP_CAP 0x40 /* Hot-Plug Surprise */
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#define VXGE_HAL_PCI_EXP_STLCAP_SL_PWR_VAL 0x7F80 /* Hot-Plug Surprise */
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#define VXGE_HAL_PCI_EXP_STLCAP_SL_PWR_250 0xF0 /* 250 W Slot Power Limit */
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#define VXGE_HAL_PCI_EXP_STLCAP_SL_PWR_275 0xF1 /* 275 W Slot Power Limit */
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#define VXGE_HAL_PCI_EXP_STLCAP_SL_PWR_300 0xF2 /* 300 W Slot Power Limit */
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#define VXGE_HAL_PCI_EXP_STLCAP_SL_PWR_LIM 0x18000 /* Hot-Plug Surprise */
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#define VXGE_HAL_PCI_EXP_STLCAP_SL_PWR_1X 0x0 /* 1.0x */
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#define VXGE_HAL_PCI_EXP_STLCAP_SL_PWR_XBY10 0x1 /* 0.1x */
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#define VXGE_HAL_PCI_EXP_STLCAP_SL_PWR_XBY100 0x2 /* 0.01x */
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#define VXGE_HAL_PCI_EXP_STLCAP_SL_PWR_XBY1000 0x3 /* 0.001x */
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#define VXGE_HAL_PCI_EXP_STLCAP_EM_INTR_LOCK 0x20000 /* Ele-mec Intrlock Pres */
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#define VXGE_HAL_PCI_EXP_STLCAP_NO_CMD_CMPL 0x40000 /* No Command Compl Supp */
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#define VXGE_HAL_PCI_EXP_STLCAP_PHY_SL_NO 0xFFF80000 /* Phy Slot Number */
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u16 pci_e_stlsta;
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#define VXGE_HAL_PCI_EXP_STLSTA_ATTN_BTN 0x1 /* Attention Button Pressed */
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#define VXGE_HAL_PCI_EXP_STLSTA_PF_DET 0x2 /* Power Fault Detected */
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#define VXGE_HAL_PCI_EXP_STLSTA_MRL_SENS_CH 0x4 /* MRL Sensor Changed */
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#define VXGE_HAL_PCI_EXP_STLSTA_PDET_CH 0x8 /* Presence Detect Changed */
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#define VXGE_HAL_PCI_EXP_STLSTA_CMD_COMPL 0x10 /* Command Completed */
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#define VXGE_HAL_PCI_EXP_STLSTA_MRL_SENS_STA 0x20 /* MRL Sensor State */
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#define VXGE_HAL_PCI_EXP_STLSTA_MRL_SENS_CL 0x0 /* MRL Sensor State - closed */
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#define VXGE_HAL_PCI_EXP_STLSTA_MRL_SENS_OP 0x1 /* MRL Sensor State - open */
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#define VXGE_HAL_PCI_EXP_STLSTA_PDET_STA 0x400 /* Presence Detect State */
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#define VXGE_HAL_PCI_EXP_STLSTA_PDET_EMPTY 0x0 /* Clost Empty */
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#define VXGE_HAL_PCI_EXP_STLSTA_PDET_PRESENT 0x1 /* Card Present */
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#define VXGE_HAL_PCI_EXP_STLSTA_EM_IL_STA 0x80 /* Ele-mec Intrlock Ctrl */
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#define VXGE_HAL_PCI_EXP_STLSTA_EM_IL_DIS 0x0 /* Disengaged */
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#define VXGE_HAL_PCI_EXP_STLSTA_EM_IL_EN 0x1 /* Engaged */
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#define VXGE_HAL_PCI_EXP_STLSTA_DLL_ST_CH 0x100 /* DL State Changed */
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u16 pci_e_stlctl;
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#define VXGE_HAL_PCI_EXP_STLCTL_ATTN_BTN_EN 0x1 /* Atten Btn pressed en */
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#define VXGE_HAL_PCI_EXP_STLCTL_PF_DET_EN 0x2 /* Pwr Fault Detected En */
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#define VXGE_HAL_PCI_EXP_STLCTL_MRL_SENS_EN 0x4 /* MRL Sensor Changed En */
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#define VXGE_HAL_PCI_EXP_STLCTL_PDET_CH_EN 0x8 /* Presence Detect Changed En */
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#define VXGE_HAL_PCI_EXP_STLCTL_CC_INTR_EN 0x10 /* Cmmd Completed Intr En */
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#define VXGE_HAL_PCI_EXP_STLCTL_HP_INTR_EN 0x20 /* Hot-Plug Intr Enable */
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#define VXGE_HAL_PCI_EXP_STLCTL_ATN_IND_CTRL 0xC0 /* Attention Ind Ctrl */
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#define VXGE_HAL_PCI_EXP_STLCTL_ATN_IND_RES 0x0 /* Reserved */
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#define VXGE_HAL_PCI_EXP_STLCTL_ATN_IND_ON 0x1 /* On */
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#define VXGE_HAL_PCI_EXP_STLCTL_ATN_IND_BLNK 0x2 /* Blink */
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#define VXGE_HAL_PCI_EXP_STLCTL_ATN_IND_OFF 0x3 /* Off */
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#define VXGE_HAL_PCI_EXP_STLCTL_PWR_IND_CTRL 0x300 /* POwer Ind Control */
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#define VXGE_HAL_PCI_EXP_STLCTL_PWR_IND_RES 0x0 /* Reserved */
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#define VXGE_HAL_PCI_EXP_STLCTL_PWR_IND_ON 0x1 /* On */
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#define VXGE_HAL_PCI_EXP_STLCTL_PWR_IND_BLNK 0x2 /* Blink */
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#define VXGE_HAL_PCI_EXP_STLCTL_PWR_IND_OFF 0x3 /* Off */
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#define VXGE_HAL_PCI_EXP_STLCTL_PWRCTRL_CTRL 0x400 /* Power Controller Ctrl */
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#define VXGE_HAL_PCI_EXP_STLCTL_PWRCTRL_on 0x0 /* Power on */
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#define VXGE_HAL_PCI_EXP_STLCTL_PWRCTRL_off 0x1 /* Power off */
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#define VXGE_HAL_PCI_EXP_STLCTL_EM_IL_CTRL 0x800 /* Ele-mec Intrlock Ctrl */
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#define VXGE_HAL_PCI_EXP_STLCTL_DLL_ST_CH_EN 0x1000 /* DL State Changed En */
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u16 pci_e_rtcap;
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#define VXGE_HAL_PCI_EXP_RTCAP_CRS_SW_VIS 0x01 /* CRS Software Visibility */
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u16 pci_e_rtctl;
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#define VXGE_HAL_PCI_EXP_RTCTL_SECEE 0x01 /* Sys Err on Correctable Error */
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#define VXGE_HAL_PCI_EXP_RTCTL_SENFEE 0x02 /* Sys Err on Non-Fatal Error */
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#define VXGE_HAL_PCI_EXP_RTCTL_SEFEE 0x04 /* Sys Err on Fatal Error */
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#define VXGE_HAL_PCI_EXP_RTCTL_PMEIE 0x08 /* PME Intr Enable */
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#define VXGE_HAL_PCI_EXP_RTCTL_CRSSVE 0x10 /* CRS SW Visibility Enable */
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u32 pci_e_rtsta;
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#define VXGE_HAL_PCI_EXP_RTSTA_PME_REQ_ID 0xFFFF /* PME Requestor ID */
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#define VXGE_HAL_PCI_EXP_RTSTA_PME_STATUS 0x10000 /* PME status */
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#define VXGE_HAL_PCI_EXP_RTSTA_PME_PENDING 0x20000 /* PME Pending */
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#else
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u8 capability_id;
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u8 next_capability_ptr;
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u16 pci_e_flags;
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#define VXGE_HAL_PCI_EXP_FLAGS_VERS 0x000f /* Capability version */
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#define VXGE_HAL_PCI_EXP_FLAGS_TYPE 0x00f0 /* Device/Port type */
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#define VXGE_HAL_PCI_EXP_TYPE_ENDPOINT 0x0 /* Express Endpoint */
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#define VXGE_HAL_PCI_EXP_TYPE_LEG_END 0x1 /* Legacy Endpoint */
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#define VXGE_HAL_PCI_EXP_TYPE_ROOT_PORT 0x4 /* Root Port */
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#define VXGE_HAL_PCI_EXP_TYPE_UPSTREAM 0x5 /* Upstream Port */
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#define VXGE_HAL_PCI_EXP_TYPE_DOWNSTREAM 0x6 /* Downstream Port */
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#define VXGE_HAL_PCI_EXP_TYPE_PCI_BRIDGE 0x7 /* PCI/PCI-X Bridge */
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#define VXGE_HAL_PCI_EXP_FLAGS_SLOT 0x0100 /* Slot implemented */
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#define VXGE_HAL_PCI_EXP_FLAGS_IRQ 0x3e00 /* Interrupt message number */
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u32 pci_e_devcap;
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#define VXGE_HAL_PCI_EXP_DEVCAP_PAYLOAD 0x07 /* Max_Payload_Size */
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#define VXGE_HAL_PCI_EXP_DEVCAP_PHANTOM 0x18 /* Phantom functions */
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#define VXGE_HAL_PCI_EXP_DEVCAP_EXT_TAG 0x20 /* Extended tags */
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#define VXGE_HAL_PCI_EXP_DEVCAP_L0S 0x1c0 /* L0s Acceptable Latency */
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#define VXGE_HAL_PCI_EXP_DEVCAP_L1 0xe00 /* L1 Acceptable Latency */
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#define VXGE_HAL_PCI_EXP_DEVCAP_ATN_BUT 0x1000 /* Attention Button Present */
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#define VXGE_HAL_PCI_EXP_DEVCAP_ATN_IND 0x2000 /* Attention Ind Present */
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#define VXGE_HAL_PCI_EXP_DEVCAP_PWR_IND 0x4000 /* Power Indicator Present */
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#define VXGE_HAL_PCI_EXP_DEVCAP_PWR_VAL 0x3fc0000 /* Slot Power Limit Value */
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#define VXGE_HAL_PCI_EXP_DEVCAP_PWR_SCL 0xc000000 /* Slot Power Limit Scale */
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u16 pci_e_devctl;
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#define VXGE_HAL_PCI_EXP_DEVCTL_CERE 0x0001 /* Corr'ble Err Reporting En. */
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#define VXGE_HAL_PCI_EXP_DEVCTL_NFERE 0x0002 /* Non-Fatal Err Reporting En */
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#define VXGE_HAL_PCI_EXP_DEVCTL_FERE 0x0004 /* Fatal Err Reporting En */
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#define VXGE_HAL_PCI_EXP_DEVCTL_URRE 0x0008 /* Unsupp Req Reporting En. */
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#define VXGE_HAL_PCI_EXP_DEVCTL_RELAX_EN 0x0010 /* Enable relaxed ordering */
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#define VXGE_HAL_PCI_EXP_DEVCTL_PAYLOAD 0x00e0 /* Max_Payload_Size */
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#define VXGE_HAL_PCI_EXP_DEVCTL_EXT_TAG 0x0100 /* Extended Tag Field Enable */
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#define VXGE_HAL_PCI_EXP_DEVCTL_PHANTOM 0x0200 /* Phantom Functions Enable */
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#define VXGE_HAL_PCI_EXP_DEVCTL_AUX_PME 0x0400 /* Auxiliary Power PM Enable */
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#define VXGE_HAL_PCI_EXP_DEVCTL_NOSNOOP_EN 0x0800 /* Enable No Snoop */
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#define VXGE_HAL_PCI_EXP_DEVCTL_READRQ 0x7000 /* Max_Read_Request_Size */
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u16 pci_e_devsta;
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#define VXGE_HAL_PCI_EXP_DEVSTA_CED 0x01 /* Correctable Error Detected */
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#define VXGE_HAL_PCI_EXP_DEVSTA_NFED 0x02 /* Non-Fatal Error Detected */
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#define VXGE_HAL_PCI_EXP_DEVSTA_FED 0x04 /* Fatal Error Detected */
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#define VXGE_HAL_PCI_EXP_DEVSTA_URD 0x08 /* Unsupp Request Detected */
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#define VXGE_HAL_PCI_EXP_DEVSTA_AUXPD 0x10 /* AUX Power Detected */
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#define VXGE_HAL_PCI_EXP_DEVSTA_TRPND 0x20 /* Transactions Pending */
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u32 pci_e_lnkcap;
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#define VXGE_HAL_PCI_EXP_LNKCAP_LNK_SPEED 0xf /* Supported Link speeds. */
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#define VXGE_HAL_PCI_EXP_LNKCAP_LS_2_5 0x1 /* 2.5 Gb/s supported. */
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#define VXGE_HAL_PCI_EXP_LNKCAP_LS_5 0x2 /* 5 and 2.5 Gb/s supported. */
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#define VXGE_HAL_PCI_EXP_LNKCAP_LNK_WIDTH 0x3f0 /* Supported Link speeds. */
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#define VXGE_HAL_PCI_EXP_LNKCAP_LW_RES 0x0 /* Reserved. */
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#define VXGE_HAL_PCI_EXP_LNKCAP_LW_X1 0x1 /* Reserved. */
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#define VXGE_HAL_PCI_EXP_LNKCAP_LW_X2 0x2 /* Reserved. */
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#define VXGE_HAL_PCI_EXP_LNKCAP_LW_X4 0x4 /* Reserved. */
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#define VXGE_HAL_PCI_EXP_LNKCAP_LW_X8 0x8 /* Reserved. */
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#define VXGE_HAL_PCI_EXP_LNKCAP_LW_X12 0xa /* Reserved. */
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#define VXGE_HAL_PCI_EXP_LNKCAP_LW_X16 0x10 /* Reserved. */
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#define VXGE_HAL_PCI_EXP_LNKCAP_LW_X32 0x20 /* Reserved. */
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#define VXGE_HAL_PCI_EXP_LNKCAP_LNK_ASPM 0xc00 /* Supported Link speeds. */
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#define VXGE_HAL_PCI_EXP_LNKCAP_LASPM_RES1 0x0 /* Reserved. */
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#define VXGE_HAL_PCI_EXP_LNKCAP_LASPM_LO 0x1 /* Reserved. */
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#define VXGE_HAL_PCI_EXP_LNKCAP_LASPM_RES2 0x2 /* Reserved. */
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#define VXGE_HAL_PCI_EXP_LNKCAP_LASPM_L0_L1 0x3 /* Reserved. */
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#define VXGE_HAL_PCI_EXP_LNKCAP_L0_LAT 0x7000 /* Supported Link speeds. */
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#define VXGE_HAL_PCI_EXP_LNKCAP_L0_LT_64 0x0 /* Less than 64 ns. */
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#define VXGE_HAL_PCI_EXP_LNKCAP_L0_64_128 0x1 /* 64ns to less than 128ns. */
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#define VXGE_HAL_PCI_EXP_LNKCAP_L0_128_256 0x2 /* 128ns to less than 256ns. */
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#define VXGE_HAL_PCI_EXP_LNKCAP_L0_256_512 0x3 /* 256ns to less than 512ns. */
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#define VXGE_HAL_PCI_EXP_LNKCAP_L0_512_1us 0x4 /* 512ns to less than 1us. */
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#define VXGE_HAL_PCI_EXP_LNKCAP_L0_1us_2us 0x5 /* 1us to less than 2us. */
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#define VXGE_HAL_PCI_EXP_LNKCAP_L0_2us_4us 0x6 /* 2us-4us. */
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#define VXGE_HAL_PCI_EXP_LNKCAP_L0_GT_4us 0x7 /* More than 4us. */
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#define VXGE_HAL_PCI_EXP_LNKCAP_L1_LAT 0x38000 /* Supported Link speeds. */
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#define VXGE_HAL_PCI_EXP_LNKCAP_L1_LT_1us 0x0 /* Less than 1us. */
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#define VXGE_HAL_PCI_EXP_LNKCAP_L1_1us_2us 0x1 /* 1us to less than 2us. */
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#define VXGE_HAL_PCI_EXP_LNKCAP_L1_2us_4us 0x2 /* 2us to less than 4us. */
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#define VXGE_HAL_PCI_EXP_LNKCAP_L1_4us_8us 0x3 /* 4us to less than 8us. */
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#define VXGE_HAL_PCI_EXP_LNKCAP_L1_8us_16us 0x4 /* 8us to less than 16us. */
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#define VXGE_HAL_PCI_EXP_LNKCAP_L1_16us_32us 0x5 /* 16us to less than 32us. */
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#define VXGE_HAL_PCI_EXP_LNKCAP_L1_32us_64us 0x6 /* 32us-64us. */
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#define VXGE_HAL_PCI_EXP_LNKCAP_L1_GT_64us 0x7 /* More than 64us. */
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#define VXGE_HAL_PCI_EXP_LNKCAP_CLK_PWR_MGMT 0x40000 /* Clock power mgmt */
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#define VXGE_HAL_PCI_EXP_LNKCAP_DOWN_ERR_CAP 0x80000 /* Down error capable. */
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#define VXGE_HAL_PCI_EXP_LNKCAP_LNK_ACT_CAP 0x100000 /* DL active rep cap. */
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#define VXGE_HAL_PCI_EXP_LNKCAP_LNK_BW_CAP 0x200000 /* DL bw rep cap. */
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#define VXGE_HAL_PCI_EXP_LNKCAP_LNK_PORT_NUM 0xff000000 /* Port number. */
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u16 pci_e_lnkctl;
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#define VXGE_HAL_PCI_EXP_LNKCTL_ASPM 0x3 /* ASPM Control. */
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#define VXGE_HAL_PCI_EXP_LNKCTL_ASPM_DISABLED 0x0 /* Disabled. */
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#define VXGE_HAL_PCI_EXP_LNKCTL_ASPM_L0_EN 0x1 /* L0 entry enabled. */
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#define VXGE_HAL_PCI_EXP_LNKCTL_ASPM_L1_EN 0x2 /* L1 entry enabled. */
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#define VXGE_HAL_PCI_EXP_LNKCTL_ASPM_L0_L1_EN 0x3 /* L0 & L1 entry enabled. */
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#define VXGE_HAL_PCI_EXP_LNKCTL_RCB 0x8 /* Read Completion Boundary. */
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#define VXGE_HAL_PCI_EXP_LNKCTL_RCB_64 0x0 /* RCB 64 bytes. */
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#define VXGE_HAL_PCI_EXP_LNKCTL_RCB_128 0x1 /* RCB 128 bytes. */
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#define VXGE_HAL_PCI_EXP_LNKCTL_DISABLED 0x10 /* Disables the link. */
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#define VXGE_HAL_PCI_EXP_LNKCTL_RETRAIN 0x20 /* Retrain the link. */
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#define VXGE_HAL_PCI_EXP_LNKCTL_CCCFG 0x40 /* Common clock config. */
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#define VXGE_HAL_PCI_EXP_LNKCTL_EXT_SYNC 0x80 /* Extended Sync. */
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#define VXGE_HAL_PCI_EXP_LNKCTL_CLK_PWRMGMT 0x100 /* Enable clock power mgmt */
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#define VXGE_HAL_PCI_EXP_LNKCTL_HW_AUTO_DIS 0x200 /* HW autonomous with dis */
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#define VXGE_HAL_PCI_EXP_LNKCTL_BWM_INTR_EN 0x400 /* Bw mgmt interrupt enable */
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#define VXGE_HAL_PCI_EXP_LNKCTL_ABW_INTR_EN 0x800 /* Autonomous BW int enable */
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u16 pci_e_lnksta;
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#define VXGE_HAL_PCI_EXP_LNKSTA_LNK_SPEED 0xf /* Supported Link speeds. */
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#define VXGE_HAL_PCI_EXP_LNKSTA_LS_2_5 0x1 /* 2.5 Gb/s supported. */
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#define VXGE_HAL_PCI_EXP_LNKSTA_LS_5 0x2 /* 5 and 2.5 Gb/s supported */
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/* Supported Link speeds. */
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#define VXGE_HAL_PCI_EXP_LNKSTA_LNK_WIDTH 0x3f0
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#define VXGE_HAL_PCI_EXP_LNKSTA_LW_RES 0x0 /* Reserved. */
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#define VXGE_HAL_PCI_EXP_LNKSTA_LW_X1 0x1 /* Reserved. */
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#define VXGE_HAL_PCI_EXP_LNKSTA_LW_X2 0x2 /* Reserved. */
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#define VXGE_HAL_PCI_EXP_LNKSTA_LW_X4 0x4 /* Reserved. */
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#define VXGE_HAL_PCI_EXP_LNKSTA_LW_X8 0x8 /* Reserved. */
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#define VXGE_HAL_PCI_EXP_LNKSTA_LW_X12 0xa /* Reserved. */
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#define VXGE_HAL_PCI_EXP_LNKSTA_LW_X16 0x10 /* Reserved. */
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#define VXGE_HAL_PCI_EXP_LNKSTA_LW_X32 0x20 /* Reserved. */
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#define VXGE_HAL_PCI_EXP_LNKSTA_LNK_TRAIN 0x800 /* Link training. */
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#define VXGE_HAL_PCI_EXP_LNKSTA_SCLK_CFG 0x1000 /* Slot Clock Config. */
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#define VXGE_HAL_PCI_EXP_LNKSTA_DLL_ACTIVE 0x2000 /* Data LL Active. */
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#define VXGE_HAL_PCI_EXP_LNKSTA_BWM_STA 0x4000 /* Bw mgmt intr enable */
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#define VXGE_HAL_PCI_EXP_LNKSTA_ABW_STA 0x8000 /* Autonomous BW intr en */
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u32 pci_e_stlcap;
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#define VXGE_HAL_PCI_EXP_STLCAP_ATTN_BTTN 0x1 /* Attention Button Present */
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#define VXGE_HAL_PCI_EXP_STLCAP_PWR_CTRL 0x2 /* Power Control Present */
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#define VXGE_HAL_PCI_EXP_STLCAP_MRL_SENS 0x4 /* MRL Sesor Present */
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#define VXGE_HAL_PCI_EXP_STLCAP_ATTN_IND 0x8 /* Attention Ind Present */
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/* Power Indicator Present */
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#define VXGE_HAL_PCI_EXP_STLCAP_PWR_IND 0x10
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#define VXGE_HAL_PCI_EXP_STLCAP_HP_SURP 0x20 /* Hot-Plug Surprise */
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#define VXGE_HAL_PCI_EXP_STLCAP_HP_CAP 0x40 /* Hot-Plug Surprise */
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#define VXGE_HAL_PCI_EXP_STLCAP_SL_PWR_VAL 0x7F80 /* Hot-Plug Surprise */
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/* 250 W Slot Power Limit */
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#define VXGE_HAL_PCI_EXP_STLCAP_SL_PWR_250 0xF0
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/* 275 W Slot Power Limit */
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#define VXGE_HAL_PCI_EXP_STLCAP_SL_PWR_275 0xF1
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/* 300 W Slot Power Limit */
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#define VXGE_HAL_PCI_EXP_STLCAP_SL_PWR_300 0xF2
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#define VXGE_HAL_PCI_EXP_STLCAP_SL_PWR_LIM 0x18000 /* Hot-Plug Surprise */
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#define VXGE_HAL_PCI_EXP_STLCAP_SL_PWR_1X 0x0 /* 1.0x */
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#define VXGE_HAL_PCI_EXP_STLCAP_SL_PWR_XBY10 0x1 /* 0.1x */
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#define VXGE_HAL_PCI_EXP_STLCAP_SL_PWR_XBY100 0x2 /* 0.01x */
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#define VXGE_HAL_PCI_EXP_STLCAP_SL_PWR_XBY1000 0x3 /* 0.001x */
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#define VXGE_HAL_PCI_EXP_STLCAP_EM_INTR_LOCK 0x20000 /* Ele-mec Intrlock Pres */
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#define VXGE_HAL_PCI_EXP_STLCAP_NO_CMD_CMPL 0x40000 /* No Cmd Completed Supp */
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#define VXGE_HAL_PCI_EXP_STLCAP_PHY_SL_NO 0xFFF80000 /* Phys Slot Number */
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u16 pci_e_stlctl;
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#define VXGE_HAL_PCI_EXP_STLCTL_ATTN_BTN_EN 0x1 /* Atten Bttn pressed en */
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#define VXGE_HAL_PCI_EXP_STLCTL_PF_DET_EN 0x2 /* Power Fault Detected En */
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#define VXGE_HAL_PCI_EXP_STLCTL_MRL_SENS_EN 0x4 /* MRL Sensor Changed Enable */
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#define VXGE_HAL_PCI_EXP_STLCTL_PDET_CH_EN 0x8 /* Presence Detect Changed En */
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#define VXGE_HAL_PCI_EXP_STLCTL_CC_INTR_EN 0x10 /* Cmd Compl Intr Enable */
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#define VXGE_HAL_PCI_EXP_STLCTL_HP_INTR_EN 0x20 /* Hot-Plug Intr Enable */
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#define VXGE_HAL_PCI_EXP_STLCTL_ATN_IND_CTRL 0xC0 /* Atten Ind Control */
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#define VXGE_HAL_PCI_EXP_STLCTL_ATN_IND_RES 0x0 /* Reserved */
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#define VXGE_HAL_PCI_EXP_STLCTL_ATN_IND_ON 0x1 /* On */
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#define VXGE_HAL_PCI_EXP_STLCTL_ATN_IND_BLNK 0x2 /* Blink */
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#define VXGE_HAL_PCI_EXP_STLCTL_ATN_IND_OFF 0x3 /* Off */
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#define VXGE_HAL_PCI_EXP_STLCTL_PWR_IND_CTRL 0x300 /* Power Ind Control */
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#define VXGE_HAL_PCI_EXP_STLCTL_PWR_IND_RES 0x0 /* Reserved */
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#define VXGE_HAL_PCI_EXP_STLCTL_PWR_IND_ON 0x1 /* On */
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#define VXGE_HAL_PCI_EXP_STLCTL_PWR_IND_BLNK 0x2 /* Blink */
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#define VXGE_HAL_PCI_EXP_STLCTL_PWR_IND_OFF 0x3 /* Off */
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#define VXGE_HAL_PCI_EXP_STLCTL_PWRCTRL_CTRL 0x400 /* Power Controller Ctrl */
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#define VXGE_HAL_PCI_EXP_STLCTL_PWRCTRL_on 0x0 /* Power on */
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#define VXGE_HAL_PCI_EXP_STLCTL_PWRCTRL_off 0x1 /* Power off */
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#define VXGE_HAL_PCI_EXP_STLCTL_EM_IL_CTRL 0x800 /* Ele-mec Intrlock Ctrl */
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#define VXGE_HAL_PCI_EXP_STLCTL_DLL_ST_CH_EN 0x1000 /* DL State Changed En */
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u16 pci_e_stlsta;
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#define VXGE_HAL_PCI_EXP_STLSTA_ATTN_BTN 0x1 /* Attention Button Pressed */
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#define VXGE_HAL_PCI_EXP_STLSTA_PF_DET 0x2 /* Power Fault Detected */
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#define VXGE_HAL_PCI_EXP_STLSTA_MRL_SENS_CH 0x4 /* MRL Sensor Changed */
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#define VXGE_HAL_PCI_EXP_STLSTA_PDET_CH 0x8 /* Presence Detect Changed */
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#define VXGE_HAL_PCI_EXP_STLSTA_CMD_COMPL 0x10 /* Command Completed */
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#define VXGE_HAL_PCI_EXP_STLSTA_MRL_SENS_STA 0x20 /* MRL Sensor State */
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#define VXGE_HAL_PCI_EXP_STLSTA_MRL_SENS_CL 0x0 /* MRL Sensor State - closed */
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#define VXGE_HAL_PCI_EXP_STLSTA_MRL_SENS_OP 0x1 /* MRL Sensor State - open */
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#define VXGE_HAL_PCI_EXP_STLSTA_PDET_STA 0x400 /* Presence Detect State */
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#define VXGE_HAL_PCI_EXP_STLSTA_PDET_EMPTY 0x0 /* Clost Empty */
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#define VXGE_HAL_PCI_EXP_STLSTA_PDET_PRESENT 0x1 /* Card Present */
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/* Ele-mec Interlock Control */
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|
#define VXGE_HAL_PCI_EXP_STLSTA_EM_IL_STA 0x80
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#define VXGE_HAL_PCI_EXP_STLSTA_EM_IL_DIS 0x0 /* Disengaged */
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#define VXGE_HAL_PCI_EXP_STLSTA_EM_IL_EN 0x1 /* Engaged */
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/* DL Layer State Changed */
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|
#define VXGE_HAL_PCI_EXP_STLSTA_DLL_ST_CH 0x100
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u16 pci_e_rtctl;
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#define VXGE_HAL_PCI_EXP_RTCTL_SECEE 0x01 /* Sys Err on Correctable Error */
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#define VXGE_HAL_PCI_EXP_RTCTL_SENFEE 0x02 /* Sys Err on Non-Fatal Error */
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#define VXGE_HAL_PCI_EXP_RTCTL_SEFEE 0x04 /* Sys Err on Fatal Error */
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#define VXGE_HAL_PCI_EXP_RTCTL_PMEIE 0x08 /* PME Interrupt Enable */
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#define VXGE_HAL_PCI_EXP_RTCTL_CRSSVE 0x10 /* CRS SW Visibility Enable */
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u16 pci_e_rtcap;
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#define VXGE_HAL_PCI_EXP_RTCAP_CRS_SW_VIS 0x01 /* CRS SW Visibility */
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u32 pci_e_rtsta;
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#define VXGE_HAL_PCI_EXP_RTSTA_PME_REQ_ID 0xFFFF /* PME Requestor ID */
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#define VXGE_HAL_PCI_EXP_RTSTA_PME_STATUS 0x10000 /* PME status */
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#define VXGE_HAL_PCI_EXP_RTSTA_PME_PENDING 0x20000 /* PME Pending */
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#endif
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} vxge_hal_pci_e_capability_t;
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typedef u32 vxge_hal_pci_e_caps_offset_t;
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#define VXGE_HAL_PCI_EXT_CAP_ID(header) (header & 0x0000ffff)
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#define VXGE_HAL_PCI_EXT_CAP_VER(header) ((header >> 16) & 0xf)
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#define VXGE_HAL_PCI_EXT_CAP_NEXT(header) ((header >> 20) & 0xffc)
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#define VXGE_HAL_PCI_EXT_CAP_ID_ERR 1
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#define VXGE_HAL_PCI_EXT_CAP_ID_VC 2
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#define VXGE_HAL_PCI_EXT_CAP_ID_DSN 3
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#define VXGE_HAL_PCI_EXT_CAP_ID_PWR 4
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typedef struct vxge_hal_err_capability_t {
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u32 pci_err_header;
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u32 pci_err_uncor_status;
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#define VXGE_HAL_PCI_ERR_UNC_TRAIN 0x00000001 /* Training */
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#define VXGE_HAL_PCI_ERR_UNC_DLP 0x00000010 /* Data Link Protocol */
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#define VXGE_HAL_PCI_ERR_UNC_POISON_TLP 0x00001000 /* Poisoned TLP */
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#define VXGE_HAL_PCI_ERR_UNC_FCP 0x00002000 /* Flow Control Protocol */
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#define VXGE_HAL_PCI_ERR_UNC_COMP_TIME 0x00004000 /* Completion Timeout */
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#define VXGE_HAL_PCI_ERR_UNC_COMP_ABORT 0x00008000 /* Completer Abort */
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#define VXGE_HAL_PCI_ERR_UNC_UNX_COMP 0x00010000 /* Unexpected Completion */
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#define VXGE_HAL_PCI_ERR_UNC_RX_OVER 0x00020000 /* Receiver Overflow */
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#define VXGE_HAL_PCI_ERR_UNC_MALF_TLP 0x00040000 /* Malformed TLP */
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#define VXGE_HAL_PCI_ERR_UNC_ECRC 0x00080000 /* ECRC Error Status */
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#define VXGE_HAL_PCI_ERR_UNC_UNSUP 0x00100000 /* Unsupported Request */
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u32 pci_err_uncor_mask;
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u32 pci_err_uncor_server;
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u32 pci_err_cor_status;
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#define VXGE_HAL_PCI_ERR_COR_RCVR 0x00000001 /* Receiver Error Status */
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#define VXGE_HAL_PCI_ERR_COR_BAD_TLP 0x00000040 /* Bad TLP Status */
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#define VXGE_HAL_PCI_ERR_COR_BAD_DLLP 0x00000080 /* Bad DLLP Status */
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#define VXGE_HAL_PCI_ERR_COR_REP_ROLL 0x00000100 /* REPLAY_NUM Rollover */
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#define VXGE_HAL_PCI_ERR_COR_REP_TIMER 0x00001000 /* Replay Timer Timeout */
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#define VXGE_HAL_PCI_ERR_COR_MASK 20 /* Correctable Error Mask */
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u32 pci_err_cap;
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#define VXGE_HAL_PCI_ERR_CAP_FEP(x) ((x) & 31) /* First Error Pointer */
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/* ECRC Generation Capable */
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#define VXGE_HAL_PCI_ERR_CAP_ECRC_GENC 0x00000020
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#define VXGE_HAL_PCI_ERR_CAP_ECRC_GENE 0x00000040 /* ECRC Generation Enable */
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#define VXGE_HAL_PCI_ERR_CAP_ECRC_CHKC 0x00000080 /* ECRC Check Capable */
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#define VXGE_HAL_PCI_ERR_CAP_ECRC_CHKE 0x00000100 /* ECRC Check Enable */
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u32 err_header_log;
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#define VXGE_HAL_PCI_ERR_HEADER_LOG(x) ((x) >> 31) /* Error Header Log */
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u32 unused2[3];
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u32 pci_err_root_command;
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u32 pci_err_root_status;
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u32 pci_err_root_cor_src;
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u32 pci_err_root_src;
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} vxge_hal_err_capability_t;
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typedef struct vxge_hal_vc_capability_t {
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u32 pci_vc_header;
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u32 pci_vc_port_reg1;
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u32 pci_vc_port_reg2;
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u32 pci_vc_port_ctrl;
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u32 pci_vc_port_status;
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u32 pci_vc_res_cap;
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u32 pci_vc_res_ctrl;
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u32 pci_vc_res_status;
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} vxge_hal_vc_capability_t;
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typedef struct vxge_hal_pwr_budget_capability_t {
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u32 pci_pwr_header;
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u32 pci_pwr_dsr;
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u32 pci_pwr_data;
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#define VXGE_HAL_PCI_PWR_DATA_BASE(x) ((x) & 0xff) /* Base Power */
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#define VXGE_HAL_PCI_PWR_DATA_SCALE(x) (((x) >> 8) & 3) /* Data Scale */
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#define VXGE_HAL_PCI_PWR_DATA_PM_SUB(x) (((x) >> 10) & 7) /* PM Sub State */
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#define VXGE_HAL_PCI_PWR_DATA_PM_STATE(x) (((x) >> 13) & 3) /* PM State */
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#define VXGE_HAL_PCI_PWR_DATA_TYPE(x) (((x) >> 15) & 7) /* Type */
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#define VXGE_HAL_PCI_PWR_DATA_RAIL(x) (((x) >> 18) & 7) /* Power Rail */
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u32 pci_pwr_cap;
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#define VXGE_HAL_PCI_PWR_CAP_BUDGET(x) ((x) & 1) /* Include in sys budget */
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} vxge_hal_pwr_budget_capability_t;
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typedef struct vxge_hal_pci_e_ext_caps_offset_t {
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u32 err_cap_offset;
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u32 vc_cap_offset;
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u32 dsn_cap_offset;
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u32 pwr_budget_cap_offset;
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} vxge_hal_pci_e_ext_caps_offset_t;
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#pragma pack()
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__EXTERN_END_DECLS
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#endif /* VXGE_HAL_REGS_H */
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