Marcel Moolenaar 7faf44ba96 o The P1020(E) & P2020(E) also have two cores. This conditional has ... a tendency to grow unwieldy so we may want to revisit this in due time. o Simplify the CPU reset function by writing to the reset control register irrespective of whether the CPU has one and automatically falling back to the debug control register if we didn't reset the CPU. The side-effect is that we now properly reset future processors without first having to add the system version to the list.		2011-05-27 23:18:41 +00:00
..
aim	Add a missing isync.	2011-05-26 14:34:22 +00:00
booke	o The P1020(E) & P2020(E) also have two cores. This conditional has	2011-05-27 23:18:41 +00:00
compile
conf	SMP has worked perfectly for a very long time on 32-bit PowerPC on both	2011-05-06 20:43:02 +00:00
cpufreq	Remove unused variables. Spotted by a cppcheck	2011-01-06 20:19:01 +00:00
fpu	The NetBSD Foundation has granted permission to remove clause 3 and 4 from	2010-03-03 17:07:02 +00:00
include	o Swap the SVR numbers for MPC8533 & MPC8533E	2011-05-27 05:58:10 +00:00
mambo	Fix the interrupt code, broken 7 months ago. The interrupt framework	2011-01-29 20:58:38 +00:00
mpc85xx	Retire isa_setup_intr() and isa_teardown_intr() and use the generic bus	2011-05-06 13:48:53 +00:00
ofw	Fix whitespace nit.	2011-03-09 15:03:42 +00:00
powermac	Do not use Open Firmware to open the device and instead program its start	2011-05-06 03:26:24 +00:00
powerpc	Fix a </<= mixup. This could result in suboptimal performance on the last	2011-05-16 15:20:54 +00:00
ps3	Add RTC support for the LV1 clock on the PS3. The hypervisor won't let us	2011-05-24 02:19:45 +00:00
psim	Fix the interrupt code, broken 7 months ago. The interrupt framework	2011-01-29 20:58:38 +00:00