188 lines
7.5 KiB
C
188 lines
7.5 KiB
C
#ifndef IF_RDPREG_H
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#define IF_RDPREG_H 1
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/*
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* Copyright (c) 1998 Joerg Wunsch
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*
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE DEVELOPERS ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE DEVELOPERS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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/*
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* Part of the definitions here has been copied over from the REDP
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* packet driver's REDPPD.INC file. This provides us with the same
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* set of acronyms as the packet driver is using.
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*
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* The packet driver had no copyright, and is believed to be in the
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* public domain. The author seems to be someone who calls himself
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* "Chiu", so that's the only acknowledgment i can give here.
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* Supposedly the author was someone from RealTek.
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*/
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/*
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* We're hanging upon an LPT port, thus suck in the lpt defs as well.
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*/
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#include <i386/isa/lptreg.h>
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struct rdphdr {
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/* RTL8002 header that is prepended to the actual packet */
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u_char unused2[2];
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u_short pktlen;
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u_char status; /* copy of RSR for this packet */
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u_char unused3[3];
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};
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/*
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*
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* 8 Data Modes are provided:
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*
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* +--------+---------------+-------------+
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* | Mode | Read | Write |
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* +--------+---------------+-------------+
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* | 0 | LptCtrl | LptData |
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* +--------+---------------+-------------+
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* | 1 | LptCtrl | LptCtrl |
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* +--------+---------------+-------------+
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* | 2 | LptCtrl*2 | LptData |
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* +--------+---------------+-------------+
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* | 3 | LptCtrl*2 | LptCtrl |
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* +--------+---------------+-------------+
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* | 4 | LptData | LptData |
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* +--------+---------------+-------------+
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* | 5 | LptData | LptCtrl |
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* +--------+---------------+-------------+
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* | 6 | LptData*2 | LptData |
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* +--------+---------------+-------------+
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* | 7 | LptData*2 | LptCtrl |
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* +--------+---------------+-------------+
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*
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* Right now, this driver only implements mode 0 (which ought to work
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* on any standard parallel interface).
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*
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*/
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/*
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* Page 0 of EPLC registers
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*/
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#define IDR0 0x00 /* Ethernet ID register (R/W) */
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#define IDR1 0x01
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#define IDR2 0x02
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#define IDR3 0x03
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#define IDR4 0x04
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#define IDR5 0x05
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#define TBCR0 0x06 /* transmit byte count (W), 11 bits valid */
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#define TBCR1 0x07
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#define TSR 0x08 /* transmit status (R), cleared upon next tx */
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# define TSR_TOK 1 /* transmit OK */
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# define TSR_TABT 2 /* transmit aborted (excessive collisions) */
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# define TSR_COL 4 /* collision detected */
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# define TSR_CDH 8 /* CD heartbeat detected */
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#define RSR 0x09 /*
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* receiver status (R), cleared upon next
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* received packet (but stored in rx buffer
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* header anyway)
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*/
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# define RSR_ROK 1 /* receive OK */
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# define RSR_CRC 2 /* CRC error */
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# define RSR_FA 4 /* frame alignment error (not multiple of 8) */
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# define RSR_BUFO 0x10 /* rx buffer overflow, packet discarded */
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# define RSR_PUN 0x20 /* packet count underflow (jump command issued
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* but rx buffer was empty) */
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# define RSR_POV 0x40 /* packet count overflow (more than 254 (?)
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* packets still in buffer) */
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#define ISR 0x0A /* interrupt status register (R), writing
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* clears the written bits */
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# define ISR_TOK 1 /* transmission OK (~ TSR_TOK) */
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# define ISR_TER 2 /* transmitter error (~ TSR_TABT) */
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# define ISR_ROK 4 /* receive OK (~ RSR_ROK) */
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# define ISR_RER 8 /* receiver error (~ RSR_CRC|RSR_FA) */
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# define ISR_RBER 0x10 /* rx buffer overflow (POV|PUN|BUFO) */
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#define IMR 0x0B /* interrupt mask register (R/W), bit as ISR */
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#define CMR1 0x0C /* command register 1 (R/W) */
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# define CMR1_BUFE 1 /* (R) rx buffer empty */
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# define CMR1_IRQ 2 /* (R) interrupt request */
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# define CMR1_TRA 4 /* (R) transmission in progress */
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/* (W) transmit start */
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# define CMR1_TE 0x10 /* (R/W) transmitter enable */
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# define CMR1_RE 0x20 /* (R/W) receiver enable */
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# define CMR1_RST 0x40 /* (R/W) reset; sticks until reset completed */
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# define CMR1_RDPAC 1 /* (W) `rx jump packet', prepare for reading
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* next packet from ring buffer */
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# define CMR1_WRPAC 2 /* (W) `tx jump packet', packet in tx buffer
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* is complete and can be sent */
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# define CMR1_RETX 8 /* (W) retransmit (must be accomp'ed by TRA) */
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# define CMR1_MUX 0x80 /* (W) RTL8012: tell the printer MUX to
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* connect the output pins to the host */
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#define CMR2 0x0D /* command register 2 (R/W) */
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# define CMR2_IRQOUT 1 /* interrupt signal output enabled */
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# define CMR2_RAMTST 2 /* enable RAM test */
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# define CMR2_PAGE 4 /* select register page #1 */
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# define CMR2_IRQINV 8 /* make active IRQ `low' */
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# define CMR2_AMbits 0x30 /* address mode bits: */
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# define CMR2_AM_NONE 0x00 /* 0: accept nothing */
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# define CMR2_AM_PHYS 0x10 /* 1: only physical addr */
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# define CMR2_AM_PB 0x20 /* 2: phys + broadcast */
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# define CMR2_AM_ALL 0x30 /* 3: promiscuous */
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# define CMR2_LBK 0x40 /* enable loopback */
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# define CMR2_SER 0x80 /* save error packet */
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#define MAR 0x0E /* memory access register (?), used for
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* remote DMA to the 8002's buffer */
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#define PNR TBCR0 /* received packet number (R) */
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#define COLR TBCR1 /* collision count (R) (4 bit valid) */
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/*
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* Page 1 of EPLC registers -- EEPROM control
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*/
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#define PCMR TBCR0 /* port command register */
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/* bits for 93C46 control -- add HNib */
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#define PCMR_SK 0x04 /* serial clock for EEPROM */
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#define PCMR_CS 0x02 /* chip select for EEPROM */
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#define PCMR_DO 0x01 /* DI to EEPROM */
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/* EEPROM data, nibbles for 74S288, bits for 93C46 */
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#define PDR TBCR1 /* DO from EEPROM, only bit 0 valid for
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* serial EEPROM */
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/*
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* The following definitionss define remote DMA command through LptCtrl
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*/
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#define ATFD 3 /* ATFD bit in Lpt's Control register */
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/* -> ATFD bit is added for Xircom's MUX */
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#define Ctrl_LNibRead (0x08+ATFD) /* specify low nibble */
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#define Ctrl_HNibRead (0+ATFD) /* specify high nibble */
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#define Ctrl_SelData (0x04+ATFD) /* not through LptCtrl but through */
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/* LptData */
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#define Ctrl_IRQEN 0x10 /* set IRQEN of lpt control register */
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/* Here define constants to construct the required read/write commands */
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#define WrAddr 0x40 /* set address of EPLC write register */
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#define RdAddr 0x0C0 /* set address of EPLC read register */
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#define EOR 0x20 /* ORed to make 'end of read',set CSB=1 */
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#define EOW 0x0E0 /* end of write, R/WB=A/DB=CSB=1 */
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#define EOC 0x0E0 /* End Of r/w Command, R/WB=A/DB=CSB=1 */
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#define HNib 0x10
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#define MkHi(value) (((value) >> 4) | HNib)
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#endif /* IF_RDPREG_H */
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