81c1993f87
- vector.s <- stub called by i386/exception.s - icu_vector.s <- UP - apic_vector.s <- SMP Split icu.s into UP and SMP specific files: - ipl.s <- stub called by i386/exception.s (formerly icu.s) - icu_ipl.s <- UP - apic_ipl.s <- SMP This was done in preparation for massive changes to the SMP INTerrupt mechanisms. More fine tuning, such as merging ipl.s into exception.s, may be appropriate.
250 lines
7.4 KiB
ArmAsm
250 lines
7.4 KiB
ArmAsm
/*
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* from: vector.s, 386BSD 0.1 unknown origin
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* $Id: icu_vector.s,v 1.2 1997/05/24 17:05:26 smp Exp smp $
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*/
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/*
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* modified for PC98 by Kakefuda
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*/
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#ifdef PC98
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#define ICU_IMR_OFFSET 2 /* IO_ICU{1,2} + 2 */
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#else
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#define ICU_IMR_OFFSET 1 /* IO_ICU{1,2} + 1 */
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#endif
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#define ICU_EOI 0x20 /* XXX - define elsewhere */
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#define IRQ_BIT(irq_num) (1 << ((irq_num) % 8))
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#define IRQ_BYTE(irq_num) ((irq_num) / 8)
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#ifdef AUTO_EOI_1
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#define ENABLE_ICU1 /* use auto-EOI to reduce i/o */
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#define OUTB_ICU1
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#else
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#define ENABLE_ICU1 \
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movb $ICU_EOI,%al ; /* as soon as possible send EOI ... */ \
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OUTB_ICU1 /* ... to clear in service bit */
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#define OUTB_ICU1 \
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outb %al,$IO_ICU1
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#endif
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#ifdef AUTO_EOI_2
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/*
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* The data sheet says no auto-EOI on slave, but it sometimes works.
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*/
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#define ENABLE_ICU1_AND_2 ENABLE_ICU1
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#else
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#define ENABLE_ICU1_AND_2 \
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movb $ICU_EOI,%al ; /* as above */ \
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outb %al,$IO_ICU2 ; /* but do second icu first ... */ \
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OUTB_ICU1 /* ... then first icu (if !AUTO_EOI_1) */
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#endif
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/*
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* Macros for interrupt interrupt entry, call to handler, and exit.
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*/
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#define FAST_INTR(irq_num, vec_name, enable_icus) \
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.text ; \
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SUPERALIGN_TEXT ; \
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IDTVEC(vec_name) ; \
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pushl %eax ; /* save only call-used registers */ \
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pushl %ecx ; \
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pushl %edx ; \
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pushl %ds ; \
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MAYBE_PUSHL_ES ; \
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movl $KDSEL,%eax ; \
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movl %ax,%ds ; \
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MAYBE_MOVW_AX_ES ; \
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FAKE_MCOUNT((4+ACTUALLY_PUSHED)*4(%esp)) ; \
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GET_MPLOCK ; /* SMP Spin lock */ \
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pushl _intr_unit + (irq_num) * 4 ; \
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call *_intr_handler + (irq_num) * 4 ; /* do the work ASAP */ \
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enable_icus ; /* (re)enable ASAP (helps edge trigger?) */ \
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addl $4,%esp ; \
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incl _cnt+V_INTR ; /* book-keeping can wait */ \
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movl _intr_countp + (irq_num) * 4,%eax ; \
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incl (%eax) ; \
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movl _cpl,%eax ; /* are we unmasking pending HWIs or SWIs? */ \
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notl %eax ; \
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andl _ipending,%eax ; \
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jne 2f ; /* yes, maybe handle them */ \
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1: ; \
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MEXITCOUNT ; \
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REL_MPLOCK ; /* SMP release global lock */ \
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MAYBE_POPL_ES ; \
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popl %ds ; \
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popl %edx ; \
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popl %ecx ; \
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popl %eax ; \
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iret ; \
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; \
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ALIGN_TEXT ; \
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2: ; \
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cmpb $3,_intr_nesting_level ; /* is there enough stack? */ \
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jae 1b ; /* no, return */ \
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movl _cpl,%eax ; \
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/* XXX next line is probably unnecessary now. */ \
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movl $HWI_MASK|SWI_MASK,_cpl ; /* limit nesting ... */ \
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incb _intr_nesting_level ; /* ... really limit it ... */ \
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sti ; /* ... to do this as early as possible */ \
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MAYBE_POPL_ES ; /* discard most of thin frame ... */ \
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popl %ecx ; /* ... original %ds ... */ \
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popl %edx ; \
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xchgl %eax,4(%esp) ; /* orig %eax; save cpl */ \
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pushal ; /* build fat frame (grrr) ... */ \
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pushl %ecx ; /* ... actually %ds ... */ \
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pushl %es ; \
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movl $KDSEL,%eax ; \
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movl %ax,%es ; \
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movl (2+8+0)*4(%esp),%ecx ; /* ... %ecx from thin frame ... */ \
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movl %ecx,(2+6)*4(%esp) ; /* ... to fat frame ... */ \
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movl (2+8+1)*4(%esp),%eax ; /* ... cpl from thin frame */ \
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pushl %eax ; \
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subl $4,%esp ; /* junk for unit number */ \
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MEXITCOUNT ; \
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jmp _doreti
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#define INTR(irq_num, vec_name, icu, enable_icus, reg) \
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.text ; \
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SUPERALIGN_TEXT ; \
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IDTVEC(vec_name) ; \
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pushl $0 ; /* dummy error code */ \
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pushl $0 ; /* dummy trap type */ \
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pushal ; \
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pushl %ds ; /* save our data and extra segments ... */ \
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pushl %es ; \
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movl $KDSEL,%eax ; /* ... and reload with kernel's own ... */ \
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movl %ax,%ds ; /* ... early for obsolete reasons */ \
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movl %ax,%es ; \
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GET_MPLOCK ; /* SMP Spin lock */ \
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movb _imen + IRQ_BYTE(irq_num),%al ; \
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orb $IRQ_BIT(irq_num),%al ; \
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movb %al,_imen + IRQ_BYTE(irq_num) ; \
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outb %al,$icu+ICU_IMR_OFFSET ; \
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enable_icus ; \
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movl _cpl,%eax ; \
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testb $IRQ_BIT(irq_num),%reg ; \
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jne 2f ; \
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incb _intr_nesting_level ; \
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__CONCAT(Xresume,irq_num): ; \
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FAKE_MCOUNT(12*4(%esp)) ; /* XXX late to avoid double count */ \
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incl _cnt+V_INTR ; /* tally interrupts */ \
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movl _intr_countp + (irq_num) * 4,%eax ; \
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incl (%eax) ; \
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movl _cpl,%eax ; \
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pushl %eax ; \
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pushl _intr_unit + (irq_num) * 4 ; \
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orl _intr_mask + (irq_num) * 4,%eax ; \
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movl %eax,_cpl ; \
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sti ; \
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call *_intr_handler + (irq_num) * 4 ; \
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cli ; /* must unmask _imen and icu atomically */ \
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movb _imen + IRQ_BYTE(irq_num),%al ; \
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andb $~IRQ_BIT(irq_num),%al ; \
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movb %al,_imen + IRQ_BYTE(irq_num) ; \
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outb %al,$icu+ICU_IMR_OFFSET ; \
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sti ; /* XXX _doreti repeats the cli/sti */ \
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MEXITCOUNT ; \
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/* We could usually avoid the following jmp by inlining some of */ \
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/* _doreti, but it's probably better to use less cache. */ \
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jmp _doreti ; \
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; \
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ALIGN_TEXT ; \
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2: ; \
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/* XXX skip mcounting here to avoid double count */ \
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orb $IRQ_BIT(irq_num),_ipending + IRQ_BYTE(irq_num) ; \
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REL_MPLOCK ; /* SMP release global lock */ \
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popl %es ; \
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popl %ds ; \
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popal ; \
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addl $4+4,%esp ; \
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iret
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MCOUNT_LABEL(bintr)
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FAST_INTR(0,fastintr0, ENABLE_ICU1)
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FAST_INTR(1,fastintr1, ENABLE_ICU1)
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FAST_INTR(2,fastintr2, ENABLE_ICU1)
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FAST_INTR(3,fastintr3, ENABLE_ICU1)
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FAST_INTR(4,fastintr4, ENABLE_ICU1)
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FAST_INTR(5,fastintr5, ENABLE_ICU1)
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FAST_INTR(6,fastintr6, ENABLE_ICU1)
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FAST_INTR(7,fastintr7, ENABLE_ICU1)
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FAST_INTR(8,fastintr8, ENABLE_ICU1_AND_2)
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FAST_INTR(9,fastintr9, ENABLE_ICU1_AND_2)
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FAST_INTR(10,fastintr10, ENABLE_ICU1_AND_2)
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FAST_INTR(11,fastintr11, ENABLE_ICU1_AND_2)
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FAST_INTR(12,fastintr12, ENABLE_ICU1_AND_2)
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FAST_INTR(13,fastintr13, ENABLE_ICU1_AND_2)
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FAST_INTR(14,fastintr14, ENABLE_ICU1_AND_2)
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FAST_INTR(15,fastintr15, ENABLE_ICU1_AND_2)
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INTR(0,intr0, IO_ICU1, ENABLE_ICU1, al)
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INTR(1,intr1, IO_ICU1, ENABLE_ICU1, al)
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INTR(2,intr2, IO_ICU1, ENABLE_ICU1, al)
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INTR(3,intr3, IO_ICU1, ENABLE_ICU1, al)
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INTR(4,intr4, IO_ICU1, ENABLE_ICU1, al)
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INTR(5,intr5, IO_ICU1, ENABLE_ICU1, al)
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INTR(6,intr6, IO_ICU1, ENABLE_ICU1, al)
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INTR(7,intr7, IO_ICU1, ENABLE_ICU1, al)
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INTR(8,intr8, IO_ICU2, ENABLE_ICU1_AND_2, ah)
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INTR(9,intr9, IO_ICU2, ENABLE_ICU1_AND_2, ah)
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INTR(10,intr10, IO_ICU2, ENABLE_ICU1_AND_2, ah)
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INTR(11,intr11, IO_ICU2, ENABLE_ICU1_AND_2, ah)
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INTR(12,intr12, IO_ICU2, ENABLE_ICU1_AND_2, ah)
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INTR(13,intr13, IO_ICU2, ENABLE_ICU1_AND_2, ah)
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INTR(14,intr14, IO_ICU2, ENABLE_ICU1_AND_2, ah)
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INTR(15,intr15, IO_ICU2, ENABLE_ICU1_AND_2, ah)
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MCOUNT_LABEL(eintr)
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.data
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ihandlers: /* addresses of interrupt handlers */
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/* actually resumption addresses for HWI's */
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.long Xresume0, Xresume1, Xresume2, Xresume3
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.long Xresume4, Xresume5, Xresume6, Xresume7
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.long Xresume8, Xresume9, Xresume10, Xresume11
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.long Xresume12, Xresume13, Xresume14, Xresume15
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.long 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
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.long swi_tty, swi_net, _softclock, swi_ast
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imasks: /* masks for interrupt handlers */
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.space NHWI*4 /* padding; HWI masks are elsewhere */
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.long 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
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.long SWI_TTY_MASK, SWI_NET_MASK, SWI_CLOCK_MASK, SWI_AST_MASK
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/*
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* Interrupt counters and names. The format of these and the label names
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* must agree with what vmstat expects. The tables are indexed by device
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* ids so that we don't have to move the names around as devices are
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* attached.
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*/
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#include "vector.h"
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.globl _intrcnt, _eintrcnt
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_intrcnt:
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.space (NR_DEVICES + ICU_LEN) * 4
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_eintrcnt:
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.globl _intrnames, _eintrnames
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_intrnames:
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.ascii DEVICE_NAMES
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.asciz "stray irq0"
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.asciz "stray irq1"
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.asciz "stray irq2"
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.asciz "stray irq3"
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.asciz "stray irq4"
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.asciz "stray irq5"
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.asciz "stray irq6"
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.asciz "stray irq7"
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.asciz "stray irq8"
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.asciz "stray irq9"
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.asciz "stray irq10"
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.asciz "stray irq11"
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.asciz "stray irq12"
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.asciz "stray irq13"
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.asciz "stray irq14"
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.asciz "stray irq15"
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_eintrnames:
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.text
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