276 lines
6.0 KiB
Plaintext
276 lines
6.0 KiB
Plaintext
/*
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* Device Tree file for Marvell Armada 385 Access Point Development board
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* (DB-88F6820-AP)
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*
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* Copyright (C) 2014 Marvell
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*
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* Nadav Haklai <nadavh@marvell.com>
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*
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* This file is dual-licensed: you can use it either under the terms
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* of the GPL or the X11 license, at your option. Note that this dual
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* licensing only applies to this file, and not this project as a
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* whole.
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*
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* a) This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without
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* any warranty of any kind, whether express or implied.
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*
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* Or, alternatively,
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*
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* b) Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use,
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* copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* $FreeBSD$
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*/
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/dts-v1/;
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#include "armada-385.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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/ {
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model = "Marvell Armada 385 Access Point Development Board";
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compatible = "marvell,a385-db-ap", "marvell,armada385", "marvell,armada380";
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chosen {
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stdout-path = "serial1";
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};
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memory {
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device_type = "memory";
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reg = <0x00000000 0x80000000>; /* 2GB */
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};
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soc {
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ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
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MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
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MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
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MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000
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MBUS_ID(0x0c, 0x04) 0 0xf1200000 0x100000>;
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internal-regs {
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i2c0: i2c@11000 {
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pinctrl-names = "default";
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pinctrl-0 = <&i2c0_pins>;
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status = "okay";
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/*
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* This bus is wired to two EEPROM
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* sockets, one of which holding the
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* board ID used by the bootloader.
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* Erasing this EEPROM's content will
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* brick the board.
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* Use this bus with caution.
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*/
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};
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mdio@72004 {
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pinctrl-names = "default";
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pinctrl-0 = <&mdio_pins>;
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phy0: ethernet-phy@1 {
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reg = <1>;
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};
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phy1: ethernet-phy@4 {
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reg = <4>;
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};
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phy2: ethernet-phy@6 {
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reg = <6>;
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};
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};
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/* UART0 is exposed through the JP8 connector */
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uart0: serial@12000 {
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pinctrl-names = "default";
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pinctrl-0 = <&uart0_pins>;
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status = "okay";
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};
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/*
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* UART1 is exposed through a FTDI chip
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* wired to the mini-USB connector
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*/
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uart1: serial@12100 {
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pinctrl-names = "default";
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pinctrl-0 = <&uart1_pins>;
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status = "okay";
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};
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pinctrl@18000 {
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xhci0_vbus_pins: xhci0-vbus-pins {
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marvell,pins = "mpp44";
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marvell,function = "gpio";
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};
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};
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/* CON3 */
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ethernet@30000 {
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status = "okay";
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phy = <&phy2>;
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phy-mode = "sgmii";
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buffer-manager = <&bm>;
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bm,pool-long = <1>;
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bm,pool-short = <3>;
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};
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/* CON2 */
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ethernet@34000 {
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status = "okay";
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phy = <&phy1>;
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phy-mode = "sgmii";
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buffer-manager = <&bm>;
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bm,pool-long = <2>;
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bm,pool-short = <3>;
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};
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usb@58000 {
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status = "okay";
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};
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/* CON4 */
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ethernet@70000 {
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pinctrl-names = "default";
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/*
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* The Reference Clock 0 is used to
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* provide a clock to the PHY
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*/
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pinctrl-0 = <&ge0_rgmii_pins>, <&ref_clk0_pins>;
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status = "okay";
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phy = <&phy0>;
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phy-mode = "rgmii-id";
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buffer-manager = <&bm>;
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bm,pool-long = <0>;
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bm,pool-short = <3>;
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};
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crypto@90000 {
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status = "okay";
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};
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crypto@92000 {
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status = "okay";
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};
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bm@c8000 {
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status = "okay";
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};
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nfc: flash@d0000 {
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status = "okay";
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num-cs = <1>;
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nand-ecc-strength = <4>;
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nand-ecc-step-size = <512>;
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marvell,nand-keep-config;
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marvell,nand-enable-arbiter;
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nand-on-flash-bbt;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "U-Boot";
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reg = <0x00000000 0x00800000>;
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read-only;
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};
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partition@800000 {
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label = "uImage";
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reg = <0x00800000 0x00400000>;
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read-only;
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};
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partition@c00000 {
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label = "Root";
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reg = <0x00c00000 0x3f400000>;
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};
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};
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};
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usb3@f0000 {
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status = "okay";
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usb-phy = <&usb3_phy>;
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};
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};
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bm-bppi {
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status = "okay";
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};
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pcie-controller {
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status = "okay";
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/*
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* The three PCIe units are accessible through
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* standard mini-PCIe slots on the board.
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*/
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pcie@1,0 {
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/* Port 0, Lane 0 */
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status = "okay";
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};
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pcie@2,0 {
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/* Port 1, Lane 0 */
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status = "okay";
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};
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pcie@3,0 {
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/* Port 2, Lane 0 */
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status = "okay";
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};
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};
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};
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usb3_phy: usb3_phy {
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compatible = "usb-nop-xceiv";
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vcc-supply = <®_xhci0_vbus>;
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};
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reg_xhci0_vbus: xhci0-vbus {
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compatible = "regulator-fixed";
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pinctrl-names = "default";
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pinctrl-0 = <&xhci0_vbus_pins>;
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regulator-name = "xhci0-vbus";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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enable-active-high;
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gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
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};
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};
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&spi1 {
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pinctrl-names = "default";
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pinctrl-0 = <&spi1_pins>;
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status = "okay";
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spi-flash@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "st,m25p128", "jedec,spi-nor";
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reg = <0>; /* Chip select 0 */
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spi-max-frequency = <54000000>;
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};
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};
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