6e9dcee4ca
Expand pci_save_state and pci_restore_state to save more of the config state for PCI Express and PCI-X devices. Various writable control registers are present in PCI Express that can potentially be lost over suspend/resume cycle. This change is modeled after similar functionality in Linux. Reviewed by: wlosh,jhb MFC after: 1 month
520 lines
16 KiB
C
520 lines
16 KiB
C
/*-
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* Copyright (c) 1997, Stefan Esser <se@freebsd.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice unmodified, this list of conditions, and the following
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* disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $FreeBSD$
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*
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*/
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#ifndef _PCIVAR_H_
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#define _PCIVAR_H_
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#include <sys/queue.h>
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/* some PCI bus constants */
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#define PCI_MAXMAPS_0 6 /* max. no. of memory/port maps */
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#define PCI_MAXMAPS_1 2 /* max. no. of maps for PCI to PCI bridge */
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#define PCI_MAXMAPS_2 1 /* max. no. of maps for CardBus bridge */
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typedef uint64_t pci_addr_t;
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/* Interesting values for PCI power management */
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struct pcicfg_pp {
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uint16_t pp_cap; /* PCI power management capabilities */
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uint8_t pp_status; /* conf. space addr. of PM control/status reg */
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uint8_t pp_bse; /* conf. space addr. of PM BSE reg */
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uint8_t pp_data; /* conf. space addr. of PM data reg */
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};
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struct pci_map {
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pci_addr_t pm_value; /* Raw BAR value */
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pci_addr_t pm_size;
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uint8_t pm_reg;
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STAILQ_ENTRY(pci_map) pm_link;
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};
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struct vpd_readonly {
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char keyword[2];
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char *value;
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};
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struct vpd_write {
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char keyword[2];
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char *value;
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int start;
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int len;
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};
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struct pcicfg_vpd {
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uint8_t vpd_reg; /* base register, + 2 for addr, + 4 data */
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char vpd_cached;
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char *vpd_ident; /* string identifier */
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int vpd_rocnt;
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struct vpd_readonly *vpd_ros;
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int vpd_wcnt;
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struct vpd_write *vpd_w;
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};
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/* Interesting values for PCI MSI */
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struct pcicfg_msi {
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uint16_t msi_ctrl; /* Message Control */
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uint8_t msi_location; /* Offset of MSI capability registers. */
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uint8_t msi_msgnum; /* Number of messages */
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int msi_alloc; /* Number of allocated messages. */
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uint64_t msi_addr; /* Contents of address register. */
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uint16_t msi_data; /* Contents of data register. */
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u_int msi_handlers;
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};
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/* Interesting values for PCI MSI-X */
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struct msix_vector {
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uint64_t mv_address; /* Contents of address register. */
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uint32_t mv_data; /* Contents of data register. */
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int mv_irq;
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};
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struct msix_table_entry {
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u_int mte_vector; /* 1-based index into msix_vectors array. */
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u_int mte_handlers;
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};
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struct pcicfg_msix {
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uint16_t msix_ctrl; /* Message Control */
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uint16_t msix_msgnum; /* Number of messages */
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uint8_t msix_location; /* Offset of MSI-X capability registers. */
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uint8_t msix_table_bar; /* BAR containing vector table. */
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uint8_t msix_pba_bar; /* BAR containing PBA. */
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uint32_t msix_table_offset;
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uint32_t msix_pba_offset;
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int msix_alloc; /* Number of allocated vectors. */
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int msix_table_len; /* Length of virtual table. */
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struct msix_table_entry *msix_table; /* Virtual table. */
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struct msix_vector *msix_vectors; /* Array of allocated vectors. */
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struct resource *msix_table_res; /* Resource containing vector table. */
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struct resource *msix_pba_res; /* Resource containing PBA. */
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};
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/* Interesting values for HyperTransport */
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struct pcicfg_ht {
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uint8_t ht_slave; /* Non-zero if device is an HT slave. */
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uint8_t ht_msimap; /* Offset of MSI mapping cap registers. */
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uint16_t ht_msictrl; /* MSI mapping control */
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uint64_t ht_msiaddr; /* MSI mapping base address */
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};
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/* Interesting values for PCI-express */
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struct pcicfg_pcie {
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uint8_t pcie_location; /* Offset of PCI-e capability registers. */
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uint8_t pcie_type; /* Device type. */
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uint16_t pcie_flags; /* Device capabilities register. */
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uint16_t pcie_device_ctl; /* Device control register. */
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uint16_t pcie_link_ctl; /* Link control register. */
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uint16_t pcie_slot_ctl; /* Slot control register. */
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uint16_t pcie_root_ctl; /* Root control register. */
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uint16_t pcie_device_ctl2; /* Second device control register. */
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uint16_t pcie_link_ctl2; /* Second link control register. */
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uint16_t pcie_slot_ctl2; /* Second slot control register. */
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};
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struct pcicfg_pcix {
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uint16_t pcix_command;
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uint8_t pcix_location; /* Offset of PCI-X capability registers. */
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};
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/* config header information common to all header types */
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typedef struct pcicfg {
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struct device *dev; /* device which owns this */
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STAILQ_HEAD(, pci_map) maps; /* BARs */
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uint16_t subvendor; /* card vendor ID */
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uint16_t subdevice; /* card device ID, assigned by card vendor */
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uint16_t vendor; /* chip vendor ID */
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uint16_t device; /* chip device ID, assigned by chip vendor */
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uint16_t cmdreg; /* disable/enable chip and PCI options */
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uint16_t statreg; /* supported PCI features and error state */
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uint8_t baseclass; /* chip PCI class */
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uint8_t subclass; /* chip PCI subclass */
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uint8_t progif; /* chip PCI programming interface */
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uint8_t revid; /* chip revision ID */
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uint8_t hdrtype; /* chip config header type */
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uint8_t cachelnsz; /* cache line size in 4byte units */
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uint8_t intpin; /* PCI interrupt pin */
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uint8_t intline; /* interrupt line (IRQ for PC arch) */
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uint8_t mingnt; /* min. useful bus grant time in 250ns units */
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uint8_t maxlat; /* max. tolerated bus grant latency in 250ns */
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uint8_t lattimer; /* latency timer in units of 30ns bus cycles */
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uint8_t mfdev; /* multi-function device (from hdrtype reg) */
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uint8_t nummaps; /* actual number of PCI maps used */
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uint32_t domain; /* PCI domain */
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uint8_t bus; /* config space bus address */
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uint8_t slot; /* config space slot address */
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uint8_t func; /* config space function number */
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struct pcicfg_pp pp; /* Power management */
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struct pcicfg_vpd vpd; /* Vital product data */
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struct pcicfg_msi msi; /* PCI MSI */
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struct pcicfg_msix msix; /* PCI MSI-X */
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struct pcicfg_ht ht; /* HyperTransport */
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struct pcicfg_pcie pcie; /* PCI Express */
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struct pcicfg_pcix pcix; /* PCI-X */
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} pcicfgregs;
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/* additional type 1 device config header information (PCI to PCI bridge) */
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#define PCI_PPBMEMBASE(h,l) ((((pci_addr_t)(h) << 32) + ((l)<<16)) & ~0xfffff)
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#define PCI_PPBMEMLIMIT(h,l) ((((pci_addr_t)(h) << 32) + ((l)<<16)) | 0xfffff)
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#define PCI_PPBIOBASE(h,l) ((((h)<<16) + ((l)<<8)) & ~0xfff)
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#define PCI_PPBIOLIMIT(h,l) ((((h)<<16) + ((l)<<8)) | 0xfff)
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typedef struct {
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pci_addr_t pmembase; /* base address of prefetchable memory */
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pci_addr_t pmemlimit; /* topmost address of prefetchable memory */
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uint32_t membase; /* base address of memory window */
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uint32_t memlimit; /* topmost address of memory window */
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uint32_t iobase; /* base address of port window */
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uint32_t iolimit; /* topmost address of port window */
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uint16_t secstat; /* secondary bus status register */
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uint16_t bridgectl; /* bridge control register */
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uint8_t seclat; /* CardBus latency timer */
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} pcih1cfgregs;
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/* additional type 2 device config header information (CardBus bridge) */
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typedef struct {
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uint32_t membase0; /* base address of memory window */
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uint32_t memlimit0; /* topmost address of memory window */
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uint32_t membase1; /* base address of memory window */
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uint32_t memlimit1; /* topmost address of memory window */
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uint32_t iobase0; /* base address of port window */
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uint32_t iolimit0; /* topmost address of port window */
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uint32_t iobase1; /* base address of port window */
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uint32_t iolimit1; /* topmost address of port window */
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uint32_t pccardif; /* PC Card 16bit IF legacy more base addr. */
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uint16_t secstat; /* secondary bus status register */
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uint16_t bridgectl; /* bridge control register */
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uint8_t seclat; /* CardBus latency timer */
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} pcih2cfgregs;
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extern uint32_t pci_numdevs;
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/* Only if the prerequisites are present */
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#if defined(_SYS_BUS_H_) && defined(_SYS_PCIIO_H_)
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struct pci_devinfo {
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STAILQ_ENTRY(pci_devinfo) pci_links;
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struct resource_list resources;
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pcicfgregs cfg;
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struct pci_conf conf;
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};
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#endif
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#ifdef _SYS_BUS_H_
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#include "pci_if.h"
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enum pci_device_ivars {
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PCI_IVAR_SUBVENDOR,
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PCI_IVAR_SUBDEVICE,
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PCI_IVAR_VENDOR,
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PCI_IVAR_DEVICE,
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PCI_IVAR_DEVID,
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PCI_IVAR_CLASS,
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PCI_IVAR_SUBCLASS,
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PCI_IVAR_PROGIF,
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PCI_IVAR_REVID,
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PCI_IVAR_INTPIN,
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PCI_IVAR_IRQ,
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PCI_IVAR_DOMAIN,
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PCI_IVAR_BUS,
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PCI_IVAR_SLOT,
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PCI_IVAR_FUNCTION,
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PCI_IVAR_ETHADDR,
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PCI_IVAR_CMDREG,
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PCI_IVAR_CACHELNSZ,
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PCI_IVAR_MINGNT,
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PCI_IVAR_MAXLAT,
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PCI_IVAR_LATTIMER
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};
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/*
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* Simplified accessors for pci devices
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*/
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#define PCI_ACCESSOR(var, ivar, type) \
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__BUS_ACCESSOR(pci, var, PCI, ivar, type)
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PCI_ACCESSOR(subvendor, SUBVENDOR, uint16_t)
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PCI_ACCESSOR(subdevice, SUBDEVICE, uint16_t)
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PCI_ACCESSOR(vendor, VENDOR, uint16_t)
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PCI_ACCESSOR(device, DEVICE, uint16_t)
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PCI_ACCESSOR(devid, DEVID, uint32_t)
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PCI_ACCESSOR(class, CLASS, uint8_t)
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PCI_ACCESSOR(subclass, SUBCLASS, uint8_t)
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PCI_ACCESSOR(progif, PROGIF, uint8_t)
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PCI_ACCESSOR(revid, REVID, uint8_t)
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PCI_ACCESSOR(intpin, INTPIN, uint8_t)
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PCI_ACCESSOR(irq, IRQ, uint8_t)
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PCI_ACCESSOR(domain, DOMAIN, uint32_t)
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PCI_ACCESSOR(bus, BUS, uint8_t)
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PCI_ACCESSOR(slot, SLOT, uint8_t)
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PCI_ACCESSOR(function, FUNCTION, uint8_t)
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PCI_ACCESSOR(ether, ETHADDR, uint8_t *)
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PCI_ACCESSOR(cmdreg, CMDREG, uint8_t)
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PCI_ACCESSOR(cachelnsz, CACHELNSZ, uint8_t)
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PCI_ACCESSOR(mingnt, MINGNT, uint8_t)
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PCI_ACCESSOR(maxlat, MAXLAT, uint8_t)
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PCI_ACCESSOR(lattimer, LATTIMER, uint8_t)
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#undef PCI_ACCESSOR
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/*
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* Operations on configuration space.
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*/
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static __inline uint32_t
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pci_read_config(device_t dev, int reg, int width)
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{
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return PCI_READ_CONFIG(device_get_parent(dev), dev, reg, width);
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}
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static __inline void
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pci_write_config(device_t dev, int reg, uint32_t val, int width)
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{
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PCI_WRITE_CONFIG(device_get_parent(dev), dev, reg, val, width);
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}
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/*
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* Ivars for pci bridges.
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*/
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/*typedef enum pci_device_ivars pcib_device_ivars;*/
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enum pcib_device_ivars {
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PCIB_IVAR_DOMAIN,
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PCIB_IVAR_BUS
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};
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#define PCIB_ACCESSOR(var, ivar, type) \
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__BUS_ACCESSOR(pcib, var, PCIB, ivar, type)
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PCIB_ACCESSOR(domain, DOMAIN, uint32_t)
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PCIB_ACCESSOR(bus, BUS, uint32_t)
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#undef PCIB_ACCESSOR
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/*
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* PCI interrupt validation. Invalid interrupt values such as 0 or 128
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* on i386 or other platforms should be mapped out in the MD pcireadconf
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* code and not here, since the only MI invalid IRQ is 255.
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*/
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#define PCI_INVALID_IRQ 255
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#define PCI_INTERRUPT_VALID(x) ((x) != PCI_INVALID_IRQ)
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/*
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* Convenience functions.
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*
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* These should be used in preference to manually manipulating
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* configuration space.
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*/
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static __inline int
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pci_enable_busmaster(device_t dev)
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{
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return(PCI_ENABLE_BUSMASTER(device_get_parent(dev), dev));
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}
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static __inline int
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pci_disable_busmaster(device_t dev)
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{
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return(PCI_DISABLE_BUSMASTER(device_get_parent(dev), dev));
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}
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static __inline int
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pci_enable_io(device_t dev, int space)
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{
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return(PCI_ENABLE_IO(device_get_parent(dev), dev, space));
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}
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static __inline int
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pci_disable_io(device_t dev, int space)
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{
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return(PCI_DISABLE_IO(device_get_parent(dev), dev, space));
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}
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static __inline int
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pci_get_vpd_ident(device_t dev, const char **identptr)
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{
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return(PCI_GET_VPD_IDENT(device_get_parent(dev), dev, identptr));
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}
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static __inline int
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pci_get_vpd_readonly(device_t dev, const char *kw, const char **vptr)
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{
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return(PCI_GET_VPD_READONLY(device_get_parent(dev), dev, kw, vptr));
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}
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/*
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* Check if the address range falls within the VGA defined address range(s)
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*/
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static __inline int
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pci_is_vga_ioport_range(u_long start, u_long end)
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{
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return (((start >= 0x3b0 && end <= 0x3bb) ||
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(start >= 0x3c0 && end <= 0x3df)) ? 1 : 0);
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}
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static __inline int
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pci_is_vga_memory_range(u_long start, u_long end)
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{
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return ((start >= 0xa0000 && end <= 0xbffff) ? 1 : 0);
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}
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/*
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* PCI power states are as defined by ACPI:
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*
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* D0 State in which device is on and running. It is receiving full
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* power from the system and delivering full functionality to the user.
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* D1 Class-specific low-power state in which device context may or may not
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* be lost. Buses in D1 cannot do anything to the bus that would force
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* devices on that bus to lose context.
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* D2 Class-specific low-power state in which device context may or may
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* not be lost. Attains greater power savings than D1. Buses in D2
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* can cause devices on that bus to lose some context. Devices in D2
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* must be prepared for the bus to be in D2 or higher.
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* D3 State in which the device is off and not running. Device context is
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* lost. Power can be removed from the device.
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*/
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#define PCI_POWERSTATE_D0 0
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#define PCI_POWERSTATE_D1 1
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#define PCI_POWERSTATE_D2 2
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#define PCI_POWERSTATE_D3 3
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#define PCI_POWERSTATE_UNKNOWN -1
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static __inline int
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pci_set_powerstate(device_t dev, int state)
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{
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return PCI_SET_POWERSTATE(device_get_parent(dev), dev, state);
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}
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static __inline int
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pci_get_powerstate(device_t dev)
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{
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return PCI_GET_POWERSTATE(device_get_parent(dev), dev);
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}
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static __inline int
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pci_find_cap(device_t dev, int capability, int *capreg)
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{
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return (PCI_FIND_CAP(device_get_parent(dev), dev, capability, capreg));
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}
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static __inline int
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pci_find_extcap(device_t dev, int capability, int *capreg)
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{
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return (PCI_FIND_EXTCAP(device_get_parent(dev), dev, capability, capreg));
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}
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static __inline int
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pci_find_htcap(device_t dev, int capability, int *capreg)
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{
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return (PCI_FIND_HTCAP(device_get_parent(dev), dev, capability, capreg));
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}
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static __inline int
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pci_alloc_msi(device_t dev, int *count)
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{
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return (PCI_ALLOC_MSI(device_get_parent(dev), dev, count));
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}
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static __inline int
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pci_alloc_msix(device_t dev, int *count)
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{
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return (PCI_ALLOC_MSIX(device_get_parent(dev), dev, count));
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}
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static __inline int
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pci_remap_msix(device_t dev, int count, const u_int *vectors)
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{
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return (PCI_REMAP_MSIX(device_get_parent(dev), dev, count, vectors));
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}
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static __inline int
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pci_release_msi(device_t dev)
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{
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return (PCI_RELEASE_MSI(device_get_parent(dev), dev));
|
|
}
|
|
|
|
static __inline int
|
|
pci_msi_count(device_t dev)
|
|
{
|
|
return (PCI_MSI_COUNT(device_get_parent(dev), dev));
|
|
}
|
|
|
|
static __inline int
|
|
pci_msix_count(device_t dev)
|
|
{
|
|
return (PCI_MSIX_COUNT(device_get_parent(dev), dev));
|
|
}
|
|
|
|
device_t pci_find_bsf(uint8_t, uint8_t, uint8_t);
|
|
device_t pci_find_dbsf(uint32_t, uint8_t, uint8_t, uint8_t);
|
|
device_t pci_find_device(uint16_t, uint16_t);
|
|
device_t pci_find_class(uint8_t class, uint8_t subclass);
|
|
|
|
/* Can be used by drivers to manage the MSI-X table. */
|
|
int pci_pending_msix(device_t dev, u_int index);
|
|
|
|
int pci_msi_device_blacklisted(device_t dev);
|
|
|
|
void pci_ht_map_msi(device_t dev, uint64_t addr);
|
|
|
|
int pci_get_max_read_req(device_t dev);
|
|
void pci_restore_state(device_t dev);
|
|
void pci_save_state(device_t dev);
|
|
int pci_set_max_read_req(device_t dev, int size);
|
|
|
|
#endif /* _SYS_BUS_H_ */
|
|
|
|
/*
|
|
* cdev switch for control device, initialised in generic PCI code
|
|
*/
|
|
extern struct cdevsw pcicdev;
|
|
|
|
/*
|
|
* List of all PCI devices, generation count for the list.
|
|
*/
|
|
STAILQ_HEAD(devlist, pci_devinfo);
|
|
|
|
extern struct devlist pci_devq;
|
|
extern uint32_t pci_generation;
|
|
|
|
struct pci_map *pci_find_bar(device_t dev, int reg);
|
|
int pci_bar_enabled(device_t dev, struct pci_map *pm);
|
|
|
|
#endif /* _PCIVAR_H_ */
|