and host1x module. Unfortunately, tegra124 SoC doesn't have 2D acceleration engine and 3D requires not yet started nouveau driver. These drivers forms a first non-x86 DRM2 enabled graphic stack. Note, there are 2 outstanding issues: - The code uses gross hack in order to be comply with OBJT_MGTDEVICE pager. (See tegra_bo_init_pager() in tegra_bo.c) - Due to improper(probably) refcounting in drm_gem_mmap_single() (in drm_gem.c), the gem objects are never released. I hope that I will be able to address both issues in finite time, but I don't want to touch x86 world now. MFC after: 1 month
401 lines
14 KiB
C
401 lines
14 KiB
C
/*-
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* Copyright 1992-2015 Michal Meloun
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _TEGRA_DC_REG_H_
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#define _TEGRA_DC_REG_H_
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/*
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* !!! WARNING !!!
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* Tegra manual uses registers index (and not register addreses).
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* We follow the TRM notation and index is converted to offset in
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* WR4 / RD4 macros
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*/
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/* --------------------------- DC CMD -------------------------------------- */
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#define DC_CMD_GENERAL_INCR_SYNCPT 0x000
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#define DC_CMD_GENERAL_INCR_SYNCPT_CNTRL 0x001
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#define SYNCPT_CNTRL_NO_STALL (1 << 8)
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#define SYNCPT_CNTRL_SOFT_RESET (1 << 0)
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#define DC_CMD_GENERAL_INCR_SYNCPT_ERROR 0x002
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#define DC_CMD_WIN_A_INCR_SYNCPT 0x008
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#define DC_CMD_WIN_A_INCR_SYNCPT_CNTRL 0x009
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#define DC_CMD_WIN_A_INCR_SYNCPT_ERROR 0x00a
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#define DC_CMD_WIN_B_INCR_SYNCPT 0x010
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#define DC_CMD_WIN_B_INCR_SYNCPT_CNTRL 0x011
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#define DC_CMD_WIN_B_INCR_SYNCPT_ERROR 0x012
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#define DC_CMD_WIN_C_INCR_SYNCPT 0x018
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#define DC_CMD_WIN_C_INCR_SYNCPT_CNTRL 0x019
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#define DC_CMD_WIN_C_INCR_SYNCPT_ERROR 0x01a
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#define DC_CMD_CONT_SYNCPT_VSYNC 0x028
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#define SYNCPT_VSYNC_ENABLE (1 << 8)
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#define DC_CMD_CTXSW 0x030
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#define DC_CMD_DISPLAY_COMMAND_OPTION0 0x031
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#define DC_CMD_DISPLAY_COMMAND 0x032
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#define DISPLAY_CTRL_MODE(x) ((x) << 5)
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#define CTRL_MODE_STOP 0
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#define CTRL_MODE_C_DISPLAY 1
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#define CTRL_MODE_NC_DISPLAY 2
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#define DC_CMD_SIGNAL_RAISE 0x033
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#define DC_CMD_DISPLAY_POWER_CONTROL 0x036
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#define PM1_ENABLE (1 << 18)
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#define PM0_ENABLE (1 << 16)
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#define PW4_ENABLE (1 << 8)
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#define PW3_ENABLE (1 << 6)
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#define PW2_ENABLE (1 << 4)
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#define PW1_ENABLE (1 << 2)
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#define PW0_ENABLE (1 << 0)
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#define DC_CMD_INT_STATUS 0x037
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#define DC_CMD_INT_MASK 0x038
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#define DC_CMD_INT_ENABLE 0x039
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#define DC_CMD_INT_TYPE 0x03a
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#define DC_CMD_INT_POLARITY 0x03b
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#define WIN_T_UF_INT (1 << 25)
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#define WIN_D_UF_INT (1 << 24)
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#define HC_UF_INT (1 << 23)
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#define CMU_LUT_CONFLICT_INT (1 << 22)
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#define WIN_C_OF_INT (1 << 16)
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#define WIN_B_OF_INT (1 << 15)
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#define WIN_A_OF_INT (1 << 14)
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#define SSF_INT (1 << 13)
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#define MSF_INT (1 << 12)
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#define WIN_C_UF_INT (1 << 10)
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#define WIN_B_UF_INT (1 << 9)
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#define WIN_A_UF_INT (1 << 8)
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#define SPI_BUSY_INT (1 << 6)
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#define V_PULSE2_INT (1 << 5)
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#define V_PULSE3_INT (1 << 4)
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#define HBLANK_INT (1 << 3)
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#define VBLANK_INT (1 << 2)
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#define FRAME_END_INT (1 << 1)
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#define DC_CMD_STATE_ACCESS 0x040
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#define WRITE_MUX (1 << 2)
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#define READ_MUX (1 << 0)
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#define DC_CMD_STATE_CONTROL 0x041
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#define NC_HOST_TRIG (1 << 24)
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#define CURSOR_UPDATE (1 << 15)
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#define WIN_C_UPDATE (1 << 11)
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#define WIN_B_UPDATE (1 << 10)
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#define WIN_A_UPDATE (1 << 9)
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#define WIN_UPDATE(x) (1 << (9 + (x)))
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#define GENERAL_UPDATE (1 << 8)
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#define CURSOR_ACT_REQ (1 << 7)
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#define WIN_D_ACT_REQ (1 << 4)
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#define WIN_C_ACT_REQ (1 << 3)
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#define WIN_B_ACT_REQ (1 << 2)
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#define WIN_A_ACT_REQ (1 << 1)
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#define WIN_ACT_REQ(x) (1 << (1 + (x)))
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#define GENERAL_ACT_REQ (1 << 0)
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#define DC_CMD_DISPLAY_WINDOW_HEADER 0x042
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#define WINDOW_D_SELECT (1 << 7)
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#define WINDOW_C_SELECT (1 << 6)
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#define WINDOW_B_SELECT (1 << 5)
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#define WINDOW_A_SELECT (1 << 4)
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#define WINDOW_SELECT(x) (1 << (4 + (x)))
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#define DC_CMD_REG_ACT_CONTROL 0x043
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#define DC_CMD_WIN_D_INCR_SYNCPT 0x04c
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#define DC_CMD_WIN_D_INCR_SYNCPT_CNTRL 0x04d
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#define DC_CMD_WIN_D_INCR_SYNCPT_ERROR 0x04e
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/* ---------------------------- DC COM ------------------------------------- */
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/* --------------------------- DC DISP ------------------------------------- */
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#define DC_DISP_DISP_SIGNAL_OPTIONS0 0x400
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#define M1_ENABLE (1 << 26)
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#define M0_ENABLE (1 << 24)
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#define V_PULSE2_ENABLE (1 << 18)
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#define V_PULSE1_ENABLE (1 << 16)
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#define V_PULSE0_ENABLE (1 << 14)
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#define H_PULSE2_ENABLE (1 << 12)
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#define H_PULSE1_ENABLE (1 << 10)
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#define H_PULSE0_ENABLE (1 << 8)
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#define DC_DISP_DISP_SIGNAL_OPTIONS1 0x401
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#define DC_DISP_DISP_WIN_OPTIONS 0x402
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#define HDMI_ENABLE (1 << 30)
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#define DSI_ENABLE (1 << 29)
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#define SOR1_TIMING_CYA (1 << 27)
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#define SOR1_ENABLE (1 << 26)
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#define SOR_ENABLE (1 << 25)
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#define CURSOR_ENABLE (1 << 16)
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#define DC_DISP_DISP_TIMING_OPTIONS 0x405
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#define VSYNC_H_POSITION(x) (((x) & 0xfff) << 0)
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#define DC_DISP_REF_TO_SYNC 0x406
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#define DC_DISP_SYNC_WIDTH 0x407
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#define DC_DISP_BACK_PORCH 0x408
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#define DC_DISP_DISP_ACTIVE 0x409
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#define DC_DISP_FRONT_PORCH 0x40a
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#define DC_DISP_H_PULSE0_CONTROL 0x40b
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#define DC_DISP_H_PULSE0_POSITION_A 0x40c
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#define DC_DISP_H_PULSE0_POSITION_B 0x40d
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#define DC_DISP_H_PULSE0_POSITION_C 0x40e
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#define DC_DISP_H_PULSE0_POSITION_D 0x40f
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#define DC_DISP_H_PULSE1_CONTROL 0x410
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#define DC_DISP_H_PULSE1_POSITION_A 0x411
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#define DC_DISP_H_PULSE1_POSITION_B 0x412
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#define DC_DISP_H_PULSE1_POSITION_C 0x413
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#define DC_DISP_H_PULSE1_POSITION_D 0x414
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#define DC_DISP_H_PULSE2_CONTROL 0x415
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#define DC_DISP_H_PULSE2_POSITION_A 0x416
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#define DC_DISP_H_PULSE2_POSITION_B 0x417
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#define DC_DISP_H_PULSE2_POSITION_C 0x418
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#define DC_DISP_H_PULSE2_POSITION_D 0x419
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#define DC_DISP_V_PULSE0_CONTROL 0x41a
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#define DC_DISP_V_PULSE0_POSITION_A 0x41b
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#define DC_DISP_V_PULSE0_POSITION_B 0x41c
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#define DC_DISP_V_PULSE0_POSITION_C 0x41d
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#define DC_DISP_V_PULSE1_CONTROL 0x41e
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#define DC_DISP_V_PULSE1_POSITION_A 0x41f
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#define DC_DISP_V_PULSE1_POSITION_B 0x420
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#define DC_DISP_V_PULSE1_POSITION_C 0x421
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#define DC_DISP_V_PULSE2_CONTROL 0x422
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#define DC_DISP_V_PULSE2_POSITION_A 0x423
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#define DC_DISP_V_PULSE3_CONTROL 0x424
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#define PULSE_CONTROL_LAST(x) (((x) & 0x7f) << 8)
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#define LAST_START_A 0
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#define LAST_END_A 1
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#define LAST_START_B 2
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#define LAST_END_B 3
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#define LAST_START_C 4
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#define LAST_END_C 5
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#define LAST_START_D 6
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#define LAST_END_D 7
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#define PULSE_CONTROL_QUAL(x) (((x) & 0x3) << 8)
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#define QUAL_ALWAYS 0
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#define QUAL_VACTIVE 2
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#define QUAL_VACTIVE1 3
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#define PULSE_POLARITY (1 << 4)
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#define PULSE_MODE (1 << 3)
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#define DC_DISP_V_PULSE3_POSITION_A 0x425
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#define PULSE_END(x) (((x) & 0xfff) << 16)
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#define PULSE_START(x) (((x) & 0xfff) << 0)
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#define DC_DISP_DISP_CLOCK_CONTROL 0x42e
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#define PIXEL_CLK_DIVIDER(x) (((x) & 0xf) << 8)
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#define PCD1 0
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#define PCD1H 1
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#define PCD2 2
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#define PCD3 3
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#define PCD4 4
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#define PCD6 5
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#define PCD8 6
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#define PCD9 7
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#define PCD12 8
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#define PCD16 9
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#define PCD18 10
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#define PCD24 11
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#define PCD13 12
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#define SHIFT_CLK_DIVIDER(x) ((x) & 0xff)
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#define DC_DISP_DISP_INTERFACE_CONTROL 0x42f
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#define DISP_ORDER_BLUE_RED ( 1 << 9)
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#define DISP_ALIGNMENT_LSB ( 1 << 8)
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#define DISP_DATA_FORMAT(x) (((x) & 0xf) << 8)
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#define DF1P1C 0
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#define DF1P2C24B 1
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#define DF1P2C18B 2
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#define DF1P2C16B 3
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#define DF1S 4
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#define DF2S 5
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#define DF3S 6
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#define DFSPI 7
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#define DF1P3C24B 8
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#define DF2P1C18B 9
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#define DFDUAL1P1C18B 10
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#define DC_DISP_DISP_COLOR_CONTROL 0x430
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#define NON_BASE_COLOR (1 << 18)
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#define BLANK_COLOR (1 << 17)
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#define DISP_COLOR_SWAP (1 << 16)
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#define ORD_DITHER_ROTATION(x) (((x) & 0x3) << 12)
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#define DITHER_CONTROL(x) (((x) & 0x3) << 8)
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#define DITHER_DISABLE 0
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#define DITHER_ORDERED 2
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#define DITHER_TEMPORAL 3
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#define BASE_COLOR_SIZE(x) (((x) & 0xF) << 0)
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#define SIZE_BASE666 0
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#define SIZE_BASE111 1
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#define SIZE_BASE222 2
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#define SIZE_BASE333 3
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#define SIZE_BASE444 4
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#define SIZE_BASE555 5
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#define SIZE_BASE565 6
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#define SIZE_BASE332 7
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#define SIZE_BASE888 8
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#define DC_DISP_CURSOR_START_ADDR 0x43e
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#define CURSOR_CLIP(x) (((x) & 0x3) << 28)
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#define CC_DISPLAY 0
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#define CC_WA 1
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#define CC_WB 2
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#define CC_WC 3
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#define CURSOR_SIZE(x) (((x) & 0x3) << 24)
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#define C32x32 0
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#define C64x64 1
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#define C128x128 2
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#define C256x256 3
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#define CURSOR_START_ADDR(x) (((x) >> 10) & 0x3FFFFF)
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#define DC_DISP_CURSOR_POSITION 0x440
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#define CURSOR_POSITION(h, v) ((((h) & 0x3fff) << 0) | \
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(((v) & 0x3fff) << 16))
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#define DC_DISP_CURSOR_UNDERFLOW_CTRL 0x4eb
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#define DC_DISP_BLEND_CURSOR_CONTROL 0x4f1
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#define CURSOR_MODE_SELECT (1 << 24)
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#define CURSOR_DST_BLEND_FACTOR_SELECT(x) (((x) & 0x3) << 16)
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#define DST_BLEND_ZERO 0
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#define DST_BLEND_K1 1
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#define DST_NEG_K1_TIMES_SRC 2
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#define CURSOR_SRC_BLEND_FACTOR_SELECT(x) (((x) & 0x3) << 8)
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#define SRC_BLEND_K1 0
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#define SRC_BLEND_K1_TIMES_SRC 1
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#define CURSOR_ALPHA(x) (((x) & 0xFF) << 0)
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#define DC_DISP_CURSOR_UFLOW_DBG_PIXEL 0x4f3
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#define CURSOR_UFLOW_CYA (1 << 7)
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#define CURSOR_UFLOW_CTRL_DBG_MODE (1 << 0)
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/* --------------------------- DC WIN ------------------------------------- */
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#define DC_WINC_COLOR_PALETTE 0x500
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#define DC_WINC_CSC_YOF 0x611
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#define DC_WINC_CSC_KYRGB 0x612
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#define DC_WINC_CSC_KUR 0x613
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#define DC_WINC_CSC_KVR 0x614
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#define DC_WINC_CSC_KUG 0x615
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#define DC_WINC_CSC_KVG 0x616
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#define DC_WINC_CSC_KUB 0x617
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#define DC_WINC_CSC_KVB 0x618
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#define DC_WINC_WIN_OPTIONS 0x700
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#define H_FILTER_MODE (1U << 31)
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#define WIN_ENABLE (1 << 30)
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#define INTERLACE_ENABLE (1 << 23)
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#define YUV_RANGE_EXPAND (1 << 22)
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#define DV_ENABLE (1 << 20)
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#define CSC_ENABLE (1 << 18)
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#define CP_ENABLE (1 << 16)
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#define V_FILTER_UV_ALIGN (1 << 14)
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#define V_FILTER_OPTIMIZE (1 << 12)
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#define V_FILTER_ENABLE (1 << 10)
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#define H_FILTER_ENABLE (1 << 8)
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#define COLOR_EXPAND (1 << 6)
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#define SCAN_COLUMN (1 << 4)
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#define V_DIRECTION (1 << 2)
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#define H_DIRECTION (1 << 0)
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#define DC_WIN_BYTE_SWAP 0x701
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#define BYTE_SWAP(x) (((x) & 0x7) << 0)
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#define NOSWAP 0
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#define SWAP2 1
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#define SWAP4 2
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#define SWAP4HW 3
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#define SWAP02 4
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#define SWAPLEFT 5
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#define DC_WIN_COLOR_DEPTH 0x703
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#define WIN_COLOR_DEPTH_P8 3
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#define WIN_COLOR_DEPTH_B4G4R4A4 4
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#define WIN_COLOR_DEPTH_B5G5R5A 5
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#define WIN_COLOR_DEPTH_B5G6R5 6
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#define WIN_COLOR_DEPTH_AB5G5R5 7
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#define WIN_COLOR_DEPTH_B8G8R8A8 12
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#define WIN_COLOR_DEPTH_R8G8B8A8 13
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#define WIN_COLOR_DEPTH_YCbCr422 16
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#define WIN_COLOR_DEPTH_YUV422 17
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#define WIN_COLOR_DEPTH_YCbCr420P 18
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#define WIN_COLOR_DEPTH_YUV420P 19
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#define WIN_COLOR_DEPTH_YCbCr422P 20
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#define WIN_COLOR_DEPTH_YUV422P 21
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#define WIN_COLOR_DEPTH_YCbCr422R 22
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#define WIN_COLOR_DEPTH_YUV422R 23
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#define WIN_COLOR_DEPTH_YCbCr422RA 24
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#define WIN_COLOR_DEPTH_YUV422RA 25
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#define DC_WIN_POSITION 0x704
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#define WIN_POSITION(h, v) ((((h) & 0x1fff) << 0) | \
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(((v) & 0x1fff) << 16))
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#define DC_WIN_SIZE 0x705
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#define WIN_SIZE(h, v) ((((h) & 0x1fff) << 0) | \
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(((v) & 0x1fff) << 16))
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#define DC_WIN_PRESCALED_SIZE 0x706
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#define WIN_PRESCALED_SIZE(h, v) ((((h) & 0x7fff) << 0) | \
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(((v) & 0x1fff) << 16))
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#define DC_WIN_H_INITIAL_DDA 0x707
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#define DC_WIN_V_INITIAL_DDA 0x708
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#define DC_WIN_DDA_INCREMENT 0x709
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#define WIN_DDA_INCREMENT(h, v) ((((h) & 0xffff) << 0) | \
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(((v) & 0xffff) << 16))
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#define DC_WIN_LINE_STRIDE 0x70a
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/* -------------------------- DC WINBUF ------------------------------------ */
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#define DC_WINBUF_START_ADDR 0x800
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#define DC_WINBUF_START_ADDR_NS 0x801
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#define DC_WINBUF_START_ADDR_U 0x802
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#define DC_WINBUF_START_ADDR_U_NS 0x803
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#define DC_WINBUF_START_ADDR_V 0x804
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#define DC_WINBUF_START_ADDR_V_NS 0x805
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#define DC_WINBUF_ADDR_H_OFFSET 0x806
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#define DC_WINBUF_ADDR_H_OFFSET_NS 0x807
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#define DC_WINBUF_ADDR_V_OFFSET 0x808
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#define DC_WINBUF_ADDR_V_OFFSET_NS 0x809
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#define DC_WINBUF_UFLOW_STATUS 0x80a
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#define DC_WINBUF_SURFACE_KIND 0x80b
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#define SURFACE_KIND_BLOCK_HEIGHT(x) (((x) & 0x7) << 4)
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#define SURFACE_KIND_PITCH 0
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#define SURFACE_KIND_TILED 1
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#define SURFACE_KIND_BL_16B2 2
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#define DC_WINBUF_SURFACE_WEIGHT 0x80c
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#define DC_WINBUF_START_ADDR_HI 0x80d
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#define DC_WINBUF_START_ADDR_HI_NS 0x80e
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#define DC_WINBUF_START_ADDR_U_HI 0x80f
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#define DC_WINBUF_START_ADDR_U_HI_NS 0x810
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#define DC_WINBUF_START_ADDR_V_HI 0x811
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#define DC_WINBUF_START_ADDR_V_HI_NS 0x812
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#define DC_WINBUF_UFLOW_CTRL 0x824
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#define UFLOW_CTR_ENABLE (1 << 0)
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#define DC_WINBUF_UFLOW_DBG_PIXEL 0x825
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#endif /* _TEGRA_DC_REG_H_ */
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