ebd63680e4
This syncs us with NetBSD as much of our changes have been upstreamed. Obtained from: NetBSD
125 lines
3.8 KiB
C
125 lines
3.8 KiB
C
/* $NetBSD: ixp425var.h,v 1.12 2009/10/21 14:15:51 rmind Exp $ */
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/*-
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* SPDX-License-Identifier: BSD-2-Clause-NetBSD
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*
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* Copyright (c) 2003
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* Ichiro FUKUHARA <ichiro@ichiro.org>.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS HEAD BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*
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*/
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#ifndef _IXP425VAR_H_
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#define _IXP425VAR_H_
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#include <sys/conf.h>
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#include <sys/queue.h>
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#include <machine/bus.h>
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#include <sys/rman.h>
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/* NB: cputype is setup by set_cpufuncs */
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#define cpu_is_ixp42x() (cputype == CPU_ID_IXP425)
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#define cpu_is_ixp43x() (cputype == CPU_ID_IXP435)
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#define cpu_is_ixp46x() (cputype == CPU_ID_IXP465)
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struct ixp425_softc {
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device_t sc_dev;
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bus_space_tag_t sc_iot;
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bus_space_handle_t sc_gpio_ioh;
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bus_space_handle_t sc_exp_ioh;
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u_int32_t sc_intrmask;
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struct rman sc_irq_rman;
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struct rman sc_mem_rman;
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bus_dma_tag_t sc_dmat;
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};
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void ixp425_set_gpio(struct ixp425_softc *sc, int pin, int type);
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struct ixppcib_softc {
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device_t sc_dev;
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u_int sc_bus;
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struct resource *sc_csr;
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struct resource *sc_mem;
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struct rman sc_io_rman;
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struct rman sc_mem_rman;
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struct rman sc_irq_rman;
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struct bus_space sc_pci_memt;
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struct bus_space sc_pci_iot;
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bus_dma_tag_t sc_dmat;
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};
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#define EXP_BUS_WRITE_4(sc, reg, data) \
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bus_space_write_4(sc->sc_iot, sc->sc_exp_ioh, reg, data)
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#define EXP_BUS_READ_4(sc, reg) \
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bus_space_read_4(sc->sc_iot, sc->sc_exp_ioh, reg)
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#define GPIO_CONF_WRITE_4(sc, reg, data) \
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bus_space_write_4(sc->sc_iot, sc->sc_gpio_ioh, reg, data)
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#define GPIO_CONF_READ_4(sc, reg) \
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bus_space_read_4(sc->sc_iot, sc->sc_gpio_ioh, reg)
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#define IXP4XX_GPIO_LOCK() mtx_lock(&ixp425_gpio_mtx)
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#define IXP4XX_GPIO_UNLOCK() mtx_unlock(&ixp425_gpio_mtx)
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extern struct mtx ixp425_gpio_mtx;
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extern struct bus_space ixp425_bs_tag;
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extern struct bus_space ixp425_a4x_bs_tag;
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extern struct bus_space cambria_exp_bs_tag;
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void cambria_exp_bus_init(struct ixp425_softc *);
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void ixp425_io_bs_init(bus_space_tag_t, void *);
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void ixp425_mem_bs_init(bus_space_tag_t, void *);
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uint32_t ixp425_sdram_size(void);
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uint32_t ixp435_ddram_size(void);
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uint32_t ixp4xx_read_feature_bits(void);
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void ixp4xx_write_feature_bits(uint32_t);
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int ixp425_md_route_interrupt(device_t, device_t, int);
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void ixp425_md_attach(device_t);
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int getvbase(uint32_t, uint32_t, uint32_t *);
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struct ixp425_ivar {
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uint32_t addr;
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int irq;
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};
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#define IXP425_IVAR(d) ((struct ixp425_ivar *) device_get_ivars(d))
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enum {
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IXP425_IVAR_ADDR, /* base physical address */
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IXP425_IVAR_IRQ /* irq/gpio pin assignment */
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};
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#endif /* _IXP425VAR_H_ */
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