536 lines
19 KiB
C
536 lines
19 KiB
C
/*-
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* Copyright (c) 2011 Aleksandr Rybalko.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef __AR8X16_SWITCHREG_H__
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#define __AR8X16_SWITCHREG_H__
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/* XXX doesn't belong here; stolen shamelessly from ath_hal/ah_internal.h */
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/*
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* Register manipulation macros that expect bit field defines
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* to follow the convention that an _S suffix is appended for
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* a shift count, while the field mask has no suffix.
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*/
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#define SM(_v, _f) (((_v) << _f##_S) & (_f))
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#define MS(_v, _f) (((_v) & (_f)) >> _f##_S)
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/* XXX Linux define compatibility stuff */
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#define BIT(_m) (1UL << (_m))
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#define BITM(_count) ((1UL << (_count)) - 1)
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#define BITS(_shift, _count) (BITM(_count) << (_shift))
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/* Atheros specific MII registers */
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#define MII_ATH_MMD_ADDR 0x0d
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#define MII_ATH_MMD_DATA 0x0e
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#define MII_ATH_DBG_ADDR 0x1d
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#define MII_ATH_DBG_DATA 0x1e
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#define AR8X16_REG_MASK_CTRL 0x0000
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#define AR8X16_MASK_CTRL_REV_MASK 0x000000ff
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#define AR8X16_MASK_CTRL_VER_MASK 0x0000ff00
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#define AR8X16_MASK_CTRL_VER_SHIFT 8
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#define AR8X16_MASK_CTRL_SOFT_RESET (1U << 31)
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#define AR8X16_REG_MODE 0x0008
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/* DIR-615 E4 U-Boot */
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#define AR8X16_MODE_DIR_615_UBOOT 0x8d1003e0
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/* From Ubiquiti RSPRO */
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#define AR8X16_MODE_RGMII_PORT4_ISO 0x81461bea
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#define AR8X16_MODE_RGMII_PORT4_SWITCH 0x01261be2
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/* AVM Fritz!Box 7390 */
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#define AR8X16_MODE_GMII 0x010e5b71
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/* from avm_cpmac/linux_ar_reg.h */
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#define AR8X16_MODE_RESERVED 0x000e1b20
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#define AR8X16_MODE_MAC0_GMII_EN (1u << 0)
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#define AR8X16_MODE_MAC0_RGMII_EN (1u << 1)
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#define AR8X16_MODE_PHY4_GMII_EN (1u << 2)
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#define AR8X16_MODE_PHY4_RGMII_EN (1u << 3)
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#define AR8X16_MODE_MAC0_MAC_MODE (1u << 4)
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#define AR8X16_MODE_RGMII_RXCLK_DELAY_EN (1u << 6)
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#define AR8X16_MODE_RGMII_TXCLK_DELAY_EN (1u << 7)
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#define AR8X16_MODE_MAC5_MAC_MODE (1u << 14)
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#define AR8X16_MODE_MAC5_PHY_MODE (1u << 15)
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#define AR8X16_MODE_TXDELAY_S0 (1u << 21)
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#define AR8X16_MODE_TXDELAY_S1 (1u << 22)
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#define AR8X16_MODE_RXDELAY_S0 (1u << 23)
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#define AR8X16_MODE_LED_OPEN_EN (1u << 24)
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#define AR8X16_MODE_SPI_EN (1u << 25)
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#define AR8X16_MODE_RXDELAY_S1 (1u << 26)
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#define AR8X16_MODE_POWER_ON_SEL (1u << 31)
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#define AR8X16_REG_ISR 0x0010
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#define AR8X16_REG_IMR 0x0014
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#define AR8X16_REG_SW_MAC_ADDR0 0x0020
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#define AR8X16_REG_SW_MAC_ADDR1 0x0024
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#define AR8X16_REG_FLOOD_MASK 0x002c
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#define AR8X16_FLOOD_MASK_BCAST_TO_CPU (1 << 26)
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#define AR8X16_REG_GLOBAL_CTRL 0x0030
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#define AR8216_GLOBAL_CTRL_MTU_MASK 0x00000fff
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#define AR8216_GLOBAL_CTRL_MTU_MASK_S 0
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#define AR8316_GLOBAL_CTRL_MTU_MASK 0x00007fff
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#define AR8316_GLOBAL_CTRL_MTU_MASK_S 0
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#define AR8236_GLOBAL_CTRL_MTU_MASK 0x00007fff
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#define AR8236_GLOBAL_CTRL_MTU_MASK_S 0
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#define AR7240_GLOBAL_CTRL_MTU_MASK 0x00003fff
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#define AR7240_GLOBAL_CTRL_MTU_MASK_S 0
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#define AR8X16_REG_VLAN_CTRL 0x0040
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#define AR8X16_VLAN_OP 0x00000007
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#define AR8X16_VLAN_OP_NOOP 0x0
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#define AR8X16_VLAN_OP_FLUSH 0x1
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#define AR8X16_VLAN_OP_LOAD 0x2
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#define AR8X16_VLAN_OP_PURGE 0x3
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#define AR8X16_VLAN_OP_REMOVE_PORT 0x4
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#define AR8X16_VLAN_OP_GET_NEXT 0x5
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#define AR8X16_VLAN_OP_GET 0x6
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#define AR8X16_VLAN_ACTIVE (1 << 3)
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#define AR8X16_VLAN_FULL (1 << 4)
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#define AR8X16_VLAN_PORT 0x00000f00
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#define AR8X16_VLAN_PORT_SHIFT 8
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#define AR8X16_VLAN_VID 0x0fff0000
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#define AR8X16_VLAN_VID_SHIFT 16
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#define AR8X16_VLAN_PRIO 0x70000000
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#define AR8X16_VLAN_PRIO_SHIFT 28
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#define AR8X16_VLAN_PRIO_EN (1U << 31)
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#define AR8X16_REG_VLAN_DATA 0x0044
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#define AR8X16_VLAN_MEMBER 0x0000003f
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#define AR8X16_VLAN_VALID (1 << 11)
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#define AR8216_REG_ATU 0x0050
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#define AR8216_ATU_OP BITS(0, 3)
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#define AR8216_ATU_OP_NOOP 0x0
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#define AR8216_ATU_OP_FLUSH 0x1
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#define AR8216_ATU_OP_LOAD 0x2
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#define AR8216_ATU_OP_PURGE 0x3
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#define AR8216_ATU_OP_FLUSH_LOCKED 0x4
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#define AR8216_ATU_OP_FLUSH_UNICAST 0x5
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#define AR8216_ATU_OP_GET_NEXT 0x6
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#define AR8216_ATU_ACTIVE BIT(3)
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#define AR8216_ATU_PORT_NUM BITS(8, 4)
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#define AR8216_ATU_FULL_VIO BIT(12)
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#define AR8216_ATU_ADDR4 BITS(16, 8)
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#define AR8216_ATU_ADDR5 BITS(24, 8)
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#define AR8216_REG_ATU_DATA 0x0054
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#define AR8216_ATU_ADDR3 BITS(0, 8)
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#define AR8216_ATU_ADDR2 BITS(8, 8)
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#define AR8216_ATU_ADDR1 BITS(16, 8)
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#define AR8216_ATU_ADDR0 BITS(24, 8)
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#define AR8X16_REG_ARL_CTRL2 0x0058
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#define AR8216_REG_ATU_CTRL 0x005C
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#define AR8216_ATU_CTRL_AGE_EN BIT(17)
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#define AR8216_ATU_CTRL_AGE_TIME BITS(0, 16)
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#define AR8216_ATU_CTRL_AGE_TIME_S 0
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#define AR8X16_REG_AT_CTRL 0x005c
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#define AR8X16_AT_CTRL_ARP_EN (1 << 20)
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#define AR8X16_REG_IP_PRIORITY_1 0x0060
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#define AR8X16_REG_IP_PRIORITY_2 0x0064
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#define AR8X16_REG_IP_PRIORITY_3 0x0068
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#define AR8X16_REG_IP_PRIORITY_4 0x006C
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#define AR8X16_REG_TAG_PRIO 0x0070
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#define AR8X16_REG_SERVICE_TAG 0x0074
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#define AR8X16_SERVICE_TAG_MASK 0x0000ffff
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#define AR8X16_REG_CPU_PORT 0x0078
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#define AR8X16_MIRROR_PORT_SHIFT 4
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#define AR8X16_MIRROR_PORT_MASK (0xf << AR8X16_MIRROR_PORT_SHIFT)
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#define AR8X16_CPU_MIRROR_PORT(_p) ((_p) << AR8X16_MIRROR_PORT_SHIFT)
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#define AR8X16_CPU_MIRROR_DIS AR8X16_CPU_MIRROR_PORT(0xf)
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#define AR8X16_CPU_PORT_EN (1 << 8)
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#define AR8X16_REG_MIB_FUNC0 0x0080
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#define AR8X16_MIB_TIMER_MASK 0x0000ffff
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#define AR8X16_MIB_AT_HALF_EN (1 << 16)
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#define AR8X16_MIB_BUSY (1 << 17)
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#define AR8X16_MIB_FUNC_SHIFT 24
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#define AR8X16_MIB_FUNC_NO_OP 0x0
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#define AR8X16_MIB_FUNC_FLUSH 0x1
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#define AR8X16_MIB_FUNC_CAPTURE 0x3
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#define AR8X16_MIB_FUNC_XXX (1 << 30) /* 0x40000000 */
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#define AR934X_MIB_ENABLE (1 << 30)
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#define AR8X16_REG_MDIO_HIGH_ADDR 0x0094
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#define AR8X16_REG_MDIO_CTRL 0x0098
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#define AR8X16_MDIO_CTRL_DATA_MASK 0x0000ffff
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#define AR8X16_MDIO_CTRL_REG_ADDR_SHIFT 16
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#define AR8X16_MDIO_CTRL_PHY_ADDR_SHIFT 21
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#define AR8X16_MDIO_CTRL_CMD_WRITE 0
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#define AR8X16_MDIO_CTRL_CMD_READ (1 << 27)
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#define AR8X16_MDIO_CTRL_MASTER_EN (1 << 30)
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#define AR8X16_MDIO_CTRL_BUSY (1U << 31)
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#define AR8X16_REG_PORT_BASE(_p) (0x0100 + (_p) * 0x0100)
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#define AR8X16_REG_PORT_STS(_p) (AR8X16_REG_PORT_BASE((_p)) + 0x0000)
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#define AR8X16_PORT_STS_SPEED_MASK 0x00000003
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#define AR8X16_PORT_STS_SPEED_10 0
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#define AR8X16_PORT_STS_SPEED_100 1
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#define AR8X16_PORT_STS_SPEED_1000 2
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#define AR8X16_PORT_STS_TXMAC (1 << 2)
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#define AR8X16_PORT_STS_RXMAC (1 << 3)
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#define AR8X16_PORT_STS_TXFLOW (1 << 4)
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#define AR8X16_PORT_STS_RXFLOW (1 << 5)
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#define AR8X16_PORT_STS_DUPLEX (1 << 6)
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#define AR8X16_PORT_STS_LINK_UP (1 << 8)
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#define AR8X16_PORT_STS_LINK_AUTO (1 << 9)
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#define AR8X16_PORT_STS_LINK_PAUSE (1 << 10)
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#define AR8X16_REG_PORT_CTRL(_p) (AR8X16_REG_PORT_BASE((_p)) + 0x0004)
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#define AR8X16_PORT_CTRL_STATE_MASK 0x00000007
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#define AR8X16_PORT_CTRL_STATE_DISABLED 0
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#define AR8X16_PORT_CTRL_STATE_BLOCK 1
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#define AR8X16_PORT_CTRL_STATE_LISTEN 2
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#define AR8X16_PORT_CTRL_STATE_LEARN 3
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#define AR8X16_PORT_CTRL_STATE_FORWARD 4
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#define AR8X16_PORT_CTRL_LEARN_LOCK (1 << 7)
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#define AR8X16_PORT_CTRL_EGRESS_VLAN_MODE_SHIFT 8
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#define AR8X16_PORT_CTRL_EGRESS_VLAN_MODE_KEEP 0
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#define AR8X16_PORT_CTRL_EGRESS_VLAN_MODE_STRIP 1
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#define AR8X16_PORT_CTRL_EGRESS_VLAN_MODE_ADD 2
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#define AR8X16_PORT_CTRL_EGRESS_VLAN_MODE_DOUBLE_TAG 3
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#define AR8X16_PORT_CTRL_IGMP_SNOOP (1 << 10)
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#define AR8X16_PORT_CTRL_HEADER (1 << 11)
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#define AR8X16_PORT_CTRL_MAC_LOOP (1 << 12)
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#define AR8X16_PORT_CTRL_SINGLE_VLAN (1 << 13)
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#define AR8X16_PORT_CTRL_LEARN (1 << 14)
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#define AR8X16_PORT_CTRL_DOUBLE_TAG (1 << 15)
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#define AR8X16_PORT_CTRL_MIRROR_TX (1 << 16)
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#define AR8X16_PORT_CTRL_MIRROR_RX (1 << 17)
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#define AR8X16_REG_PORT_VLAN(_p) (AR8X16_REG_PORT_BASE((_p)) + 0x0008)
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#define AR8X16_PORT_VLAN_DEFAULT_ID_SHIFT 0
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#define AR8X16_PORT_VLAN_DEST_PORTS_SHIFT 16
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#define AR8X16_PORT_VLAN_MODE_MASK 0xc0000000
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#define AR8X16_PORT_VLAN_MODE_SHIFT 30
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#define AR8X16_PORT_VLAN_MODE_PORT_ONLY 0
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#define AR8X16_PORT_VLAN_MODE_PORT_FALLBACK 1
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#define AR8X16_PORT_VLAN_MODE_VLAN_ONLY 2
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#define AR8X16_PORT_VLAN_MODE_SECURE 3
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#define AR8X16_REG_PORT_RATE_LIM(_p) (AR8X16_REG_PORT_BASE((_p)) + 0x000c)
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#define AR8X16_PORT_RATE_LIM_128KB 0
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#define AR8X16_PORT_RATE_LIM_256KB 1
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#define AR8X16_PORT_RATE_LIM_512KB 2
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#define AR8X16_PORT_RATE_LIM_1MB 3
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#define AR8X16_PORT_RATE_LIM_2MB 4
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#define AR8X16_PORT_RATE_LIM_4MB 5
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#define AR8X16_PORT_RATE_LIM_8MB 6
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#define AR8X16_PORT_RATE_LIM_16MB 7
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#define AR8X16_PORT_RATE_LIM_32MB 8
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#define AR8X16_PORT_RATE_LIM_64MB 9
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#define AR8X16_PORT_RATE_LIM_IN_EN (1 << 24)
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#define AR8X16_PORT_RATE_LIM_OUT_EN (1 << 23)
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#define AR8X16_PORT_RATE_LIM_IN_MASK 0x000f0000
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#define AR8X16_PORT_RATE_LIM_IN_SHIFT 16
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#define AR8X16_PORT_RATE_LIM_OUT_MASK 0x0000000f
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#define AR8X16_PORT_RATE_LIM_OUT_SHIFT 0
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#define AR8X16_REG_PORT_PRIORITY(_p) (AR8X16_REG_PORT_BASE((_p)) + 0x0010)
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#define AR8X16_REG_STATS_BASE(_p) (0x20000 + (_p) * 0x100)
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#define AR8X16_STATS_RXBROAD 0x0000
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#define AR8X16_STATS_RXPAUSE 0x0004
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#define AR8X16_STATS_RXMULTI 0x0008
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#define AR8X16_STATS_RXFCSERR 0x000c
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#define AR8X16_STATS_RXALIGNERR 0x0010
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#define AR8X16_STATS_RXRUNT 0x0014
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#define AR8X16_STATS_RXFRAGMENT 0x0018
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#define AR8X16_STATS_RX64BYTE 0x001c
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#define AR8X16_STATS_RX128BYTE 0x0020
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#define AR8X16_STATS_RX256BYTE 0x0024
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#define AR8X16_STATS_RX512BYTE 0x0028
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#define AR8X16_STATS_RX1024BYTE 0x002c
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#define AR8X16_STATS_RX1518BYTE 0x0030
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#define AR8X16_STATS_RXMAXBYTE 0x0034
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#define AR8X16_STATS_RXTOOLONG 0x0038
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#define AR8X16_STATS_RXGOODBYTE 0x003c
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#define AR8X16_STATS_RXBADBYTE 0x0044
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#define AR8X16_STATS_RXOVERFLOW 0x004c
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#define AR8X16_STATS_FILTERED 0x0050
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#define AR8X16_STATS_TXBROAD 0x0054
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#define AR8X16_STATS_TXPAUSE 0x0058
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#define AR8X16_STATS_TXMULTI 0x005c
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#define AR8X16_STATS_TXUNDERRUN 0x0060
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#define AR8X16_STATS_TX64BYTE 0x0064
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#define AR8X16_STATS_TX128BYTE 0x0068
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#define AR8X16_STATS_TX256BYTE 0x006c
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#define AR8X16_STATS_TX512BYTE 0x0070
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#define AR8X16_STATS_TX1024BYTE 0x0074
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#define AR8X16_STATS_TX1518BYTE 0x0078
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#define AR8X16_STATS_TXMAXBYTE 0x007c
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#define AR8X16_STATS_TXOVERSIZE 0x0080
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#define AR8X16_STATS_TXBYTE 0x0084
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#define AR8X16_STATS_TXCOLLISION 0x008c
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#define AR8X16_STATS_TXABORTCOL 0x0090
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#define AR8X16_STATS_TXMULTICOL 0x0094
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#define AR8X16_STATS_TXSINGLECOL 0x0098
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#define AR8X16_STATS_TXEXCDEFER 0x009c
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#define AR8X16_STATS_TXDEFER 0x00a0
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#define AR8X16_STATS_TXLATECOL 0x00a4
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#define AR8X16_PORT_CPU 0
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#define AR8X16_NUM_PORTS 6
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#define AR8X16_NUM_PHYS 5
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#define AR8X16_MAGIC 0xc000050e
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#define AR8X16_PHY_ID1 0x004d
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#define AR8X16_PHY_ID2 0xd041
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#define AR8X16_PORT_MASK(_port) (1 << (_port))
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#define AR8X16_PORT_MASK_ALL ((1<<AR8X16_NUM_PORTS)-1)
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#define AR8X16_PORT_MASK_BUT(_port) (AR8X16_PORT_MASK_ALL & ~(1 << (_port)))
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#define AR8X16_MAX_VLANS 16
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/*
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* AR9340 switch specific definitions.
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*/
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#define AR934X_REG_OPER_MODE0 0x04
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#define AR934X_OPER_MODE0_MAC_GMII_EN (1 << 6)
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#define AR934X_OPER_MODE0_PHY_MII_EN (1 << 10)
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#define AR934X_REG_OPER_MODE1 0x08
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#define AR934X_REG_OPER_MODE1_PHY4_MII_EN (1 << 28)
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#define AR934X_REG_FLOOD_MASK 0x2c
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#define AR934X_FLOOD_MASK_MC_DP(_p) (1 << (16 + (_p)))
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#define AR934X_FLOOD_MASK_BC_DP(_p) (1 << (25 + (_p)))
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#define AR934X_REG_QM_CTRL 0x3c
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#define AR934X_QM_CTRL_ARP_EN (1 << 15)
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#define AR934X_REG_AT_CTRL 0x5c
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#define AR934X_AT_CTRL_AGE_TIME BITS(0, 15)
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#define AR934X_AT_CTRL_AGE_EN (1 << 17)
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#define AR934X_AT_CTRL_LEARN_CHANGE (1 << 18)
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#define AR934X_REG_PORT_BASE(_port) (0x100 + (_port) * 0x100)
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#define AR934X_REG_PORT_VLAN1(_port) (AR934X_REG_PORT_BASE((_port)) + 0x08)
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#define AR934X_PORT_VLAN1_DEFAULT_SVID_S 0
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#define AR934X_PORT_VLAN1_FORCE_DEFAULT_VID_EN (1 << 12)
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#define AR934X_PORT_VLAN1_PORT_TLS_MODE (1 << 13)
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#define AR934X_PORT_VLAN1_PORT_VLAN_PROP_EN (1 << 14)
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#define AR934X_PORT_VLAN1_PORT_CLONE_EN (1 << 15)
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#define AR934X_PORT_VLAN1_DEFAULT_CVID_S 16
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#define AR934X_PORT_VLAN1_FORCE_PORT_VLAN_EN (1 << 28)
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#define AR934X_PORT_VLAN1_ING_PORT_PRI_S 29
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#define AR934X_REG_PORT_VLAN2(_port) (AR934X_REG_PORT_BASE((_port)) + 0x0c)
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#define AR934X_PORT_VLAN2_PORT_VID_MEM_S 16
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#define AR934X_PORT_VLAN2_8021Q_MODE_S 30
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#define AR934X_PORT_VLAN2_8021Q_MODE_PORT_ONLY 0
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#define AR934X_PORT_VLAN2_8021Q_MODE_PORT_FALLBACK 1
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#define AR934X_PORT_VLAN2_8021Q_MODE_VLAN_ONLY 2
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#define AR934X_PORT_VLAN2_8021Q_MODE_SECURE 3
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/*
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* AR8327 specific registers
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*/
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#define AR8327_NUM_PORTS 7
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#define AR8327_NUM_PHYS 5
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#define AR8327_PORTS_ALL 0x7f
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#define AR8327_REG_MASK 0x000
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#define AR8327_REG_PAD0_MODE 0x004
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#define AR8327_REG_PAD5_MODE 0x008
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#define AR8327_REG_PAD6_MODE 0x00c
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#define AR8327_PAD_MAC_MII_RXCLK_SEL (1 << 0)
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#define AR8327_PAD_MAC_MII_TXCLK_SEL (1 << 1)
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#define AR8327_PAD_MAC_MII_EN (1 << 2)
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#define AR8327_PAD_MAC_GMII_RXCLK_SEL (1 << 4)
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#define AR8327_PAD_MAC_GMII_TXCLK_SEL (1 << 5)
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#define AR8327_PAD_MAC_GMII_EN (1 << 6)
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#define AR8327_PAD_SGMII_EN (1 << 7)
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#define AR8327_PAD_PHY_MII_RXCLK_SEL (1 << 8)
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#define AR8327_PAD_PHY_MII_TXCLK_SEL (1 << 9)
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#define AR8327_PAD_PHY_MII_EN (1 << 10)
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#define AR8327_PAD_PHY_GMII_PIPE_RXCLK_SEL (1 << 11)
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#define AR8327_PAD_PHY_GMII_RXCLK_SEL (1 << 12)
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#define AR8327_PAD_PHY_GMII_TXCLK_SEL (1 << 13)
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#define AR8327_PAD_PHY_GMII_EN (1 << 14)
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#define AR8327_PAD_PHYX_GMII_EN (1 << 16)
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#define AR8327_PAD_PHYX_RGMII_EN (1 << 17)
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#define AR8327_PAD_PHYX_MII_EN (1 << 18)
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#define AR8327_PAD_SGMII_DELAY_EN (1 << 19)
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#define AR8327_PAD_RGMII_RXCLK_DELAY_SEL BITS(20, 2)
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#define AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S 20
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#define AR8327_PAD_RGMII_TXCLK_DELAY_SEL BITS(22, 2)
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#define AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S 22
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#define AR8327_PAD_RGMII_RXCLK_DELAY_EN (1 << 24)
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#define AR8327_PAD_RGMII_TXCLK_DELAY_EN (1 << 25)
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#define AR8327_PAD_RGMII_EN (1 << 26)
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#define AR8327_REG_POWER_ON_STRIP 0x010
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#define AR8327_POWER_ON_STRIP_POWER_ON_SEL (1U << 31)
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#define AR8327_POWER_ON_STRIP_LED_OPEN_EN (1 << 24)
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#define AR8327_POWER_ON_STRIP_SERDES_AEN (1 << 7)
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#define AR8327_REG_INT_STATUS0 0x020
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#define AR8327_INT0_VT_DONE (1 << 20)
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#define AR8327_REG_INT_STATUS1 0x024
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#define AR8327_REG_INT_MASK0 0x028
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#define AR8327_REG_INT_MASK1 0x02c
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#define AR8327_REG_MODULE_EN 0x030
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#define AR8327_MODULE_EN_MIB (1 << 0)
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#define AR8327_REG_MIB_FUNC 0x034
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#define AR8327_MIB_CPU_KEEP (1 << 20)
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#define AR8327_REG_MDIO_CTRL 0x03c
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#define AR8327_REG_SERVICE_TAG 0x048
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#define AR8327_REG_LED_CTRL0 0x050
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#define AR8327_REG_LED_CTRL1 0x054
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#define AR8327_REG_LED_CTRL2 0x058
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#define AR8327_REG_LED_CTRL3 0x05c
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#define AR8327_REG_MAC_ADDR0 0x060
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#define AR8327_REG_MAC_ADDR1 0x064
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#define AR8327_REG_MAX_FRAME_SIZE 0x078
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#define AR8327_MAX_FRAME_SIZE_MTU BITS(0, 14)
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#define AR8327_REG_PORT_STATUS(_i) (0x07c + (_i) * 4)
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#define AR8327_REG_HEADER_CTRL 0x098
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#define AR8327_REG_PORT_HEADER(_i) (0x09c + (_i) * 4)
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#define AR8327_REG_SGMII_CTRL 0x0e0
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#define AR8327_SGMII_CTRL_EN_PLL (1 << 1)
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#define AR8327_SGMII_CTRL_EN_RX (1 << 2)
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#define AR8327_SGMII_CTRL_EN_TX (1 << 3)
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#define AR8327_REG_PORT_VLAN0(_i) (0x420 + (_i) * 0x8)
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#define AR8327_PORT_VLAN0_DEF_SVID BITS(0, 12)
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#define AR8327_PORT_VLAN0_DEF_SVID_S 0
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#define AR8327_PORT_VLAN0_DEF_CVID BITS(16, 12)
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#define AR8327_PORT_VLAN0_DEF_CVID_S 16
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#define AR8327_REG_PORT_VLAN1(_i) (0x424 + (_i) * 0x8)
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#define AR8327_PORT_VLAN1_PORT_VLAN_PROP (1 << 6)
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#define AR8327_PORT_VLAN1_OUT_MODE BITS(12, 2)
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#define AR8327_PORT_VLAN1_OUT_MODE_S 12
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#define AR8327_PORT_VLAN1_OUT_MODE_UNMOD 0
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#define AR8327_PORT_VLAN1_OUT_MODE_UNTAG 1
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#define AR8327_PORT_VLAN1_OUT_MODE_TAG 2
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#define AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH 3
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#define AR8327_REG_ATU_DATA0 0x600
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#define AR8327_REG_ATU_DATA1 0x604
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#define AR8327_REG_ATU_DATA2 0x608
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#define AR8327_REG_ATU_FUNC 0x60c
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#define AR8327_ATU_FUNC_OP BITS(0, 4)
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#define AR8327_ATU_FUNC_OP_NOOP 0x0
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#define AR8327_ATU_FUNC_OP_FLUSH 0x1
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#define AR8327_ATU_FUNC_OP_LOAD 0x2
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#define AR8327_ATU_FUNC_OP_PURGE 0x3
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#define AR8327_ATU_FUNC_OP_FLUSH_LOCKED 0x4
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#define AR8327_ATU_FUNC_OP_FLUSH_UNICAST 0x5
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#define AR8327_ATU_FUNC_OP_GET_NEXT 0x6
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#define AR8327_ATU_FUNC_OP_SEARCH_MAC 0x7
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#define AR8327_ATU_FUNC_OP_CHANGE_TRUNK 0x8
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#define AR8327_ATU_FUNC_BUSY (1U << 31)
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#define AR8327_REG_VTU_FUNC0 0x0610
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#define AR8327_VTU_FUNC0_EG_MODE BITS(4, 14)
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#define AR8327_VTU_FUNC0_EG_MODE_S(_i) (4 + (_i) * 2)
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#define AR8327_VTU_FUNC0_EG_MODE_KEEP 0
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#define AR8327_VTU_FUNC0_EG_MODE_UNTAG 1
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#define AR8327_VTU_FUNC0_EG_MODE_TAG 2
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#define AR8327_VTU_FUNC0_EG_MODE_NOT 3
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#define AR8327_VTU_FUNC0_IVL (1 << 19)
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#define AR8327_VTU_FUNC0_VALID (1 << 20)
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#define AR8327_REG_VTU_FUNC1 0x0614
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#define AR8327_VTU_FUNC1_OP BITS(0, 3)
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#define AR8327_VTU_FUNC1_OP_NOOP 0
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#define AR8327_VTU_FUNC1_OP_FLUSH 1
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#define AR8327_VTU_FUNC1_OP_LOAD 2
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#define AR8327_VTU_FUNC1_OP_PURGE 3
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#define AR8327_VTU_FUNC1_OP_REMOVE_PORT 4
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#define AR8327_VTU_FUNC1_OP_GET_NEXT 5
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#define AR8327_VTU_FUNC1_OP_GET_ONE 6
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#define AR8327_VTU_FUNC1_FULL (1 << 4)
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#define AR8327_VTU_FUNC1_PORT (1 << 8, 4)
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#define AR8327_VTU_FUNC1_PORT_S 8
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#define AR8327_VTU_FUNC1_VID (1 << 16, 12)
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#define AR8327_VTU_FUNC1_VID_S 16
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#define AR8327_VTU_FUNC1_BUSY (1U << 31)
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#define AR8327_REG_FWD_CTRL0 0x620
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#define AR8327_FWD_CTRL0_CPU_PORT_EN (1 << 10)
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#define AR8327_FWD_CTRL0_MIRROR_PORT BITS(4, 4)
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#define AR8327_FWD_CTRL0_MIRROR_PORT_S 4
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#define AR8327_REG_FWD_CTRL1 0x624
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#define AR8327_FWD_CTRL1_UC_FLOOD BITS(0, 7)
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#define AR8327_FWD_CTRL1_UC_FLOOD_S 0
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#define AR8327_FWD_CTRL1_MC_FLOOD BITS(8, 7)
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#define AR8327_FWD_CTRL1_MC_FLOOD_S 8
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#define AR8327_FWD_CTRL1_BC_FLOOD BITS(16, 7)
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#define AR8327_FWD_CTRL1_BC_FLOOD_S 16
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#define AR8327_FWD_CTRL1_IGMP BITS(24, 7)
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#define AR8327_FWD_CTRL1_IGMP_S 24
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#define AR8327_REG_PORT_LOOKUP(_i) (0x660 + (_i) * 0xc)
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#define AR8327_PORT_LOOKUP_MEMBER BITS(0, 7)
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#define AR8327_PORT_LOOKUP_IN_MODE BITS(8, 2)
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#define AR8327_PORT_LOOKUP_IN_MODE_S 8
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#define AR8327_PORT_LOOKUP_STATE BITS(16, 3)
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#define AR8327_PORT_LOOKUP_STATE_S 16
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#define AR8327_PORT_LOOKUP_LEARN (1 << 20)
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#define AR8327_PORT_LOOKUP_ING_MIRROR_EN (1 << 25)
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#define AR8327_REG_PORT_PRIO(_i) (0x664 + (_i) * 0xc)
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#define AR8327_REG_PORT_HOL_CTRL1(_i) (0x974 + (_i) * 0x8)
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#define AR8327_PORT_HOL_CTRL1_EG_MIRROR_EN (1 << 16)
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#define AR8327_REG_PORT_STATS_BASE(_i) (0x1000 + (_i) * 0x100)
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#endif /* __AR8X16_SWITCHREG_H__ */
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