3d2533f5c2
When writing to memory on arm64 we may be trying to be accessing a read-only page. In this case try to access via the DMAP region to get a writable location. While here simplify writing data in DDB and stop trashing the size as it is passed into the cache handling functions. Sponsored by: The FreeBSD Foundation Differential Revision: https://reviews.freebsd.org/D32053
253 lines
5.2 KiB
C
253 lines
5.2 KiB
C
/*-
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* Copyright (c) 2014 Andrew Turner
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _MACHINE_CPUFUNC_H_
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#define _MACHINE_CPUFUNC_H_
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static __inline void
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breakpoint(void)
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{
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__asm("brk #0");
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}
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#ifdef _KERNEL
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#define HAVE_INLINE_FFS
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static __inline __pure2 int
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ffs(int mask)
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{
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return (__builtin_ffs(mask));
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}
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#define HAVE_INLINE_FFSL
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static __inline __pure2 int
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ffsl(long mask)
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{
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return (__builtin_ffsl(mask));
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}
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#define HAVE_INLINE_FFSLL
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static __inline __pure2 int
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ffsll(long long mask)
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{
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return (__builtin_ffsll(mask));
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}
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#define HAVE_INLINE_FLS
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static __inline __pure2 int
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fls(int mask)
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{
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return (mask == 0 ? 0 :
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8 * sizeof(mask) - __builtin_clz((u_int)mask));
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}
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#define HAVE_INLINE_FLSL
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static __inline __pure2 int
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flsl(long mask)
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{
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return (mask == 0 ? 0 :
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8 * sizeof(mask) - __builtin_clzl((u_long)mask));
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}
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#define HAVE_INLINE_FLSLL
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static __inline __pure2 int
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flsll(long long mask)
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{
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return (mask == 0 ? 0 :
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8 * sizeof(mask) - __builtin_clzll((unsigned long long)mask));
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}
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#include <machine/armreg.h>
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void pan_enable(void);
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static __inline register_t
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dbg_disable(void)
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{
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uint32_t ret;
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__asm __volatile(
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"mrs %x0, daif \n"
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"msr daifset, #(" __XSTRING(DAIF_D) ") \n"
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: "=&r" (ret));
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return (ret);
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}
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static __inline void
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dbg_enable(void)
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{
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__asm __volatile("msr daifclr, #(" __XSTRING(DAIF_D) ")");
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}
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static __inline register_t
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intr_disable(void)
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{
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/* DAIF is a 32-bit register */
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uint32_t ret;
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__asm __volatile(
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"mrs %x0, daif \n"
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"msr daifset, #(" __XSTRING(DAIF_INTR) ") \n"
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: "=&r" (ret));
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return (ret);
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}
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static __inline void
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intr_restore(register_t s)
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{
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WRITE_SPECIALREG(daif, s);
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}
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static __inline void
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intr_enable(void)
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{
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__asm __volatile("msr daifclr, #(" __XSTRING(DAIF_INTR) ")");
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}
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static __inline void
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serror_enable(void)
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{
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__asm __volatile("msr daifclr, #(" __XSTRING(DAIF_A) ")");
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}
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static __inline register_t
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get_midr(void)
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{
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uint64_t midr;
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midr = READ_SPECIALREG(midr_el1);
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return (midr);
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}
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static __inline register_t
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get_mpidr(void)
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{
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uint64_t mpidr;
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mpidr = READ_SPECIALREG(mpidr_el1);
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return (mpidr);
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}
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static __inline void
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clrex(void)
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{
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/*
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* Ensure compiler barrier, otherwise the monitor clear might
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* occur too late for us ?
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*/
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__asm __volatile("clrex" : : : "memory");
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}
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static __inline void
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set_ttbr0(uint64_t ttbr0)
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{
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__asm __volatile(
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"msr ttbr0_el1, %0 \n"
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"isb \n"
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:
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: "r" (ttbr0));
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}
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static __inline void
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invalidate_icache(void)
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{
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__asm __volatile(
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"ic ialluis \n"
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"dsb ish \n"
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"isb \n");
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}
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static __inline void
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invalidate_local_icache(void)
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{
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__asm __volatile(
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"ic iallu \n"
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"dsb nsh \n"
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"isb \n");
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}
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extern bool icache_aliasing;
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extern bool icache_vmid;
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extern int64_t dcache_line_size;
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extern int64_t icache_line_size;
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extern int64_t idcache_line_size;
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extern int64_t dczva_line_size;
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#define cpu_nullop() arm64_nullop()
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#define cpufunc_nullop() arm64_nullop()
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#define cpu_tlb_flushID() arm64_tlb_flushID()
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#define cpu_dcache_wbinv_range(a, s) arm64_dcache_wbinv_range((a), (s))
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#define cpu_dcache_inv_range(a, s) arm64_dcache_inv_range((a), (s))
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#define cpu_dcache_wb_range(a, s) arm64_dcache_wb_range((a), (s))
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extern void (*arm64_icache_sync_range)(vm_offset_t, vm_size_t);
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#define cpu_icache_sync_range(a, s) arm64_icache_sync_range((a), (s))
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#define cpu_icache_sync_range_checked(a, s) arm64_icache_sync_range_checked((a), (s))
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void arm64_nullop(void);
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void arm64_tlb_flushID(void);
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void arm64_dic_idc_icache_sync_range(vm_offset_t, vm_size_t);
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void arm64_aliasing_icache_sync_range(vm_offset_t, vm_size_t);
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int arm64_icache_sync_range_checked(vm_offset_t, vm_size_t);
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void arm64_dcache_wbinv_range(vm_offset_t, vm_size_t);
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void arm64_dcache_inv_range(vm_offset_t, vm_size_t);
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void arm64_dcache_wb_range(vm_offset_t, vm_size_t);
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bool arm64_get_writable_addr(vm_offset_t, vm_offset_t *);
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#endif /* _KERNEL */
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#endif /* _MACHINE_CPUFUNC_H_ */
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