d3300d4aed
If the mlx5_ib_read_cong_stats() function was running when mlx5ib was unloaded, because this function unconditionally restarts the timer, the timer can still be pending after the delayed work has been cancelled. To fix this simply loop on the delayed work cancel procedure as long as it returns non-zero. Submitted by: hselasky@ Approved by: hselasky (mentor) MFC after: 1 week Sponsored by: Mellanox Technologies
462 lines
14 KiB
C
462 lines
14 KiB
C
/*-
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* Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#include "mlx5_ib.h"
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#include <dev/mlx5/cmd.h>
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static const char *mlx5_ib_cong_params_desc[] = {
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MLX5_IB_CONG_PARAMS(MLX5_IB_STATS_DESC)
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};
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static const char *mlx5_ib_cong_stats_desc[] = {
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MLX5_IB_CONG_STATS(MLX5_IB_STATS_DESC)
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};
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#define MLX5_IB_INDEX(field) (__offsetof(struct mlx5_ib_congestion, field) / sizeof(u64))
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#define MLX5_IB_FLD_MAX(type, field) ((1ULL << __mlx5_bit_sz(type, field)) - 1ULL)
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#define MLX5_IB_SET_CLIPPED(type, ptr, field, var) do { \
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/* rangecheck */ \
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if ((var) > MLX5_IB_FLD_MAX(type, field)) \
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(var) = MLX5_IB_FLD_MAX(type, field); \
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/* set value */ \
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MLX5_SET(type, ptr, field, var); \
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} while (0)
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#define CONG_LOCK(dev) sx_xlock(&(dev)->congestion.lock)
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#define CONG_UNLOCK(dev) sx_xunlock(&(dev)->congestion.lock)
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#define CONG_LOCKED(dev) sx_xlocked(&(dev)->congestion.lock)
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#define MLX5_IB_RP_CLAMP_TGT_RATE_ATTR BIT(1)
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#define MLX5_IB_RP_CLAMP_TGT_RATE_ATI_ATTR BIT(2)
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#define MLX5_IB_RP_TIME_RESET_ATTR BIT(3)
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#define MLX5_IB_RP_BYTE_RESET_ATTR BIT(4)
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#define MLX5_IB_RP_THRESHOLD_ATTR BIT(5)
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#define MLX5_IB_RP_AI_RATE_ATTR BIT(7)
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#define MLX5_IB_RP_HAI_RATE_ATTR BIT(8)
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#define MLX5_IB_RP_MIN_DEC_FAC_ATTR BIT(9)
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#define MLX5_IB_RP_MIN_RATE_ATTR BIT(10)
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#define MLX5_IB_RP_RATE_TO_SET_ON_FIRST_CNP_ATTR BIT(11)
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#define MLX5_IB_RP_DCE_TCP_G_ATTR BIT(12)
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#define MLX5_IB_RP_DCE_TCP_RTT_ATTR BIT(13)
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#define MLX5_IB_RP_RATE_REDUCE_MONITOR_PERIOD_ATTR BIT(14)
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#define MLX5_IB_RP_INITIAL_ALPHA_VALUE_ATTR BIT(15)
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#define MLX5_IB_RP_GD_ATTR BIT(16)
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#define MLX5_IB_NP_CNP_DSCP_ATTR BIT(3)
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#define MLX5_IB_NP_CNP_PRIO_MODE_ATTR BIT(4)
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enum mlx5_ib_cong_node_type {
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MLX5_IB_RROCE_ECN_RP = 1,
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MLX5_IB_RROCE_ECN_NP = 2,
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};
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static enum mlx5_ib_cong_node_type
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mlx5_ib_param_to_node(u32 index)
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{
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if (index >= MLX5_IB_INDEX(rp_clamp_tgt_rate) &&
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index <= MLX5_IB_INDEX(rp_gd))
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return MLX5_IB_RROCE_ECN_RP;
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else
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return MLX5_IB_RROCE_ECN_NP;
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}
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static u64
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mlx5_get_cc_param_val(void *field, u32 index)
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{
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switch (index) {
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case MLX5_IB_INDEX(rp_clamp_tgt_rate):
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return MLX5_GET(cong_control_r_roce_ecn_rp, field,
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clamp_tgt_rate);
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case MLX5_IB_INDEX(rp_clamp_tgt_rate_ati):
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return MLX5_GET(cong_control_r_roce_ecn_rp, field,
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clamp_tgt_rate_after_time_inc);
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case MLX5_IB_INDEX(rp_time_reset):
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return MLX5_GET(cong_control_r_roce_ecn_rp, field,
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rpg_time_reset);
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case MLX5_IB_INDEX(rp_byte_reset):
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return MLX5_GET(cong_control_r_roce_ecn_rp, field,
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rpg_byte_reset);
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case MLX5_IB_INDEX(rp_threshold):
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return MLX5_GET(cong_control_r_roce_ecn_rp, field,
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rpg_threshold);
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case MLX5_IB_INDEX(rp_ai_rate):
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return MLX5_GET(cong_control_r_roce_ecn_rp, field,
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rpg_ai_rate);
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case MLX5_IB_INDEX(rp_hai_rate):
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return MLX5_GET(cong_control_r_roce_ecn_rp, field,
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rpg_hai_rate);
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case MLX5_IB_INDEX(rp_min_dec_fac):
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return MLX5_GET(cong_control_r_roce_ecn_rp, field,
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rpg_min_dec_fac);
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case MLX5_IB_INDEX(rp_min_rate):
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return MLX5_GET(cong_control_r_roce_ecn_rp, field,
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rpg_min_rate);
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case MLX5_IB_INDEX(rp_rate_to_set_on_first_cnp):
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return MLX5_GET(cong_control_r_roce_ecn_rp, field,
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rate_to_set_on_first_cnp);
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case MLX5_IB_INDEX(rp_dce_tcp_g):
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return MLX5_GET(cong_control_r_roce_ecn_rp, field,
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dce_tcp_g);
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case MLX5_IB_INDEX(rp_dce_tcp_rtt):
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return MLX5_GET(cong_control_r_roce_ecn_rp, field,
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dce_tcp_rtt);
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case MLX5_IB_INDEX(rp_rate_reduce_monitor_period):
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return MLX5_GET(cong_control_r_roce_ecn_rp, field,
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rate_reduce_monitor_period);
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case MLX5_IB_INDEX(rp_initial_alpha_value):
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return MLX5_GET(cong_control_r_roce_ecn_rp, field,
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initial_alpha_value);
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case MLX5_IB_INDEX(rp_gd):
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return MLX5_GET(cong_control_r_roce_ecn_rp, field,
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rpg_gd);
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case MLX5_IB_INDEX(np_cnp_dscp):
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return MLX5_GET(cong_control_r_roce_ecn_np, field,
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cnp_dscp);
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case MLX5_IB_INDEX(np_cnp_prio_mode):
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return MLX5_GET(cong_control_r_roce_ecn_np, field,
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cnp_prio_mode);
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case MLX5_IB_INDEX(np_cnp_prio):
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return MLX5_GET(cong_control_r_roce_ecn_np, field,
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cnp_802p_prio);
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default:
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return 0;
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}
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}
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static void
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mlx5_ib_set_cc_param_mask_val(void *field, u32 index,
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u64 var, u32 *attr_mask)
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{
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switch (index) {
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case MLX5_IB_INDEX(rp_clamp_tgt_rate):
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*attr_mask |= MLX5_IB_RP_CLAMP_TGT_RATE_ATTR;
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MLX5_IB_SET_CLIPPED(cong_control_r_roce_ecn_rp, field,
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clamp_tgt_rate, var);
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break;
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case MLX5_IB_INDEX(rp_clamp_tgt_rate_ati):
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*attr_mask |= MLX5_IB_RP_CLAMP_TGT_RATE_ATI_ATTR;
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MLX5_IB_SET_CLIPPED(cong_control_r_roce_ecn_rp, field,
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clamp_tgt_rate_after_time_inc, var);
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break;
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case MLX5_IB_INDEX(rp_time_reset):
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*attr_mask |= MLX5_IB_RP_TIME_RESET_ATTR;
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MLX5_IB_SET_CLIPPED(cong_control_r_roce_ecn_rp, field,
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rpg_time_reset, var);
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break;
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case MLX5_IB_INDEX(rp_byte_reset):
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*attr_mask |= MLX5_IB_RP_BYTE_RESET_ATTR;
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MLX5_IB_SET_CLIPPED(cong_control_r_roce_ecn_rp, field,
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rpg_byte_reset, var);
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break;
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case MLX5_IB_INDEX(rp_threshold):
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*attr_mask |= MLX5_IB_RP_THRESHOLD_ATTR;
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MLX5_IB_SET_CLIPPED(cong_control_r_roce_ecn_rp, field,
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rpg_threshold, var);
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break;
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case MLX5_IB_INDEX(rp_ai_rate):
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*attr_mask |= MLX5_IB_RP_AI_RATE_ATTR;
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MLX5_IB_SET_CLIPPED(cong_control_r_roce_ecn_rp, field,
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rpg_ai_rate, var);
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break;
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case MLX5_IB_INDEX(rp_hai_rate):
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*attr_mask |= MLX5_IB_RP_HAI_RATE_ATTR;
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MLX5_IB_SET_CLIPPED(cong_control_r_roce_ecn_rp, field,
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rpg_hai_rate, var);
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break;
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case MLX5_IB_INDEX(rp_min_dec_fac):
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*attr_mask |= MLX5_IB_RP_MIN_DEC_FAC_ATTR;
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MLX5_IB_SET_CLIPPED(cong_control_r_roce_ecn_rp, field,
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rpg_min_dec_fac, var);
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break;
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case MLX5_IB_INDEX(rp_min_rate):
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*attr_mask |= MLX5_IB_RP_MIN_RATE_ATTR;
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MLX5_IB_SET_CLIPPED(cong_control_r_roce_ecn_rp, field,
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rpg_min_rate, var);
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break;
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case MLX5_IB_INDEX(rp_rate_to_set_on_first_cnp):
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*attr_mask |= MLX5_IB_RP_RATE_TO_SET_ON_FIRST_CNP_ATTR;
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MLX5_IB_SET_CLIPPED(cong_control_r_roce_ecn_rp, field,
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rate_to_set_on_first_cnp, var);
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break;
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case MLX5_IB_INDEX(rp_dce_tcp_g):
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*attr_mask |= MLX5_IB_RP_DCE_TCP_G_ATTR;
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MLX5_IB_SET_CLIPPED(cong_control_r_roce_ecn_rp, field,
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dce_tcp_g, var);
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break;
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case MLX5_IB_INDEX(rp_dce_tcp_rtt):
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*attr_mask |= MLX5_IB_RP_DCE_TCP_RTT_ATTR;
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MLX5_IB_SET_CLIPPED(cong_control_r_roce_ecn_rp, field,
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dce_tcp_rtt, var);
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break;
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case MLX5_IB_INDEX(rp_rate_reduce_monitor_period):
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*attr_mask |= MLX5_IB_RP_RATE_REDUCE_MONITOR_PERIOD_ATTR;
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MLX5_IB_SET_CLIPPED(cong_control_r_roce_ecn_rp, field,
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rate_reduce_monitor_period, var);
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break;
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case MLX5_IB_INDEX(rp_initial_alpha_value):
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*attr_mask |= MLX5_IB_RP_INITIAL_ALPHA_VALUE_ATTR;
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MLX5_IB_SET_CLIPPED(cong_control_r_roce_ecn_rp, field,
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initial_alpha_value, var);
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break;
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case MLX5_IB_INDEX(rp_gd):
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*attr_mask |= MLX5_IB_RP_GD_ATTR;
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MLX5_IB_SET_CLIPPED(cong_control_r_roce_ecn_rp, field,
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rpg_gd, var);
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break;
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case MLX5_IB_INDEX(np_cnp_dscp):
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*attr_mask |= MLX5_IB_NP_CNP_DSCP_ATTR;
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MLX5_IB_SET_CLIPPED(cong_control_r_roce_ecn_np, field, cnp_dscp, var);
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break;
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case MLX5_IB_INDEX(np_cnp_prio_mode):
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*attr_mask |= MLX5_IB_NP_CNP_PRIO_MODE_ATTR;
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MLX5_IB_SET_CLIPPED(cong_control_r_roce_ecn_np, field, cnp_prio_mode, var);
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break;
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case MLX5_IB_INDEX(np_cnp_prio):
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*attr_mask |= MLX5_IB_NP_CNP_PRIO_MODE_ATTR;
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MLX5_SET(cong_control_r_roce_ecn_np, field, cnp_prio_mode, 0);
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MLX5_IB_SET_CLIPPED(cong_control_r_roce_ecn_np, field, cnp_802p_prio, var);
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break;
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default:
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break;
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}
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}
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static int
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mlx5_ib_get_all_cc_params(struct mlx5_ib_dev *dev)
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{
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int outlen = MLX5_ST_SZ_BYTES(query_cong_params_out);
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enum mlx5_ib_cong_node_type node = 0;
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void *out;
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void *field;
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u32 x;
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int err = 0;
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out = kzalloc(outlen, GFP_KERNEL);
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if (!out)
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return -ENOMEM;
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/* get the current values */
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for (x = 0; x != MLX5_IB_CONG_PARAMS_NUM; x++) {
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if (node != mlx5_ib_param_to_node(x)) {
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node = mlx5_ib_param_to_node(x);
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err = mlx5_cmd_query_cong_params(dev->mdev, node, out, outlen);
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if (err)
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break;
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}
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field = MLX5_ADDR_OF(query_cong_params_out, out, congestion_parameters);
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dev->congestion.arg[x] = mlx5_get_cc_param_val(field, x);
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}
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kfree(out);
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return err;
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}
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static int
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mlx5_ib_set_cc_params(struct mlx5_ib_dev *dev, u32 index, u64 var)
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{
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int inlen = MLX5_ST_SZ_BYTES(modify_cong_params_in);
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enum mlx5_ib_cong_node_type node;
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u32 attr_mask = 0;
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void *field;
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void *in;
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int err;
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in = kzalloc(inlen, GFP_KERNEL);
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if (!in)
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return -ENOMEM;
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MLX5_SET(modify_cong_params_in, in, opcode,
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MLX5_CMD_OP_MODIFY_CONG_PARAMS);
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node = mlx5_ib_param_to_node(index);
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MLX5_SET(modify_cong_params_in, in, cong_protocol, node);
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field = MLX5_ADDR_OF(modify_cong_params_in, in, congestion_parameters);
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mlx5_ib_set_cc_param_mask_val(field, index, var, &attr_mask);
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field = MLX5_ADDR_OF(modify_cong_params_in, in, field_select);
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MLX5_SET(field_select_r_roce_rp, field, field_select_r_roce_rp,
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attr_mask);
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err = mlx5_cmd_modify_cong_params(dev->mdev, in, inlen);
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kfree(in);
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return err;
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}
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static int
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mlx5_ib_cong_params_handler(SYSCTL_HANDLER_ARGS)
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{
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struct mlx5_ib_dev *dev = arg1;
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u64 value;
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int error;
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CONG_LOCK(dev);
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value = dev->congestion.arg[arg2];
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if (req != NULL) {
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error = sysctl_handle_64(oidp, &value, 0, req);
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if (error || req->newptr == NULL ||
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value == dev->congestion.arg[arg2])
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goto done;
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/* assign new value */
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dev->congestion.arg[arg2] = value;
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} else {
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error = 0;
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}
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if (!MLX5_CAP_GEN(dev->mdev, cc_modify_allowed))
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error = EPERM;
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else {
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error = -mlx5_ib_set_cc_params(dev, MLX5_IB_INDEX(arg[arg2]),
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dev->congestion.arg[arg2]);
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}
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done:
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CONG_UNLOCK(dev);
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return (error);
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}
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#define MLX5_GET_UNALIGNED_64(t,p,f) \
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(((u64)MLX5_GET(t,p,f##_high) << 32) | MLX5_GET(t,p,f##_low))
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static void
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mlx5_ib_read_cong_stats(struct work_struct *work)
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{
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struct mlx5_ib_dev *dev =
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container_of(work, struct mlx5_ib_dev, congestion.dwork.work);
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const int outlen = MLX5_ST_SZ_BYTES(query_cong_statistics_out);
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void *out;
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out = kzalloc(outlen, GFP_KERNEL);
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if (!out)
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goto done;
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CONG_LOCK(dev);
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if (mlx5_cmd_query_cong_counter(dev->mdev, 0, out, outlen))
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memset(out, 0, outlen);
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dev->congestion.syndrome =
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MLX5_GET(query_cong_statistics_out, out, syndrome);
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dev->congestion.rp_cur_flows =
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MLX5_GET(query_cong_statistics_out, out, rp_cur_flows);
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dev->congestion.sum_flows =
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MLX5_GET(query_cong_statistics_out, out, sum_flows);
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dev->congestion.rp_cnp_ignored =
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MLX5_GET_UNALIGNED_64(query_cong_statistics_out, out, rp_cnp_ignored);
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dev->congestion.rp_cnp_handled =
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MLX5_GET_UNALIGNED_64(query_cong_statistics_out, out, rp_cnp_handled);
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dev->congestion.time_stamp =
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MLX5_GET_UNALIGNED_64(query_cong_statistics_out, out, time_stamp);
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dev->congestion.accumulators_period =
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MLX5_GET(query_cong_statistics_out, out, accumulators_period);
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dev->congestion.np_ecn_marked_roce_packets =
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MLX5_GET_UNALIGNED_64(query_cong_statistics_out, out, np_ecn_marked_roce_packets);
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dev->congestion.np_cnp_sent =
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MLX5_GET_UNALIGNED_64(query_cong_statistics_out, out, np_cnp_sent);
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CONG_UNLOCK(dev);
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kfree(out);
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done:
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schedule_delayed_work(&dev->congestion.dwork, hz);
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}
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void
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mlx5_ib_cleanup_congestion(struct mlx5_ib_dev *dev)
|
|
{
|
|
|
|
while (cancel_delayed_work_sync(&dev->congestion.dwork))
|
|
;
|
|
sysctl_ctx_free(&dev->congestion.ctx);
|
|
sx_destroy(&dev->congestion.lock);
|
|
}
|
|
|
|
int
|
|
mlx5_ib_init_congestion(struct mlx5_ib_dev *dev)
|
|
{
|
|
struct sysctl_ctx_list *ctx;
|
|
struct sysctl_oid *parent;
|
|
struct sysctl_oid *node;
|
|
int err;
|
|
u32 x;
|
|
|
|
ctx = &dev->congestion.ctx;
|
|
sysctl_ctx_init(ctx);
|
|
sx_init(&dev->congestion.lock, "mlx5ibcong");
|
|
INIT_DELAYED_WORK(&dev->congestion.dwork, mlx5_ib_read_cong_stats);
|
|
|
|
if (!MLX5_CAP_GEN(dev->mdev, cc_query_allowed))
|
|
return (0);
|
|
|
|
err = mlx5_ib_get_all_cc_params(dev);
|
|
if (err)
|
|
return (err);
|
|
|
|
parent = SYSCTL_ADD_NODE(ctx, SYSCTL_CHILDREN(dev->ib_dev.dev.kobj.oidp),
|
|
OID_AUTO, "cong", CTLFLAG_RW, NULL, "Congestion control");
|
|
if (parent == NULL)
|
|
return (-ENOMEM);
|
|
|
|
node = SYSCTL_ADD_NODE(ctx, SYSCTL_CHILDREN(parent),
|
|
OID_AUTO, "conf", CTLFLAG_RW, NULL, "Configuration");
|
|
if (node == NULL) {
|
|
sysctl_ctx_free(&dev->congestion.ctx);
|
|
return (-ENOMEM);
|
|
}
|
|
|
|
for (x = 0; x != MLX5_IB_CONG_PARAMS_NUM; x++) {
|
|
SYSCTL_ADD_PROC(ctx,
|
|
SYSCTL_CHILDREN(node), OID_AUTO,
|
|
mlx5_ib_cong_params_desc[2 * x],
|
|
CTLTYPE_U64 | CTLFLAG_RWTUN | CTLFLAG_MPSAFE,
|
|
dev, x, &mlx5_ib_cong_params_handler, "QU",
|
|
mlx5_ib_cong_params_desc[2 * x + 1]);
|
|
}
|
|
|
|
node = SYSCTL_ADD_NODE(ctx, SYSCTL_CHILDREN(parent),
|
|
OID_AUTO, "stats", CTLFLAG_RD, NULL, "Statistics");
|
|
if (node == NULL) {
|
|
sysctl_ctx_free(&dev->congestion.ctx);
|
|
return (-ENOMEM);
|
|
}
|
|
|
|
for (x = 0; x != MLX5_IB_CONG_STATS_NUM; x++) {
|
|
/* read-only SYSCTLs */
|
|
SYSCTL_ADD_U64(ctx, SYSCTL_CHILDREN(node), OID_AUTO,
|
|
mlx5_ib_cong_stats_desc[2 * x],
|
|
CTLFLAG_RD | CTLFLAG_MPSAFE,
|
|
&dev->congestion.arg[x + MLX5_IB_CONG_PARAMS_NUM],
|
|
0, mlx5_ib_cong_stats_desc[2 * x + 1]);
|
|
}
|
|
schedule_delayed_work(&dev->congestion.dwork, hz);
|
|
return (0);
|
|
}
|