9d45af5c09
This is derived from similar work done in r310481 for i386 and r312610 for armv6/armv7. Additionally, use a critical section to keep the thread pinned for per-CPU operations instead of completely disabling local interrupts. No objections from: adrian, jmallett, imp Differential Revision: https://reviews.freebsd.org/D18593
101 lines
3.6 KiB
C
101 lines
3.6 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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* Copyright (c) 1999 Luoqi Chen <luoqi@freebsd.org>
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* Copyright (c) Peter Wemm <peter@netplex.com.au>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* from: src/sys/alpha/include/pcpu.h,v 1.15 2004/11/05 19:16:44 jhb
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* $FreeBSD$
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*/
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#ifndef _MACHINE_PCPU_H_
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#define _MACHINE_PCPU_H_
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#include <machine/cpufunc.h>
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#include <machine/pte.h>
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#define PCPU_MD_COMMON_FIELDS \
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pd_entry_t *pc_segbase; /* curthread segbase */ \
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struct pmap *pc_curpmap; /* pmap of curthread */ \
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u_int32_t pc_next_asid; /* next ASID to alloc */ \
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u_int32_t pc_asid_generation; /* current ASID generation */ \
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u_int pc_pending_ipis; /* IPIs pending to this CPU */ \
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struct pcpu *pc_self; /* globally-uniqe self pointer */
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#ifdef __mips_n64
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#define PCPU_MD_MIPS64_FIELDS \
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PCPU_MD_COMMON_FIELDS \
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char __pad[245]
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#else
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#define PCPU_MD_MIPS32_FIELDS \
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PCPU_MD_COMMON_FIELDS \
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pt_entry_t *pc_cmap1_ptep; /* PTE for copy window 1 KVA */ \
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pt_entry_t *pc_cmap2_ptep; /* PTE for copy window 2 KVA */ \
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vm_offset_t pc_cmap1_addr; /* KVA page for copy window 1 */ \
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vm_offset_t pc_cmap2_addr; /* KVA page for copy window 2 */ \
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vm_offset_t pc_qmap_addr; /* KVA page for temporary mappings */ \
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pt_entry_t *pc_qmap_ptep; /* PTE for temporary mapping KVA */ \
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char __pad[101]
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#endif
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#ifdef __mips_n64
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#define PCPU_MD_FIELDS PCPU_MD_MIPS64_FIELDS
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#else
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#define PCPU_MD_FIELDS PCPU_MD_MIPS32_FIELDS
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#endif
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#ifdef _KERNEL
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extern char pcpu_space[MAXCPU][PAGE_SIZE * 2];
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#define PCPU_ADDR(cpu) (struct pcpu *)(pcpu_space[(cpu)])
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extern struct pcpu *pcpup;
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#define PCPUP pcpup
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/*
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* Since we use a wired TLB entry to map the same VA to a different
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* physical page for each CPU, get_pcpu() must use the pc_self
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* field to obtain a globally-unique pointer.
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*/
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#define get_pcpu() (PCPUP->pc_self)
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#define PCPU_ADD(member, value) (PCPUP->pc_ ## member += (value))
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#define PCPU_GET(member) (PCPUP->pc_ ## member)
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#define PCPU_INC(member) PCPU_ADD(member, 1)
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#define PCPU_PTR(member) (&PCPUP->pc_ ## member)
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#define PCPU_SET(member,value) (PCPUP->pc_ ## member = (value))
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#define PCPU_LAZY_INC(member) (++PCPUP->pc_ ## member)
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#ifdef SMP
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/*
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* Instantiate the wired TLB entry at PCPU_TLB_ENTRY to map 'pcpu' at 'pcpup'.
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*/
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void mips_pcpu_tlb_init(struct pcpu *pcpu);
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#endif
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#endif /* _KERNEL */
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#endif /* !_MACHINE_PCPU_H_ */
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