628 lines
16 KiB
C
628 lines
16 KiB
C
/*-
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* Copyright (C) 1995, 1996 Wolfgang Solfrank.
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* Copyright (C) 1995, 1996 TooLs GmbH.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by TooLs GmbH.
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* 4. The name of TooLs GmbH may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*-
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* Copyright (C) 2001 Benno Rice
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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* $NetBSD: machdep.c,v 1.74.2.1 2000/11/01 16:13:48 tv Exp $
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include "opt_compat.h"
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#include "opt_ddb.h"
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#include "opt_kstack_pages.h"
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#include "opt_platform.h"
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#include <sys/param.h>
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#include <sys/proc.h>
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#include <sys/systm.h>
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#include <sys/bio.h>
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#include <sys/buf.h>
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#include <sys/bus.h>
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#include <sys/cons.h>
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#include <sys/cpu.h>
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#include <sys/eventhandler.h>
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#include <sys/exec.h>
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#include <sys/imgact.h>
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#include <sys/kdb.h>
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#include <sys/kernel.h>
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#include <sys/ktr.h>
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#include <sys/linker.h>
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#include <sys/lock.h>
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#include <sys/malloc.h>
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#include <sys/mbuf.h>
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#include <sys/msgbuf.h>
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#include <sys/mutex.h>
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#include <sys/ptrace.h>
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#include <sys/reboot.h>
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#include <sys/rwlock.h>
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#include <sys/signalvar.h>
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#include <sys/syscallsubr.h>
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#include <sys/sysctl.h>
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#include <sys/sysent.h>
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#include <sys/sysproto.h>
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#include <sys/ucontext.h>
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#include <sys/uio.h>
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#include <sys/vmmeter.h>
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#include <sys/vnode.h>
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#include <net/netisr.h>
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#include <vm/vm.h>
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#include <vm/vm_extern.h>
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#include <vm/vm_kern.h>
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#include <vm/vm_page.h>
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#include <vm/vm_map.h>
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#include <vm/vm_object.h>
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#include <vm/vm_pager.h>
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#include <machine/altivec.h>
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#ifndef __powerpc64__
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#include <machine/bat.h>
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#endif
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#include <machine/cpu.h>
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#include <machine/elf.h>
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#include <machine/fpu.h>
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#include <machine/hid.h>
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#include <machine/kdb.h>
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#include <machine/md_var.h>
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#include <machine/metadata.h>
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#include <machine/mmuvar.h>
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#include <machine/pcb.h>
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#include <machine/reg.h>
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#include <machine/sigframe.h>
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#include <machine/spr.h>
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#include <machine/trap.h>
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#include <machine/vmparam.h>
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#include <machine/ofw_machdep.h>
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#include <ddb/ddb.h>
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#include <dev/ofw/openfirm.h>
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#ifdef __powerpc64__
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extern int n_slbs;
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#endif
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#ifndef __powerpc64__
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struct bat battable[16];
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#endif
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#ifndef __powerpc64__
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/* Bits for running on 64-bit systems in 32-bit mode. */
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extern void *testppc64, *testppc64size;
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extern void *restorebridge, *restorebridgesize;
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extern void *rfid_patch, *rfi_patch1, *rfi_patch2;
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extern void *trapcode64;
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extern Elf_Addr _GLOBAL_OFFSET_TABLE_[];
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#endif
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extern void *rstcode, *rstcodeend;
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extern void *trapcode, *trapcodeend;
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extern void *generictrap, *generictrap64;
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extern void *slbtrap, *slbtrapend;
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extern void *alitrap, *aliend;
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extern void *dsitrap, *dsiend;
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extern void *decrint, *decrsize;
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extern void *extint, *extsize;
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extern void *dblow, *dbend;
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extern void *imisstrap, *imisssize;
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extern void *dlmisstrap, *dlmisssize;
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extern void *dsmisstrap, *dsmisssize;
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extern void *ap_pcpu;
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void aim_cpu_init(vm_offset_t toc);
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void
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aim_cpu_init(vm_offset_t toc)
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{
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size_t trap_offset, trapsize;
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vm_offset_t trap;
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register_t msr, scratch;
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uint8_t *cache_check;
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int cacheline_warn;
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#ifndef __powerpc64__
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int ppc64;
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#endif
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trap_offset = 0;
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cacheline_warn = 0;
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#ifdef __powerpc64__
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/*
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* Switch to 64-bit mode, if the bootloader didn't, before we start
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* using memory beyond what the bootloader might have set up.
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* Guaranteed not to cause an implicit branch since we either (a)
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* started with a 32-bit bootloader below 4 GB or (b) were already in
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* 64-bit mode, making this a no-op.
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*/
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mtmsrd(mfmsr() | PSL_SF);
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#endif
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/* Various very early CPU fix ups */
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switch (mfpvr() >> 16) {
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/*
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* PowerPC 970 CPUs have a misfeature requested by Apple that
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* makes them pretend they have a 32-byte cacheline. Turn this
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* off before we measure the cacheline size.
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*/
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case IBM970:
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case IBM970FX:
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case IBM970MP:
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case IBM970GX:
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scratch = mfspr(SPR_HID5);
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scratch &= ~HID5_970_DCBZ_SIZE_HI;
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mtspr(SPR_HID5, scratch);
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break;
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#ifdef __powerpc64__
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case IBMPOWER7:
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case IBMPOWER7PLUS:
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case IBMPOWER8:
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case IBMPOWER8E:
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/* XXX: get from ibm,slb-size in device tree */
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n_slbs = 32;
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break;
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#endif
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}
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/*
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* Initialize the interrupt tables and figure out our cache line
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* size and whether or not we need the 64-bit bridge code.
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*/
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/*
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* Disable translation in case the vector area hasn't been
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* mapped (G5). Note that no OFW calls can be made until
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* translation is re-enabled.
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*/
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msr = mfmsr();
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mtmsr((msr & ~(PSL_IR | PSL_DR)) | PSL_RI);
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/*
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* Measure the cacheline size using dcbz
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*
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* Use EXC_PGM as a playground. We are about to overwrite it
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* anyway, we know it exists, and we know it is cache-aligned.
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*/
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cache_check = (void *)EXC_PGM;
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for (cacheline_size = 0; cacheline_size < 0x100; cacheline_size++)
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cache_check[cacheline_size] = 0xff;
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__asm __volatile("dcbz 0,%0":: "r" (cache_check) : "memory");
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/* Find the first byte dcbz did not zero to get the cache line size */
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for (cacheline_size = 0; cacheline_size < 0x100 &&
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cache_check[cacheline_size] == 0; cacheline_size++);
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/* Work around psim bug */
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if (cacheline_size == 0) {
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cacheline_warn = 1;
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cacheline_size = 32;
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}
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#ifndef __powerpc64__
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/*
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* Figure out whether we need to use the 64 bit PMAP. This works by
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* executing an instruction that is only legal on 64-bit PPC (mtmsrd),
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* and setting ppc64 = 0 if that causes a trap.
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*/
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ppc64 = 1;
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bcopy(&testppc64, (void *)EXC_PGM, (size_t)&testppc64size);
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__syncicache((void *)EXC_PGM, (size_t)&testppc64size);
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__asm __volatile("\
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mfmsr %0; \
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mtsprg2 %1; \
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\
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mtmsrd %0; \
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mfsprg2 %1;"
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: "=r"(scratch), "=r"(ppc64));
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if (ppc64)
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cpu_features |= PPC_FEATURE_64;
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/*
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* Now copy restorebridge into all the handlers, if necessary,
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* and set up the trap tables.
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*/
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if (cpu_features & PPC_FEATURE_64) {
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/* Patch the two instances of rfi -> rfid */
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bcopy(&rfid_patch,&rfi_patch1,4);
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#ifdef KDB
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/* rfi_patch2 is at the end of dbleave */
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bcopy(&rfid_patch,&rfi_patch2,4);
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#endif
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}
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#else /* powerpc64 */
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cpu_features |= PPC_FEATURE_64;
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#endif
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trapsize = (size_t)&trapcodeend - (size_t)&trapcode;
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/*
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* Copy generic handler into every possible trap. Special cases will get
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* different ones in a minute.
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*/
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for (trap = EXC_RST; trap < EXC_LAST; trap += 0x20)
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bcopy(&trapcode, (void *)trap, trapsize);
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#ifndef __powerpc64__
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if (cpu_features & PPC_FEATURE_64) {
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/*
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* Copy a code snippet to restore 32-bit bridge mode
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* to the top of every non-generic trap handler
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*/
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trap_offset += (size_t)&restorebridgesize;
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bcopy(&restorebridge, (void *)EXC_RST, trap_offset);
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bcopy(&restorebridge, (void *)EXC_DSI, trap_offset);
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bcopy(&restorebridge, (void *)EXC_ALI, trap_offset);
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bcopy(&restorebridge, (void *)EXC_PGM, trap_offset);
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bcopy(&restorebridge, (void *)EXC_MCHK, trap_offset);
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bcopy(&restorebridge, (void *)EXC_TRC, trap_offset);
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bcopy(&restorebridge, (void *)EXC_BPT, trap_offset);
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}
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#endif
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bcopy(&rstcode, (void *)(EXC_RST + trap_offset), (size_t)&rstcodeend -
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(size_t)&rstcode);
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#ifdef KDB
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bcopy(&dblow, (void *)(EXC_MCHK + trap_offset), (size_t)&dbend -
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(size_t)&dblow);
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bcopy(&dblow, (void *)(EXC_PGM + trap_offset), (size_t)&dbend -
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(size_t)&dblow);
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bcopy(&dblow, (void *)(EXC_TRC + trap_offset), (size_t)&dbend -
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(size_t)&dblow);
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bcopy(&dblow, (void *)(EXC_BPT + trap_offset), (size_t)&dbend -
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(size_t)&dblow);
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#endif
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bcopy(&alitrap, (void *)(EXC_ALI + trap_offset), (size_t)&aliend -
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(size_t)&alitrap);
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bcopy(&dsitrap, (void *)(EXC_DSI + trap_offset), (size_t)&dsiend -
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(size_t)&dsitrap);
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#ifdef __powerpc64__
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/* Set TOC base so that the interrupt code can get at it */
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*((void **)TRAP_GENTRAP) = &generictrap;
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*((register_t *)TRAP_TOCBASE) = toc;
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bcopy(&slbtrap, (void *)EXC_DSE,(size_t)&slbtrapend - (size_t)&slbtrap);
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bcopy(&slbtrap, (void *)EXC_ISE,(size_t)&slbtrapend - (size_t)&slbtrap);
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#else
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/* Set branch address for trap code */
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if (cpu_features & PPC_FEATURE_64)
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*((void **)TRAP_GENTRAP) = &generictrap64;
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else
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*((void **)TRAP_GENTRAP) = &generictrap;
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*((void **)TRAP_TOCBASE) = _GLOBAL_OFFSET_TABLE_;
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/* G2-specific TLB miss helper handlers */
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bcopy(&imisstrap, (void *)EXC_IMISS, (size_t)&imisssize);
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bcopy(&dlmisstrap, (void *)EXC_DLMISS, (size_t)&dlmisssize);
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bcopy(&dsmisstrap, (void *)EXC_DSMISS, (size_t)&dsmisssize);
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#endif
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__syncicache(EXC_RSVD, EXC_LAST - EXC_RSVD);
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/*
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* Restore MSR
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*/
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mtmsr(msr);
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/* Warn if cachline size was not determined */
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if (cacheline_warn == 1) {
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printf("WARNING: cacheline size undetermined, setting to 32\n");
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}
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/*
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* Initialise virtual memory. Use BUS_PROBE_GENERIC priority
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* in case the platform module had a better idea of what we
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* should do.
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*/
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if (cpu_features & PPC_FEATURE_64)
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pmap_mmu_install(MMU_TYPE_G5, BUS_PROBE_GENERIC);
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else
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pmap_mmu_install(MMU_TYPE_OEA, BUS_PROBE_GENERIC);
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}
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/*
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* Shutdown the CPU as much as possible.
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*/
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void
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cpu_halt(void)
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{
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OF_exit();
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}
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int
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ptrace_single_step(struct thread *td)
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{
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struct trapframe *tf;
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tf = td->td_frame;
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tf->srr1 |= PSL_SE;
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return (0);
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}
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int
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ptrace_clear_single_step(struct thread *td)
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{
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struct trapframe *tf;
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tf = td->td_frame;
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tf->srr1 &= ~PSL_SE;
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return (0);
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}
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void
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kdb_cpu_clear_singlestep(void)
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{
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kdb_frame->srr1 &= ~PSL_SE;
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}
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void
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kdb_cpu_set_singlestep(void)
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{
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kdb_frame->srr1 |= PSL_SE;
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}
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/*
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* Initialise a struct pcpu.
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*/
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void
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cpu_pcpu_init(struct pcpu *pcpu, int cpuid, size_t sz)
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{
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#ifdef __powerpc64__
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/* Copy the SLB contents from the current CPU */
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memcpy(pcpu->pc_slb, PCPU_GET(slb), sizeof(pcpu->pc_slb));
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#endif
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}
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#ifndef __powerpc64__
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uint64_t
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va_to_vsid(pmap_t pm, vm_offset_t va)
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{
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return ((pm->pm_sr[(uintptr_t)va >> ADDR_SR_SHFT]) & SR_VSID_MASK);
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}
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#endif
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vm_offset_t
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pmap_early_io_map(vm_paddr_t pa, vm_size_t size)
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{
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return (pa);
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}
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/* From p3-53 of the MPC7450 RISC Microprocessor Family Reference Manual */
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void
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flush_disable_caches(void)
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{
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register_t msr;
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register_t msscr0;
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register_t cache_reg;
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volatile uint32_t *memp;
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uint32_t temp;
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int i;
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int x;
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msr = mfmsr();
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powerpc_sync();
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mtmsr(msr & ~(PSL_EE | PSL_DR));
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msscr0 = mfspr(SPR_MSSCR0);
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msscr0 &= ~MSSCR0_L2PFE;
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mtspr(SPR_MSSCR0, msscr0);
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powerpc_sync();
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isync();
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__asm__ __volatile__("dssall; sync");
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powerpc_sync();
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isync();
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__asm__ __volatile__("dcbf 0,%0" :: "r"(0));
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__asm__ __volatile__("dcbf 0,%0" :: "r"(0));
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__asm__ __volatile__("dcbf 0,%0" :: "r"(0));
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/* Lock the L1 Data cache. */
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mtspr(SPR_LDSTCR, mfspr(SPR_LDSTCR) | 0xFF);
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powerpc_sync();
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isync();
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mtspr(SPR_LDSTCR, 0);
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/*
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* Perform this in two stages: Flush the cache starting in RAM, then do it
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* from ROM.
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*/
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memp = (volatile uint32_t *)0x00000000;
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for (i = 0; i < 128 * 1024; i++) {
|
|
temp = *memp;
|
|
__asm__ __volatile__("dcbf 0,%0" :: "r"(memp));
|
|
memp += 32/sizeof(*memp);
|
|
}
|
|
|
|
memp = (volatile uint32_t *)0xfff00000;
|
|
x = 0xfe;
|
|
|
|
for (; x != 0xff;) {
|
|
mtspr(SPR_LDSTCR, x);
|
|
for (i = 0; i < 128; i++) {
|
|
temp = *memp;
|
|
__asm__ __volatile__("dcbf 0,%0" :: "r"(memp));
|
|
memp += 32/sizeof(*memp);
|
|
}
|
|
x = ((x << 1) | 1) & 0xff;
|
|
}
|
|
mtspr(SPR_LDSTCR, 0);
|
|
|
|
cache_reg = mfspr(SPR_L2CR);
|
|
if (cache_reg & L2CR_L2E) {
|
|
cache_reg &= ~(L2CR_L2IO_7450 | L2CR_L2DO_7450);
|
|
mtspr(SPR_L2CR, cache_reg);
|
|
powerpc_sync();
|
|
mtspr(SPR_L2CR, cache_reg | L2CR_L2HWF);
|
|
while (mfspr(SPR_L2CR) & L2CR_L2HWF)
|
|
; /* Busy wait for cache to flush */
|
|
powerpc_sync();
|
|
cache_reg &= ~L2CR_L2E;
|
|
mtspr(SPR_L2CR, cache_reg);
|
|
powerpc_sync();
|
|
mtspr(SPR_L2CR, cache_reg | L2CR_L2I);
|
|
powerpc_sync();
|
|
while (mfspr(SPR_L2CR) & L2CR_L2I)
|
|
; /* Busy wait for L2 cache invalidate */
|
|
powerpc_sync();
|
|
}
|
|
|
|
cache_reg = mfspr(SPR_L3CR);
|
|
if (cache_reg & L3CR_L3E) {
|
|
cache_reg &= ~(L3CR_L3IO | L3CR_L3DO);
|
|
mtspr(SPR_L3CR, cache_reg);
|
|
powerpc_sync();
|
|
mtspr(SPR_L3CR, cache_reg | L3CR_L3HWF);
|
|
while (mfspr(SPR_L3CR) & L3CR_L3HWF)
|
|
; /* Busy wait for cache to flush */
|
|
powerpc_sync();
|
|
cache_reg &= ~L3CR_L3E;
|
|
mtspr(SPR_L3CR, cache_reg);
|
|
powerpc_sync();
|
|
mtspr(SPR_L3CR, cache_reg | L3CR_L3I);
|
|
powerpc_sync();
|
|
while (mfspr(SPR_L3CR) & L3CR_L3I)
|
|
; /* Busy wait for L3 cache invalidate */
|
|
powerpc_sync();
|
|
}
|
|
|
|
mtspr(SPR_HID0, mfspr(SPR_HID0) & ~HID0_DCE);
|
|
powerpc_sync();
|
|
isync();
|
|
|
|
mtmsr(msr);
|
|
}
|
|
|
|
void
|
|
cpu_sleep()
|
|
{
|
|
static u_quad_t timebase = 0;
|
|
static register_t sprgs[4];
|
|
static register_t srrs[2];
|
|
|
|
jmp_buf resetjb;
|
|
struct thread *fputd;
|
|
struct thread *vectd;
|
|
register_t hid0;
|
|
register_t msr;
|
|
register_t saved_msr;
|
|
|
|
ap_pcpu = pcpup;
|
|
|
|
PCPU_SET(restore, &resetjb);
|
|
|
|
saved_msr = mfmsr();
|
|
fputd = PCPU_GET(fputhread);
|
|
vectd = PCPU_GET(vecthread);
|
|
if (fputd != NULL)
|
|
save_fpu(fputd);
|
|
if (vectd != NULL)
|
|
save_vec(vectd);
|
|
if (setjmp(resetjb) == 0) {
|
|
sprgs[0] = mfspr(SPR_SPRG0);
|
|
sprgs[1] = mfspr(SPR_SPRG1);
|
|
sprgs[2] = mfspr(SPR_SPRG2);
|
|
sprgs[3] = mfspr(SPR_SPRG3);
|
|
srrs[0] = mfspr(SPR_SRR0);
|
|
srrs[1] = mfspr(SPR_SRR1);
|
|
timebase = mftb();
|
|
powerpc_sync();
|
|
flush_disable_caches();
|
|
hid0 = mfspr(SPR_HID0);
|
|
hid0 = (hid0 & ~(HID0_DOZE | HID0_NAP)) | HID0_SLEEP;
|
|
powerpc_sync();
|
|
isync();
|
|
msr = mfmsr() | PSL_POW;
|
|
mtspr(SPR_HID0, hid0);
|
|
powerpc_sync();
|
|
|
|
while (1)
|
|
mtmsr(msr);
|
|
}
|
|
mttb(timebase);
|
|
PCPU_SET(curthread, curthread);
|
|
PCPU_SET(curpcb, curthread->td_pcb);
|
|
pmap_activate(curthread);
|
|
powerpc_sync();
|
|
mtspr(SPR_SPRG0, sprgs[0]);
|
|
mtspr(SPR_SPRG1, sprgs[1]);
|
|
mtspr(SPR_SPRG2, sprgs[2]);
|
|
mtspr(SPR_SPRG3, sprgs[3]);
|
|
mtspr(SPR_SRR0, srrs[0]);
|
|
mtspr(SPR_SRR1, srrs[1]);
|
|
mtmsr(saved_msr);
|
|
if (fputd == curthread)
|
|
enable_fpu(curthread);
|
|
if (vectd == curthread)
|
|
enable_vec(curthread);
|
|
powerpc_sync();
|
|
}
|
|
|