150 lines
6.4 KiB
C
150 lines
6.4 KiB
C
/* $Id$ */
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/* $NetBSD: espreg.h,v 1.2.4.1 1996/09/10 17:28:17 cgd Exp $ */
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/*
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* Copyright (c) 1994 Peter Galbavy. All rights reserved.
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Peter Galbavy.
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Register addresses, relative to some base address
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*/
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#define ESP_TCL 0x00 /* RW - Transfer Count Low */
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#define ESP_TCM 0x01 /* RW - Transfer Count Mid */
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#define ESP_TCH 0x0e /* RW - Transfer Count High */
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/* NOT on 53C90 */
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#define ESP_FIFO 0x02 /* RW - FIFO data */
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#define ESP_CMD 0x03 /* RW - Command (2 deep) */
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#define ESPCMD_DMA 0x80 /* DMA Bit */
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#define ESPCMD_NOP 0x00 /* No Operation */
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#define ESPCMD_FLUSH 0x01 /* Flush FIFO */
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#define ESPCMD_RSTCHIP 0x02 /* Reset Chip */
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#define ESPCMD_RSTSCSI 0x03 /* Reset SCSI Bus */
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#define ESPCMD_RESEL 0x40 /* Reselect Sequence */
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#define ESPCMD_SELNATN 0x41 /* Select without ATN */
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#define ESPCMD_SELATN 0x42 /* Select with ATN */
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#define ESPCMD_SELATNS 0x43 /* Select with ATN & Stop */
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#define ESPCMD_ENSEL 0x44 /* Enable (Re)Selection */
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#define ESPCMD_DISSEL 0x45 /* Disable (Re)Selection */
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#define ESPCMD_SELATN3 0x46 /* Select with ATN3 */
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#define ESPCMD_RESEL3 0x47 /* Reselect3 Sequence */
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#define ESPCMD_SNDMSG 0x20 /* Send Message */
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#define ESPCMD_SNDSTAT 0x21 /* Send Status */
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#define ESPCMD_SNDDATA 0x22 /* Send Data */
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#define ESPCMD_DISCSEQ 0x23 /* Disconnect Sequence */
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#define ESPCMD_TERMSEQ 0x24 /* Terminate Sequence */
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#define ESPCMD_TCCS 0x25 /* Target Command Comp Seq */
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#define ESPCMD_DISC 0x27 /* Disconnect */
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#define ESPCMD_RECMSG 0x28 /* Receive Message */
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#define ESPCMD_RECCMD 0x29 /* Receive Command */
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#define ESPCMD_RECDATA 0x2a /* Receive Data */
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#define ESPCMD_RECCSEQ 0x2b /* Receive Command Sequence*/
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#define ESPCMD_ABORT 0x04 /* Target Abort DMA */
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#define ESPCMD_TRANS 0x10 /* Transfer Information */
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#define ESPCMD_ICCS 0x11 /* Initiator Cmd Comp Seq */
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#define ESPCMD_MSGOK 0x12 /* Message Accepted */
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#define ESPCMD_TRPAD 0x18 /* Transfer Pad */
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#define ESPCMD_SETATN 0x1a /* Set ATN */
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#define ESPCMD_RSTATN 0x1b /* Reset ATN */
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#define ESP_STAT 0x04 /* RO - Status */
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#define ESPSTAT_INT 0x80 /* Interrupt */
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#define ESPSTAT_GE 0x40 /* Gross Error */
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#define ESPSTAT_PE 0x20 /* Parity Error */
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#define ESPSTAT_TC 0x10 /* Terminal Count */
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#define ESPSTAT_VGC 0x08 /* Valid Group Code */
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#define ESPSTAT_PHASE 0x07 /* Phase bits */
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#define ESP_SELID 0x04 /* WO - Select/Reselect Bus ID */
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#define ESP_INTR 0x05 /* RO - Interrupt */
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#define ESPINTR_SBR 0x80 /* SCSI Bus Reset */
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#define ESPINTR_ILL 0x40 /* Illegal Command */
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#define ESPINTR_DIS 0x20 /* Disconnect */
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#define ESPINTR_BS 0x10 /* Bus Service */
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#define ESPINTR_FC 0x08 /* Function Complete */
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#define ESPINTR_RESEL 0x04 /* Reselected */
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#define ESPINTR_SELATN 0x02 /* Select with ATN */
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#define ESPINTR_SEL 0x01 /* Selected */
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#define ESP_TIMEOUT 0x05 /* WO - Select/Reselect Timeout */
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#define ESP_STEP 0x06 /* RO - Sequence Step */
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#define ESPSTEP_MASK 0x07 /* the last 3 bits */
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#define ESPSTEP_DONE 0x04 /* command went out */
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#define ESP_SYNCTP 0x06 /* WO - Synch Transfer Period */
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/* Default 5 (53C9X) */
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#define ESP_FFLAG 0x07 /* RO - FIFO Flags */
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#define ESPFIFO_SS 0xe0 /* Sequence Step (Dup) */
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#define ESPFIFO_FF 0x1f /* Bytes in FIFO */
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#define ESP_SYNCOFF 0x07 /* WO - Synch Offset */
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/* 0 = ASYNC */
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/* 1 - 15 = SYNC bytes */
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#define ESP_CFG1 0x08 /* RW - Configuration #1 */
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#define ESPCFG1_SLOW 0x80 /* Slow Cable Mode */
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#define ESPCFG1_SRR 0x40 /* SCSI Reset Rep Int Dis */
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#define ESPCFG1_PTEST 0x20 /* Parity Test Mod */
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#define ESPCFG1_PARENB 0x10 /* Enable Parity Check */
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#define ESPCFG1_CTEST 0x08 /* Enable Chip Test */
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#define ESPCFG1_BUSID 0x07 /* Bus ID */
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#define ESP_CCF 0x09 /* WO - Clock Conversion Factor */
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/* 0 = 35.01 - 40Mhz */
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/* NEVER SET TO 1 */
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/* 2 = 10Mhz */
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/* 3 = 10.01 - 15Mhz */
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/* 4 = 15.01 - 20Mhz */
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/* 5 = 20.01 - 25Mhz */
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/* 6 = 25.01 - 30Mhz */
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/* 7 = 30.01 - 35Mhz */
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#define ESP_TEST 0x0a /* WO - Test (Chip Test Only) */
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#define ESP_CFG2 0x0b /* RW - Configuration #2 */
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#define ESPCFG2_RSVD 0xa0 /* reserved */
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#define ESPCFG2_FE 0x40 /* Features Enable */
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#define ESPCFG2_DREQ 0x10 /* DREQ High Impedance */
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#define ESPCFG2_SCSI2 0x08 /* SCSI-2 Enable */
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#define ESPCFG2_BPA 0x04 /* Target Bad Parity Abort */
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#define ESPCFG2_RPE 0x02 /* Register Parity Error */
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#define ESPCFG2_DPE 0x01 /* DMA Parity Error */
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/* Config #3 only on 53C9X */
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#define ESP_CFG3 0x0c /* RW - Configuration #3 */
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#define ESPCFG3_RSVD 0xe0 /* reserved */
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#define ESPCFG3_IDM 0x10 /* ID Message Res Check */
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#define ESPCFG3_QTE 0x08 /* Queue Tag Enable */
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#define ESPCFG3_CDB 0x04 /* CDB 10-bytes OK */
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#define ESPCFG3_FSCSI 0x02 /* Fast SCSI */
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#define ESPCFG3_FCLK 0x01 /* Fast Clock (>25Mhz) */
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