7453645f2a
All devices: - add support for rate adaptation via ieee80211_amrr(9); - use short preamble for transmitted frames when needed; - multi-bss support: * for RTL8821AU: 2 VAPs at the same time; * other: 1 any VAP + 1 sta VAP. RTL8188CE: - fix IQ calibration bug (reason of significant speed degradation); - add h/w crypto acceleration support. USB: - A-MPDU Tx support; - short GI support; Other: - add support for RTL8812AU / RTL8821AU chipsets (a/b/g/n only; no ac yet); - split merged code into subparts: * bus glue (usb/*, pci/*, rtl*/usb/*, rtl*/pci/*) * common (if_rtwn*) * chip-specific (rtl*/*) - various other bugfixes. Due to code reorganization, module names / requirements were changed too: urtwn urtwnfw -> rtwn rtwn_usb rtwnfw rtwn rtwnfw -> rtwn rtwn_pci rtwnfw Tested with RTL8188CE, RTL8188CUS, RTL8188EU and RTL8821AU. Tested by: kevlo, garga, Peter Garshtja <peter.garshtja@ambient-md.com>, Kevin McAleavey <kevin.mcaleavey@knosproject.com>, Ilias-Dimitrios Vrachnis <id@vrachnis.com>, <otacilio.neto@bsd.com.br> Relnotes: yes
150 lines
4.8 KiB
C
150 lines
4.8 KiB
C
/*-
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* Copyright (c) 2016 Andriy Voskoboinyk <avos@FreeBSD.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef R12A_TX_DESC_H
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#define R12A_TX_DESC_H
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/* Tx MAC descriptor (common part). */
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struct r12a_tx_desc {
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uint16_t pktlen;
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uint8_t offset;
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uint8_t flags0;
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#define R12A_FLAGS0_BMCAST 0x01
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#define R12A_FLAGS0_LSG 0x04
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#define R12A_FLAGS0_FSG 0x08
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#define R12A_FLAGS0_OWN 0x80
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uint32_t txdw1;
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#define R12A_TXDW1_MACID_M 0x0000003f
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#define R12A_TXDW1_MACID_S 0
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#define R12A_TXDW1_QSEL_M 0x00001f00
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#define R12A_TXDW1_QSEL_S 8
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#define R12A_TXDW1_QSEL_BE 0x00 /* or 0x03 */
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#define R12A_TXDW1_QSEL_BK 0x01 /* or 0x02 */
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#define R12A_TXDW1_QSEL_VI 0x04 /* or 0x05 */
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#define R12A_TXDW1_QSEL_VO 0x06 /* or 0x07 */
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#define RTWN_MAX_TID 8
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#define R12A_TXDW1_QSEL_BEACON 0x10
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#define R12A_TXDW1_QSEL_MGNT 0x12
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#define R12A_TXDW1_RAID_M 0x001f0000
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#define R12A_TXDW1_RAID_S 16
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#define R12A_TXDW1_CIPHER_M 0x00c00000
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#define R12A_TXDW1_CIPHER_S 22
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#define R12A_TXDW1_CIPHER_NONE 0
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#define R12A_TXDW1_CIPHER_RC4 1
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#define R12A_TXDW1_CIPHER_SM4 2
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#define R12A_TXDW1_CIPHER_AES 3
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#define R12A_TXDW1_PKTOFF_M 0x1f000000
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#define R12A_TXDW1_PKTOFF_S 24
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uint32_t txdw2;
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#define R12A_TXDW2_AGGEN 0x00001000
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#define R12A_TXDW2_AGGBK 0x00010000
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#define R12A_TXDW2_MOREFRAG 0x00020000
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#define R12A_TXDW2_SPE_RPT 0x00080000
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#define R12A_TXDW2_AMPDU_DEN_M 0x00700000
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#define R12A_TXDW2_AMPDU_DEN_S 20
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uint32_t txdw3;
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#define R12A_TXDW3_SEQ_SEL_M 0x000000c0
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#define R12A_TXDW3_SEQ_SEL_S 6
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#define R12A_TXDW3_DRVRATE 0x00000100
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#define R12A_TXDW3_DISRTSFB 0x00000200
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#define R12A_TXDW3_DISDATAFB 0x00000400
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#define R12A_TXDW3_CTS2SELF 0x00000800
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#define R12A_TXDW3_RTSEN 0x00001000
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#define R12A_TXDW3_HWRTSEN 0x00002000
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#define R12A_TXDW3_MAX_AGG_M 0x003e0000
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#define R12A_TXDW3_MAX_AGG_S 17
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uint32_t txdw4;
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#define R12A_TXDW4_DATARATE_M 0x0000007f
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#define R12A_TXDW4_DATARATE_S 0
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#define R12A_TXDW4_DATARATE_FB_LMT_M 0x00001f00
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#define R12A_TXDW4_DATARATE_FB_LMT_S 8
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#define R12A_TXDW4_RTSRATE_FB_LMT_M 0x0001e000
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#define R12A_TXDW4_RTSRATE_FB_LMT_S 13
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#define R12A_TXDW4_RETRY_LMT_ENA 0x00020000
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#define R12A_TXDW4_RETRY_LMT_M 0x00fc0000
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#define R12A_TXDW4_RETRY_LMT_S 18
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#define R12A_TXDW4_RTSRATE_M 0x1f000000
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#define R12A_TXDW4_RTSRATE_S 24
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uint32_t txdw5;
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#define R12A_TXDW5_DATA_PRIM_CHAN_M 0x0000000f
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#define R12A_TXDW5_DATA_PRIM_CHAN_S 0
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#define R12A_TXDW5_PRIM_CHAN_20_80_3 1
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#define R12A_TXDW5_PRIM_CHAN_20_80_2 2
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#define R12A_TXDW5_PRIM_CHAN_20_80_4 3
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#define R12A_TXDW5_PRIM_CHAN_20_80_1 4
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#define R12A_TXDW5_PRIM_CHAN_40_80_1 9
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#define R12A_TXDW5_PRIM_CHAN_40_80_2 10
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#define R12A_TXDW5_DATA_SHORT 0x00000010
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#define R12A_TXDW5_DATA_BW_M 0x00000060
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#define R12A_TXDW5_DATA_BW_S 5
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#define R12A_TXDW5_DATA_BW40 1
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#define R12A_TXDW5_DATA_BW80 2
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#define R12A_TXDW5_DATA_LDPC 0x00000080
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#define R12A_TXDW5_RTS_SHORT 0x00001000
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#define R12A_TXDW5_RTS_PRIM_CHAN_M 0x0001e000
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#define R12A_TXDW5_RTS_PRIM_CHAN_S 13
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uint32_t txdw6;
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#define R21A_TXDW6_MBSSID_M 0x0000f000
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#define R21A_TXDW6_MBSSID_S 12
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uint32_t reserved;
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uint32_t txdw8;
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#define R12A_TXDW8_HWSEQ_EN 0x00008000
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uint32_t txdw9;
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#define R12A_TXDW9_SEQ_M 0x00fff000
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#define R12A_TXDW9_SEQ_S 12
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} __packed __attribute__((aligned(4)));
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/* Rate adaptation modes. */
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#define R12A_RAID_11BGN_2_40 0
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#define R12A_RAID_11BGN_1_40 1
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#define R12A_RAID_11BGN_2 2
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#define R12A_RAID_11BGN_1 3
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#define R12A_RAID_11GN_2 4
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#define R12A_RAID_11GN_1 5
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#define R12A_RAID_11BG 6
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#define R12A_RAID_11G 7 /* "pure" 11g */
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#define R12A_RAID_11B 8
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#define R12A_RAID_11AC_2_80 9
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#define R12A_RAID_11AC_1_80 10
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#define R12A_RAID_11AC_1 11
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#define R12A_RAID_11AC_2 12
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#endif /* R12A_TX_DESC_H */
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