7847079929
handle the minor (but significant) differences between the various Vortex chips; add (incomplete) support for playback.
179 lines
4.9 KiB
C
179 lines
4.9 KiB
C
/*-
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* Copyright (c) 2003 Dag-Erling Coïdan Smørgrav
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer
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* in this position and unchanged.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _AU88X0_H_INCLUDED
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#define _AU88X0_H_INCLUDED
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/*
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* Chipset parameters
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*/
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struct au88x0_chipset {
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const char *auc_name;
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uint32_t auc_pci_id;
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/* General control register */
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uint32_t auc_control;
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#define AU88X0_CTL_MIDI_ENABLE 0x0001
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#define AU88X0_CTL_GAME_ENABLE 0x0008
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#define AU88X0_CTL_IRQ_ENABLE 0x4000
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/* IRQ control register */
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uint32_t auc_irq_source;
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#define AU88X0_IRQ_FATAL_ERR 0x0001
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#define AU88X0_IRQ_PARITY_ERR 0x0002
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#define AU88X0_IRQ_REG_ERR 0x0004
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#define AU88X0_IRQ_FIFO_ERR 0x0008
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#define AU88X0_IRQ_DMA_ERR 0x0010
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#define AU88X0_IRQ_PCMOUT 0x0020
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#define AU88X0_IRQ_TIMER 0x1000
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#define AU88X0_IRQ_MIDI 0x2000
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#define AU88X0_IRQ_MODEM 0x4000
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uint32_t auc_irq_mask;
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uint32_t auc_irq_control;
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#define AU88X0_IRQ_PENDING_BIT 0x0001
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uint32_t auc_irq_status;
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/* DMA control registers */
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uint32_t auc_dma_control;
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/* FIFOs */
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int auc_fifo_size;
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int auc_wt_fifos;
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uint32_t auc_wt_fifo_base;
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uint32_t auc_wt_fifo_ctl;
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uint32_t auc_wt_dma_ctl;
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int auc_adb_fifos;
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uint32_t auc_adb_fifo_base;
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uint32_t auc_adb_fifo_ctl;
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uint32_t auc_adb_dma_ctl;
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/* Routing */
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uint32_t auc_adb_route_base;
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int auc_adb_route_bits;
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int auc_adb_codec_in;
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int auc_adb_codec_out;
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};
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/*
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* Channel information
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*/
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struct au88x0_chan_info {
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struct au88x0_info *auci_aui;
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struct pcm_channel *auci_pcmchan;
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struct snd_dbuf *auci_buf;
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int auci_dir;
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};
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/*
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* Device information
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*/
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struct au88x0_info {
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/* the device we're associated with */
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device_t aui_dev;
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uint32_t aui_model;
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struct au88x0_chipset *aui_chipset;
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/* parameters */
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bus_size_t aui_bufsize;
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int aui_wt_fifos;
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int aui_wt_fifo_ctl;
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int aui_adb_fifos;
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int aui_adb_fifo_ctl;
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int aui_fifo_size;
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uint32_t aui_chanbase;
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/* bus_space tag and handle */
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bus_space_tag_t aui_spct;
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bus_space_handle_t aui_spch;
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/* register space */
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int aui_regtype;
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int aui_regid;
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struct resource *aui_reg;
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/* irq */
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int aui_irqtype;
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int aui_irqid;
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struct resource *aui_irq;
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void *aui_irqh;
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/* dma */
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bus_dma_tag_t aui_dmat;
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/* codec */
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struct ac97_info *aui_ac97i;
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/* channels */
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struct au88x0_chan_info aui_chan[2];
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};
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/*
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* Common parameters
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*/
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#define AU88X0_SETTLE_DELAY 1000
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#define AU88X0_RETRY_COUNT 10
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#define AU88X0_BUFSIZE_MIN 0x1000
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#define AU88X0_BUFSIZE_DFLT 0x4000
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#define AU88X0_BUFSIZE_MAX 0x4000
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/*
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* Codec control registers
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*
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* AU88X0_CODEC_CHANNEL array of 32 32-bit words
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*
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* AU88X0_CODEC_CONTROL control register
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*
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* bit 16 ready
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*
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* AU88X0_CODEC_IO I/O register
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*
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* bits 0-15 contents of codec register
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* bits 16-22 address of codec register
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* bit 23 0 for read, 1 for write
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*/
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#define AU88X0_CODEC_CHANNEL 0x29080
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#define AU88X0_CODEC_CONTROL 0x29184
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#define AU88X0_CDCTL_WROK 0x00000100
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#define AU88X0_CODEC_IO 0x29188
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#define AU88X0_CDIO_DATA_SHIFT 0
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#define AU88X0_CDIO_DATA_MASK 0x0000ffff
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#define AU88X0_CDIO_ADDR_SHIFT 16
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#define AU88X0_CDIO_ADDR_MASK 0x007f0000
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#define AU88X0_CDIO_RDBIT 0x00000000
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#define AU88X0_CDIO_WRBIT 0x00800000
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#define AU88X0_CDIO_READ(a) (AU88X0_CDIO_RDBIT | \
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(((a) << AU88X0_CDIO_ADDR_SHIFT) & AU88X0_CDIO_ADDR_MASK))
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#define AU88X0_CDIO_WRITE(a, d) (AU88X0_CDIO_WRBIT | \
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(((a) << AU88X0_CDIO_ADDR_SHIFT) & AU88X0_CDIO_ADDR_MASK) | \
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(((d) << AU88X0_CDIO_DATA_SHIFT) & AU88X0_CDIO_DATA_MASK))
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#define AU88X0_CODEC_ENABLE 0x29190
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#endif
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