50a9f1c71c
This fine work was done by Yohanes Nugroho <yohanes a gmail dot com> Many thanks to John Nicholls and Thinlinx for providing sample hardware.
107 lines
2.4 KiB
C
107 lines
2.4 KiB
C
/*
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* $FreeBSD$
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*/
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#ifndef MACB_REG_H
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#define MACB_REG_H
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#define EMAC_NCR 0x00
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#define EMAC_NCFGR 0x04
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#define EMAC_TSR 0x14
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#define EMAC_RSR 0x20
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#define EMAC_ISR 0x24
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#define EMAC_IER 0x28
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#define EMAC_IDR 0x2C
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#define EMAC_IMR 0x30
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#define EMAC_RBQP 0x18
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#define EMAC_TBQP 0x1C
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#define EMAC_HRB 0x90
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#define EMAC_HRT 0x94
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#define EMAC_SA1B 0x98
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#define EMAC_SA1T 0x9C
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#define EMAC_USRIO 0xC0
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#define EMAC_MAN 0x34 /* EMAC PHY Maintenance Register */
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#define EMAC_SR 0x08 /* EMAC STatus Register */
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#define EMAC_SR_LINK (1U << 0) /* Reserved! */
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#define EMAC_SR_MDIO (1U << 1) /* MDIO pin status */
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#define EMAC_SR_IDLE (1U << 2) /* IDLE (PHY logic) */
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#define RX_ENABLE (1 << 2)
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#define TX_ENABLE (1 << 3)
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#define MPE_ENABLE (1 << 4)
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/* EMAC_MAN */
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#define EMAC_MAN_BITS 0x40020000 /* HIGH and CODE bits */
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#define EMAC_MAN_READ (2U << 28)
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#define EMAC_MAN_WRITE (1U << 28)
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#define EMAC_MAN_PHYA_BIT 23
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#define EMAC_MAN_REGA_BIT 18
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#define EMAC_MAN_VALUE_MASK 0xffffU
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#define EMAC_MAN_REG_WR(phy, reg, val) \
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(EMAC_MAN_BITS | EMAC_MAN_WRITE | ((phy) << EMAC_MAN_PHYA_BIT) | \
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((reg) << EMAC_MAN_REGA_BIT) | ((val) & EMAC_MAN_VALUE_MASK))
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#define EMAC_MAN_REG_RD(phy, reg) \
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(EMAC_MAN_BITS | EMAC_MAN_READ | ((phy) << EMAC_MAN_PHYA_BIT) | \
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((reg) << EMAC_MAN_REGA_BIT))
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#define RCOMP_INTERRUPT (1 << 1)
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#define RXUBR_INTERRUPT (1 << 2)
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#define TUBR_INTERRUPT (1 << 3)
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#define TUND_INTERRUPT (1 << 4)
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#define RLE_INTERRUPT (1 << 5)
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#define TXERR_INTERRUPT (1 << 6)
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#define ROVR_INTERRUPT (1 << 10)
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#define HRESP_INTERRUPT (1 << 11)
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#define TCOMP_INTERRUPT (1 << 7)
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#define CLEAR_STAT (1 << 5)
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#define TRANSMIT_START (1 << 9)
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#define TRANSMIT_STOP (1 << 10)
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/*Transmit status register flags*/
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#define TSR_UND (1 << 6)
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#define TSR_COMP (1 << 5)
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#define TSR_BEX (1 << 4)
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#define TSR_TGO (1 << 3)
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#define TSR_RLE (1 << 2)
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#define TSR_COL (1 << 1)
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#define TSR_UBR (1 << 0)
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#define CFG_SPD (1 << 0)
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#define CFG_FD (1 << 1)
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#define CFG_CAF (1 << 4)
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#define CFG_NBC (1 << 5)
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#define CFG_MTI (1 << 6)
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#define CFG_UNI (1 << 7)
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#define CFG_BIG (1 << 8)
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#define CFG_CLK_8 (0)
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#define CFG_CLK_16 (1)
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#define CFG_CLK_32 (2)
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#define CFG_CLK_64 (3)
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#define CFG_PAE (1 << 13)
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#define CFG_RBOF_0 (0 << 14)
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#define CFG_RBOF_1 (1 << 14)
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#define CFG_RBOF_2 (2 << 14)
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#define CFG_RBOF_3 (3 << 14)
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#define CFG_DRFCS (1 << 17)
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#define USRIO_CLOCK (1 << 1)
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#endif
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