9efd0ba788
Add support for pci deviceID 0x8070 for QLE41xxx product line which supports 10GbE/25GbE/40GbE MFC after:5 days
390 lines
11 KiB
C
390 lines
11 KiB
C
/*
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* Copyright (c) 2017-2018 Cavium, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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* $FreeBSD$
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*
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*/
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#ifndef __ECORE_RDMA_H__
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#define __ECORE_RDMA_H__
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#include "ecore_status.h"
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#include "ecore.h"
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#include "ecore_hsi_common.h"
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#include "ecore_proto_if.h"
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#include "ecore_roce_api.h"
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#include "ecore_dev_api.h"
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/* Constants */
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/* HW/FW RoCE Limitations (internal. For external see ecore_rdma_api.h) */
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#define ECORE_RDMA_MAX_FMR (RDMA_MAX_TIDS) /* 2^17 - 1 */
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#define ECORE_RDMA_MAX_P_KEY (1)
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#define ECORE_RDMA_MAX_WQE (0x7FFF) /* 2^15 -1 */
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#define ECORE_RDMA_MAX_SRQ_WQE_ELEM (0x7FFF) /* 2^15 -1 */
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#define ECORE_RDMA_PAGE_SIZE_CAPS (0xFFFFF000) /* TODO: > 4k?! */
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#define ECORE_RDMA_ACK_DELAY (15) /* 131 milliseconds */
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#define ECORE_RDMA_MAX_MR_SIZE (0x10000000000ULL) /* 2^40 */
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#define ECORE_RDMA_MAX_CQS (RDMA_MAX_CQS) /* 64k */
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#define ECORE_RDMA_MAX_MRS (RDMA_MAX_TIDS) /* 2^17 - 1 */
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/* Add 1 for header element */
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#define ECORE_RDMA_MAX_SRQ_ELEM_PER_WQE (RDMA_MAX_SGE_PER_RQ_WQE + 1)
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#define ECORE_RDMA_MAX_SGE_PER_SRQ_WQE (RDMA_MAX_SGE_PER_RQ_WQE)
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#define ECORE_RDMA_SRQ_WQE_ELEM_SIZE (16)
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#define ECORE_RDMA_MAX_SRQS (32 * 1024) /* 32k */
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/* Configurable */
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/* Max CQE is derived from u16/32 size, halved and decremented by 1 to handle
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* wrap properly and then decremented by 1 again. The latter decrement comes
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* from a requirement to create a chain that is bigger than what the user
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* requested by one:
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* The CQE size is 32 bytes but the FW writes in chunks of 64
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* bytes, for performance purposes. Allocating an extra entry and telling the
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* FW we have less prevents overwriting the first entry in case of a wrap i.e.
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* when the FW writes the last entry and the application hasn't read the first
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* one.
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*/
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#define ECORE_RDMA_MAX_CQE_32_BIT (0x7FFFFFFF - 1)
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#define ECORE_RDMA_MAX_CQE_16_BIT (0x7FFF - 1)
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enum ecore_rdma_toggle_bit {
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ECORE_RDMA_TOGGLE_BIT_CLEAR = 0,
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ECORE_RDMA_TOGGLE_BIT_SET = 1
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};
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/* @@@TBD Currently we support only affilited events
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* enum ecore_rdma_unaffiliated_event_code {
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* ECORE_RDMA_PORT_ACTIVE, // Link Up
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* ECORE_RDMA_PORT_CHANGED, // SGID table has changed
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* ECORE_RDMA_LOCAL_CATASTROPHIC_ERR, // Fatal device error
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* ECORE_RDMA_PORT_ERR, // Link down
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* };
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*/
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#define QEDR_MAX_BMAP_NAME (10)
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struct ecore_bmap {
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u32 max_count;
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unsigned long *bitmap;
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char name[QEDR_MAX_BMAP_NAME];
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};
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/* functions for enabling/disabling edpm in rdma PFs according to existence of
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* qps during DCBx update or bar size
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*/
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void ecore_roce_dpm_dcbx(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt);
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void ecore_rdma_dpm_bar(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt);
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#ifdef CONFIG_ECORE_IWARP
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#define ECORE_IWARP_PREALLOC_CNT (256)
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#define ECORE_IWARP_LL2_SYN_TX_SIZE (128)
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#define ECORE_IWARP_LL2_SYN_RX_SIZE (256)
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#define ECORE_IWARP_LL2_OOO_DEF_TX_SIZE (256)
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#define ECORE_IWARP_LL2_OOO_DEF_RX_SIZE (4096)
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#define ECORE_IWARP_LL2_OOO_MAX_RX_SIZE (16384)
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#define ECORE_IWARP_MAX_SYN_PKT_SIZE (128)
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#define ECORE_IWARP_HANDLE_INVAL (0xff)
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struct ecore_iwarp_ll2_buff {
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struct ecore_iwarp_ll2_buff *piggy_buf;
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void *data;
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dma_addr_t data_phys_addr;
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u32 buff_size;
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};
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struct ecore_iwarp_ll2_mpa_buf {
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osal_list_entry_t list_entry;
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struct ecore_iwarp_ll2_buff *ll2_buf;
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struct unaligned_opaque_data data;
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u16 tcp_payload_len;
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u8 placement_offset;
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};
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/* In some cases a fpdu will arrive with only one byte of the header, in this
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* case the fpdu_length will be partial ( contain only higher byte and
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* incomplete bytes will contain the invalid value */
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#define ECORE_IWARP_INVALID_INCOMPLETE_BYTES 0xffff
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struct ecore_iwarp_fpdu {
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struct ecore_iwarp_ll2_buff *mpa_buf;
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dma_addr_t pkt_hdr;
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u8 pkt_hdr_size;
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dma_addr_t mpa_frag;
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void *mpa_frag_virt;
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u16 mpa_frag_len;
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u16 fpdu_length;
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u16 incomplete_bytes;
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};
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struct ecore_iwarp_info {
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osal_list_t listen_list; /* ecore_iwarp_listener */
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osal_list_t ep_list; /* ecore_iwarp_ep */
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osal_list_t ep_free_list;/* pre-allocated ep's */
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osal_list_t mpa_buf_list;/* list of mpa_bufs */
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osal_list_t mpa_buf_pending_list;
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osal_spinlock_t iw_lock;
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osal_spinlock_t qp_lock; /* for teardown races */
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struct iwarp_rxmit_stats_drv stats;
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u32 rcv_wnd_scale;
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u16 max_mtu;
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u16 num_ooo_rx_bufs;
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u8 mac_addr[ETH_ALEN];
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u8 crc_needed;
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u8 tcp_flags;
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u8 ll2_syn_handle;
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u8 ll2_ooo_handle;
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u8 ll2_mpa_handle;
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u8 peer2peer;
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u8 _pad;
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enum mpa_negotiation_mode mpa_rev;
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enum mpa_rtr_type rtr_type;
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struct ecore_iwarp_fpdu *partial_fpdus;
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struct ecore_iwarp_ll2_mpa_buf *mpa_bufs;
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u8 *mpa_intermediate_buf;
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u16 max_num_partial_fpdus;
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/* MPA statistics */
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u64 unalign_rx_comp;
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};
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#endif
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#define IS_ECORE_DCQCN(p_hwfn) \
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(!!(p_hwfn->pf_params.rdma_pf_params.enable_dcqcn))
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struct ecore_roce_info {
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struct roce_events_stats event_stats;
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u8 dcqcn_enabled;
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u8 dcqcn_reaction_point;
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};
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struct ecore_rdma_info {
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osal_spinlock_t lock;
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struct ecore_bmap cq_map;
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struct ecore_bmap pd_map;
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struct ecore_bmap tid_map;
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struct ecore_bmap srq_map;
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struct ecore_bmap cid_map;
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struct ecore_bmap tcp_cid_map;
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struct ecore_bmap real_cid_map;
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struct ecore_bmap dpi_map;
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struct ecore_bmap toggle_bits;
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struct ecore_rdma_events events;
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struct ecore_rdma_device *dev;
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struct ecore_rdma_port *port;
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u32 last_tid;
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u8 num_cnqs;
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struct rdma_sent_stats rdma_sent_pstats;
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struct rdma_rcv_stats rdma_rcv_tstats;
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u32 num_qps;
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u32 num_mrs;
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u32 num_srqs;
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u16 queue_zone_base;
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u16 max_queue_zones;
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enum protocol_type proto;
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struct ecore_roce_info roce;
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#ifdef CONFIG_ECORE_IWARP
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struct ecore_iwarp_info iwarp;
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#endif
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};
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#ifdef CONFIG_ECORE_IWARP
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enum ecore_iwarp_qp_state {
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ECORE_IWARP_QP_STATE_IDLE,
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ECORE_IWARP_QP_STATE_RTS,
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ECORE_IWARP_QP_STATE_TERMINATE,
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ECORE_IWARP_QP_STATE_CLOSING,
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ECORE_IWARP_QP_STATE_ERROR,
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};
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#endif
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struct ecore_rdma_qp {
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struct regpair qp_handle;
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struct regpair qp_handle_async;
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u32 qpid; /* iwarp: may differ from icid */
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u16 icid;
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enum ecore_roce_qp_state cur_state;
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#ifdef CONFIG_ECORE_IWARP
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enum ecore_iwarp_qp_state iwarp_state;
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#endif
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bool use_srq;
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bool signal_all;
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bool fmr_and_reserved_lkey;
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bool incoming_rdma_read_en;
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bool incoming_rdma_write_en;
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bool incoming_atomic_en;
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bool e2e_flow_control_en;
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u16 pd; /* Protection domain */
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u16 pkey; /* Primary P_key index */
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u32 dest_qp;
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u16 mtu;
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u16 srq_id;
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u8 traffic_class_tos; /* IPv6/GRH traffic class; IPv4 TOS */
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u8 hop_limit_ttl; /* IPv6/GRH hop limit; IPv4 TTL */
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u16 dpi;
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u32 flow_label; /* ignored in IPv4 */
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u16 vlan_id;
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u32 ack_timeout;
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u8 retry_cnt;
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u8 rnr_retry_cnt;
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u8 min_rnr_nak_timer;
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bool sqd_async;
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union ecore_gid sgid; /* GRH SGID; IPv4/6 Source IP */
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union ecore_gid dgid; /* GRH DGID; IPv4/6 Destination IP */
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enum roce_mode roce_mode;
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u16 udp_src_port; /* RoCEv2 only */
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u8 stats_queue;
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/* requeseter */
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u8 max_rd_atomic_req;
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u32 sq_psn;
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u16 sq_cq_id; /* The cq to be associated with the send queue*/
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u16 sq_num_pages;
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dma_addr_t sq_pbl_ptr;
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void *orq;
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dma_addr_t orq_phys_addr;
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u8 orq_num_pages;
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bool req_offloaded;
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/* responder */
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u8 max_rd_atomic_resp;
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u32 rq_psn;
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u16 rq_cq_id; /* The cq to be associated with the receive queue */
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u16 rq_num_pages;
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dma_addr_t rq_pbl_ptr;
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void *irq;
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dma_addr_t irq_phys_addr;
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u8 irq_num_pages;
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bool resp_offloaded;
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u32 cq_prod;
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u8 remote_mac_addr[6];
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u8 local_mac_addr[6];
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void *shared_queue;
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dma_addr_t shared_queue_phys_addr;
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#ifdef CONFIG_ECORE_IWARP
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struct ecore_iwarp_ep *ep;
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#endif
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};
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#ifdef CONFIG_ECORE_IWARP
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enum ecore_iwarp_ep_state {
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ECORE_IWARP_EP_INIT,
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ECORE_IWARP_EP_MPA_REQ_RCVD,
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ECORE_IWARP_EP_ESTABLISHED,
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ECORE_IWARP_EP_CLOSED
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};
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union async_output {
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struct iwarp_eqe_data_mpa_async_completion mpa_response;
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struct iwarp_eqe_data_tcp_async_completion mpa_request;
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};
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#define ECORE_MAX_PRIV_DATA_LEN (512)
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struct ecore_iwarp_ep_memory {
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u8 in_pdata[ECORE_MAX_PRIV_DATA_LEN];
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u8 out_pdata[ECORE_MAX_PRIV_DATA_LEN];
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union async_output async_output;
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};
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/* Endpoint structure represents a TCP connection. This connection can be
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* associated with a QP or not (in which case QP==NULL)
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*/
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struct ecore_iwarp_ep {
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osal_list_entry_t list_entry;
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int sig;
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struct ecore_rdma_qp *qp;
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enum ecore_iwarp_ep_state state;
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/* This contains entire buffer required for ep memories. This is the
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* only one actually allocated and freed. The rest are pointers into
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* this buffer
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*/
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struct ecore_iwarp_ep_memory *ep_buffer_virt;
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dma_addr_t ep_buffer_phys;
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struct ecore_iwarp_cm_info cm_info;
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enum tcp_connect_mode connect_mode;
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enum mpa_rtr_type rtr_type;
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enum mpa_negotiation_mode mpa_rev;
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u32 tcp_cid;
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u32 cid;
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u8 remote_mac_addr[6];
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u8 local_mac_addr[6];
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u16 mss;
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bool mpa_reply_processed;
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/* The event_cb function is called for asynchrounous events associated
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* with the ep. It is initialized at different entry points depending
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* on whether the ep is the tcp connection active side or passive side
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* The cb_context is passed to the event_cb function.
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*/
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iwarp_event_handler event_cb;
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void *cb_context;
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/* For Passive side - syn packet related data */
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struct ecore_iwarp_ll2_buff *syn;
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u16 syn_ip_payload_length;
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dma_addr_t syn_phy_addr;
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};
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struct ecore_iwarp_listener {
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osal_list_entry_t list_entry;
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/* The event_cb function is called for connection requests.
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* The cb_context is passed to the event_cb function.
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*/
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iwarp_event_handler event_cb;
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void *cb_context;
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u32 max_backlog;
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u8 ip_version;
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u32 ip_addr[4];
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u16 port;
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u16 vlan;
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};
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void ecore_iwarp_async_event(struct ecore_hwfn *p_hwfn,
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u8 fw_event_code,
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struct regpair *fw_handle,
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u8 fw_return_code);
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#endif /* CONFIG_ECORE_IWARP */
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void ecore_roce_async_event(struct ecore_hwfn *p_hwfn,
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u8 fw_event_code,
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union rdma_eqe_data *rdma_data);
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#endif /*__ECORE_RDMA_H__*/
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